1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #ifdef CONFIG_X86 27 #include <asm/hypervisor.h> 28 #endif 29 30 #include <drm/drm_drv.h> 31 #include <xen/xen.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "vi.h" 36 #include "soc15.h" 37 #include "nv.h" 38 39 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 40 do { \ 41 vf2pf_info->ucode_info[ucode].id = ucode; \ 42 vf2pf_info->ucode_info[ucode].version = ver; \ 43 } while (0) 44 45 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 46 { 47 /* By now all MMIO pages except mailbox are blocked */ 48 /* if blocking is enabled in hypervisor. Choose the */ 49 /* SCRATCH_REG0 to test. */ 50 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 51 } 52 53 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 54 { 55 struct drm_device *ddev = adev_to_drm(adev); 56 57 /* enable virtual display */ 58 if (adev->asic_type != CHIP_ALDEBARAN && 59 adev->asic_type != CHIP_ARCTURUS && 60 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { 61 if (adev->mode_info.num_crtc == 0) 62 adev->mode_info.num_crtc = 1; 63 adev->enable_virtual_display = true; 64 } 65 ddev->driver_features &= ~DRIVER_ATOMIC; 66 adev->cg_flags = 0; 67 adev->pg_flags = 0; 68 69 /* enable mcbp for sriov */ 70 amdgpu_mcbp = 1; 71 72 /* Reduce kcq number to 2 to reduce latency */ 73 if (amdgpu_num_kcq == -1) 74 amdgpu_num_kcq = 2; 75 } 76 77 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 78 uint32_t reg0, uint32_t reg1, 79 uint32_t ref, uint32_t mask) 80 { 81 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 82 struct amdgpu_ring *ring = &kiq->ring; 83 signed long r, cnt = 0; 84 unsigned long flags; 85 uint32_t seq; 86 87 if (adev->mes.ring.sched.ready) { 88 amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1, 89 ref, mask); 90 return; 91 } 92 93 spin_lock_irqsave(&kiq->ring_lock, flags); 94 amdgpu_ring_alloc(ring, 32); 95 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, 96 ref, mask); 97 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 98 if (r) 99 goto failed_undo; 100 101 amdgpu_ring_commit(ring); 102 spin_unlock_irqrestore(&kiq->ring_lock, flags); 103 104 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 105 106 /* don't wait anymore for IRQ context */ 107 if (r < 1 && in_interrupt()) 108 goto failed_kiq; 109 110 might_sleep(); 111 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 112 113 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 114 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 115 } 116 117 if (cnt > MAX_KIQ_REG_TRY) 118 goto failed_kiq; 119 120 return; 121 122 failed_undo: 123 amdgpu_ring_undo(ring); 124 spin_unlock_irqrestore(&kiq->ring_lock, flags); 125 failed_kiq: 126 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1); 127 } 128 129 /** 130 * amdgpu_virt_request_full_gpu() - request full gpu access 131 * @adev: amdgpu device. 132 * @init: is driver init time. 133 * When start to init/fini driver, first need to request full gpu access. 134 * Return: Zero if request success, otherwise will return error. 135 */ 136 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 137 { 138 struct amdgpu_virt *virt = &adev->virt; 139 int r; 140 141 if (virt->ops && virt->ops->req_full_gpu) { 142 r = virt->ops->req_full_gpu(adev, init); 143 if (r) 144 return r; 145 146 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 147 } 148 149 return 0; 150 } 151 152 /** 153 * amdgpu_virt_release_full_gpu() - release full gpu access 154 * @adev: amdgpu device. 155 * @init: is driver init time. 156 * When finishing driver init/fini, need to release full gpu access. 157 * Return: Zero if release success, otherwise will returen error. 158 */ 159 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 160 { 161 struct amdgpu_virt *virt = &adev->virt; 162 int r; 163 164 if (virt->ops && virt->ops->rel_full_gpu) { 165 r = virt->ops->rel_full_gpu(adev, init); 166 if (r) 167 return r; 168 169 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 170 } 171 return 0; 172 } 173 174 /** 175 * amdgpu_virt_reset_gpu() - reset gpu 176 * @adev: amdgpu device. 177 * Send reset command to GPU hypervisor to reset GPU that VM is using 178 * Return: Zero if reset success, otherwise will return error. 179 */ 180 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 181 { 182 struct amdgpu_virt *virt = &adev->virt; 183 int r; 184 185 if (virt->ops && virt->ops->reset_gpu) { 186 r = virt->ops->reset_gpu(adev); 187 if (r) 188 return r; 189 190 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 191 } 192 193 return 0; 194 } 195 196 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 197 { 198 struct amdgpu_virt *virt = &adev->virt; 199 200 if (virt->ops && virt->ops->req_init_data) 201 virt->ops->req_init_data(adev); 202 203 if (adev->virt.req_init_data_ver > 0) 204 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 205 else 206 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 207 } 208 209 /** 210 * amdgpu_virt_wait_reset() - wait for reset gpu completed 211 * @adev: amdgpu device. 212 * Wait for GPU reset completed. 213 * Return: Zero if reset success, otherwise will return error. 214 */ 215 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 216 { 217 struct amdgpu_virt *virt = &adev->virt; 218 219 if (!virt->ops || !virt->ops->wait_reset) 220 return -EINVAL; 221 222 return virt->ops->wait_reset(adev); 223 } 224 225 /** 226 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 227 * @adev: amdgpu device. 228 * MM table is used by UVD and VCE for its initialization 229 * Return: Zero if allocate success. 230 */ 231 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 232 { 233 int r; 234 235 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 236 return 0; 237 238 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 239 AMDGPU_GEM_DOMAIN_VRAM | 240 AMDGPU_GEM_DOMAIN_GTT, 241 &adev->virt.mm_table.bo, 242 &adev->virt.mm_table.gpu_addr, 243 (void *)&adev->virt.mm_table.cpu_addr); 244 if (r) { 245 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 246 return r; 247 } 248 249 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 250 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 251 adev->virt.mm_table.gpu_addr, 252 adev->virt.mm_table.cpu_addr); 253 return 0; 254 } 255 256 /** 257 * amdgpu_virt_free_mm_table() - free mm table memory 258 * @adev: amdgpu device. 259 * Free MM table memory 260 */ 261 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 262 { 263 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 264 return; 265 266 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 267 &adev->virt.mm_table.gpu_addr, 268 (void *)&adev->virt.mm_table.cpu_addr); 269 adev->virt.mm_table.gpu_addr = 0; 270 } 271 272 273 unsigned int amd_sriov_msg_checksum(void *obj, 274 unsigned long obj_size, 275 unsigned int key, 276 unsigned int checksum) 277 { 278 unsigned int ret = key; 279 unsigned long i = 0; 280 unsigned char *pos; 281 282 pos = (char *)obj; 283 /* calculate checksum */ 284 for (i = 0; i < obj_size; ++i) 285 ret += *(pos + i); 286 /* minus the checksum itself */ 287 pos = (char *)&checksum; 288 for (i = 0; i < sizeof(checksum); ++i) 289 ret -= *(pos + i); 290 return ret; 291 } 292 293 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 294 { 295 struct amdgpu_virt *virt = &adev->virt; 296 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 297 /* GPU will be marked bad on host if bp count more then 10, 298 * so alloc 512 is enough. 299 */ 300 unsigned int align_space = 512; 301 void *bps = NULL; 302 struct amdgpu_bo **bps_bo = NULL; 303 304 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 305 if (!*data) 306 goto data_failure; 307 308 bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL); 309 if (!bps) 310 goto bps_failure; 311 312 bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL); 313 if (!bps_bo) 314 goto bps_bo_failure; 315 316 (*data)->bps = bps; 317 (*data)->bps_bo = bps_bo; 318 (*data)->count = 0; 319 (*data)->last_reserved = 0; 320 321 virt->ras_init_done = true; 322 323 return 0; 324 325 bps_bo_failure: 326 kfree(bps); 327 bps_failure: 328 kfree(*data); 329 data_failure: 330 return -ENOMEM; 331 } 332 333 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 334 { 335 struct amdgpu_virt *virt = &adev->virt; 336 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 337 struct amdgpu_bo *bo; 338 int i; 339 340 if (!data) 341 return; 342 343 for (i = data->last_reserved - 1; i >= 0; i--) { 344 bo = data->bps_bo[i]; 345 amdgpu_bo_free_kernel(&bo, NULL, NULL); 346 data->bps_bo[i] = bo; 347 data->last_reserved = i; 348 } 349 } 350 351 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 352 { 353 struct amdgpu_virt *virt = &adev->virt; 354 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 355 356 virt->ras_init_done = false; 357 358 if (!data) 359 return; 360 361 amdgpu_virt_ras_release_bp(adev); 362 363 kfree(data->bps); 364 kfree(data->bps_bo); 365 kfree(data); 366 virt->virt_eh_data = NULL; 367 } 368 369 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 370 struct eeprom_table_record *bps, int pages) 371 { 372 struct amdgpu_virt *virt = &adev->virt; 373 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 374 375 if (!data) 376 return; 377 378 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 379 data->count += pages; 380 } 381 382 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 383 { 384 struct amdgpu_virt *virt = &adev->virt; 385 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 386 struct amdgpu_bo *bo = NULL; 387 uint64_t bp; 388 int i; 389 390 if (!data) 391 return; 392 393 for (i = data->last_reserved; i < data->count; i++) { 394 bp = data->bps[i].retired_page; 395 396 /* There are two cases of reserve error should be ignored: 397 * 1) a ras bad page has been allocated (used by someone); 398 * 2) a ras bad page has been reserved (duplicate error injection 399 * for one page); 400 */ 401 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 402 AMDGPU_GPU_PAGE_SIZE, 403 &bo, NULL)) 404 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 405 406 data->bps_bo[i] = bo; 407 data->last_reserved = i + 1; 408 bo = NULL; 409 } 410 } 411 412 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 413 uint64_t retired_page) 414 { 415 struct amdgpu_virt *virt = &adev->virt; 416 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 417 int i; 418 419 if (!data) 420 return true; 421 422 for (i = 0; i < data->count; i++) 423 if (retired_page == data->bps[i].retired_page) 424 return true; 425 426 return false; 427 } 428 429 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 430 uint64_t bp_block_offset, uint32_t bp_block_size) 431 { 432 struct eeprom_table_record bp; 433 uint64_t retired_page; 434 uint32_t bp_idx, bp_cnt; 435 void *vram_usage_va = NULL; 436 437 if (adev->mman.fw_vram_usage_va) 438 vram_usage_va = adev->mman.fw_vram_usage_va; 439 else 440 vram_usage_va = adev->mman.drv_vram_usage_va; 441 442 if (bp_block_size) { 443 bp_cnt = bp_block_size / sizeof(uint64_t); 444 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 445 retired_page = *(uint64_t *)(vram_usage_va + 446 bp_block_offset + bp_idx * sizeof(uint64_t)); 447 bp.retired_page = retired_page; 448 449 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 450 continue; 451 452 amdgpu_virt_ras_add_bps(adev, &bp, 1); 453 454 amdgpu_virt_ras_reserve_bps(adev); 455 } 456 } 457 } 458 459 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 460 { 461 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 462 uint32_t checksum; 463 uint32_t checkval; 464 465 uint32_t i; 466 uint32_t tmp; 467 468 if (adev->virt.fw_reserve.p_pf2vf == NULL) 469 return -EINVAL; 470 471 if (pf2vf_info->size > 1024) { 472 DRM_ERROR("invalid pf2vf message size\n"); 473 return -EINVAL; 474 } 475 476 switch (pf2vf_info->version) { 477 case 1: 478 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 479 checkval = amd_sriov_msg_checksum( 480 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 481 adev->virt.fw_reserve.checksum_key, checksum); 482 if (checksum != checkval) { 483 DRM_ERROR("invalid pf2vf message\n"); 484 return -EINVAL; 485 } 486 487 adev->virt.gim_feature = 488 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 489 break; 490 case 2: 491 /* TODO: missing key, need to add it later */ 492 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 493 checkval = amd_sriov_msg_checksum( 494 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 495 0, checksum); 496 if (checksum != checkval) { 497 DRM_ERROR("invalid pf2vf message\n"); 498 return -EINVAL; 499 } 500 501 adev->virt.vf2pf_update_interval_ms = 502 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 503 adev->virt.gim_feature = 504 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 505 adev->virt.reg_access = 506 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 507 508 adev->virt.decode_max_dimension_pixels = 0; 509 adev->virt.decode_max_frame_pixels = 0; 510 adev->virt.encode_max_dimension_pixels = 0; 511 adev->virt.encode_max_frame_pixels = 0; 512 adev->virt.is_mm_bw_enabled = false; 513 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 514 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 515 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 516 517 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 518 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 519 520 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 521 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 522 523 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 524 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 525 } 526 if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 527 adev->virt.is_mm_bw_enabled = true; 528 529 adev->unique_id = 530 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 531 break; 532 default: 533 DRM_ERROR("invalid pf2vf version\n"); 534 return -EINVAL; 535 } 536 537 /* correct too large or too little interval value */ 538 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 539 adev->virt.vf2pf_update_interval_ms = 2000; 540 541 return 0; 542 } 543 544 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 545 { 546 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 547 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 548 549 if (adev->virt.fw_reserve.p_vf2pf == NULL) 550 return; 551 552 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 553 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 554 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 555 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 556 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 557 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 558 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 559 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 560 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 561 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 562 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 563 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 564 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 565 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, 566 adev->psp.asd_context.bin_desc.fw_version); 567 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, 568 adev->psp.ras_context.context.bin_desc.fw_version); 569 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, 570 adev->psp.xgmi_context.context.bin_desc.fw_version); 571 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 572 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 573 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 574 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 575 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 576 } 577 578 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 579 { 580 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 581 582 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 583 584 if (adev->virt.fw_reserve.p_vf2pf == NULL) 585 return -EINVAL; 586 587 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 588 589 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 590 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 591 592 #ifdef MODULE 593 if (THIS_MODULE->version != NULL) 594 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 595 else 596 #endif 597 strcpy(vf2pf_info->driver_version, "N/A"); 598 599 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 600 vf2pf_info->driver_cert = 0; 601 vf2pf_info->os_info.all = 0; 602 603 vf2pf_info->fb_usage = 604 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; 605 vf2pf_info->fb_vis_usage = 606 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 607 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 608 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 609 610 amdgpu_virt_populate_vf2pf_ucode_info(adev); 611 612 /* TODO: read dynamic info */ 613 vf2pf_info->gfx_usage = 0; 614 vf2pf_info->compute_usage = 0; 615 vf2pf_info->encode_usage = 0; 616 vf2pf_info->decode_usage = 0; 617 618 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 619 vf2pf_info->checksum = 620 amd_sriov_msg_checksum( 621 vf2pf_info, vf2pf_info->header.size, 0, 0); 622 623 return 0; 624 } 625 626 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 627 { 628 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 629 int ret; 630 631 ret = amdgpu_virt_read_pf2vf_data(adev); 632 if (ret) 633 goto out; 634 amdgpu_virt_write_vf2pf_data(adev); 635 636 out: 637 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 638 } 639 640 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 641 { 642 if (adev->virt.vf2pf_update_interval_ms != 0) { 643 DRM_INFO("clean up the vf2pf work item\n"); 644 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 645 adev->virt.vf2pf_update_interval_ms = 0; 646 } 647 } 648 649 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 650 { 651 adev->virt.fw_reserve.p_pf2vf = NULL; 652 adev->virt.fw_reserve.p_vf2pf = NULL; 653 adev->virt.vf2pf_update_interval_ms = 0; 654 655 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { 656 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!"); 657 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 658 /* go through this logic in ip_init and reset to init workqueue*/ 659 amdgpu_virt_exchange_data(adev); 660 661 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 662 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 663 } else if (adev->bios != NULL) { 664 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 665 adev->virt.fw_reserve.p_pf2vf = 666 (struct amd_sriov_msg_pf2vf_info_header *) 667 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 668 669 amdgpu_virt_read_pf2vf_data(adev); 670 } 671 } 672 673 674 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 675 { 676 uint64_t bp_block_offset = 0; 677 uint32_t bp_block_size = 0; 678 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 679 680 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 681 if (adev->mman.fw_vram_usage_va) { 682 adev->virt.fw_reserve.p_pf2vf = 683 (struct amd_sriov_msg_pf2vf_info_header *) 684 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 685 adev->virt.fw_reserve.p_vf2pf = 686 (struct amd_sriov_msg_vf2pf_info_header *) 687 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 688 } else if (adev->mman.drv_vram_usage_va) { 689 adev->virt.fw_reserve.p_pf2vf = 690 (struct amd_sriov_msg_pf2vf_info_header *) 691 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 692 adev->virt.fw_reserve.p_vf2pf = 693 (struct amd_sriov_msg_vf2pf_info_header *) 694 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 695 } 696 697 amdgpu_virt_read_pf2vf_data(adev); 698 amdgpu_virt_write_vf2pf_data(adev); 699 700 /* bad page handling for version 2 */ 701 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 702 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 703 704 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 705 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 706 bp_block_size = pf2vf_v2->bp_block_size; 707 708 if (bp_block_size && !adev->virt.ras_init_done) 709 amdgpu_virt_init_ras_err_handler_data(adev); 710 711 if (adev->virt.ras_init_done) 712 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 713 } 714 } 715 } 716 717 void amdgpu_detect_virtualization(struct amdgpu_device *adev) 718 { 719 uint32_t reg; 720 721 switch (adev->asic_type) { 722 case CHIP_TONGA: 723 case CHIP_FIJI: 724 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 725 break; 726 case CHIP_VEGA10: 727 case CHIP_VEGA20: 728 case CHIP_NAVI10: 729 case CHIP_NAVI12: 730 case CHIP_SIENNA_CICHLID: 731 case CHIP_ARCTURUS: 732 case CHIP_ALDEBARAN: 733 case CHIP_IP_DISCOVERY: 734 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 735 break; 736 default: /* other chip doesn't support SRIOV */ 737 reg = 0; 738 break; 739 } 740 741 if (reg & 1) 742 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 743 744 if (reg & 0x80000000) 745 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 746 747 if (!reg) { 748 /* passthrough mode exclus sriov mod */ 749 if (is_virtual_machine() && !xen_initial_domain()) 750 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 751 } 752 753 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) 754 /* VF MMIO access (except mailbox range) from CPU 755 * will be blocked during sriov runtime 756 */ 757 adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT; 758 759 /* we have the ability to check now */ 760 if (amdgpu_sriov_vf(adev)) { 761 switch (adev->asic_type) { 762 case CHIP_TONGA: 763 case CHIP_FIJI: 764 vi_set_virt_ops(adev); 765 break; 766 case CHIP_VEGA10: 767 soc15_set_virt_ops(adev); 768 #ifdef CONFIG_X86 769 /* not send GPU_INIT_DATA with MS_HYPERV*/ 770 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV)) 771 #endif 772 /* send a dummy GPU_INIT_DATA request to host on vega10 */ 773 amdgpu_virt_request_init_data(adev); 774 break; 775 case CHIP_VEGA20: 776 case CHIP_ARCTURUS: 777 case CHIP_ALDEBARAN: 778 soc15_set_virt_ops(adev); 779 break; 780 case CHIP_NAVI10: 781 case CHIP_NAVI12: 782 case CHIP_SIENNA_CICHLID: 783 case CHIP_IP_DISCOVERY: 784 nv_set_virt_ops(adev); 785 /* try send GPU_INIT_DATA request to host */ 786 amdgpu_virt_request_init_data(adev); 787 break; 788 default: /* other chip doesn't support SRIOV */ 789 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 790 break; 791 } 792 } 793 } 794 795 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 796 { 797 return amdgpu_sriov_is_debug(adev) ? true : false; 798 } 799 800 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 801 { 802 return amdgpu_sriov_is_normal(adev) ? true : false; 803 } 804 805 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 806 { 807 if (!amdgpu_sriov_vf(adev) || 808 amdgpu_virt_access_debugfs_is_kiq(adev)) 809 return 0; 810 811 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 812 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 813 else 814 return -EPERM; 815 816 return 0; 817 } 818 819 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 820 { 821 if (amdgpu_sriov_vf(adev)) 822 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 823 } 824 825 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 826 { 827 enum amdgpu_sriov_vf_mode mode; 828 829 if (amdgpu_sriov_vf(adev)) { 830 if (amdgpu_sriov_is_pp_one_vf(adev)) 831 mode = SRIOV_VF_MODE_ONE_VF; 832 else 833 mode = SRIOV_VF_MODE_MULTI_VF; 834 } else { 835 mode = SRIOV_VF_MODE_BARE_METAL; 836 } 837 838 return mode; 839 } 840 841 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) 842 { 843 switch (adev->ip_versions[MP0_HWIP][0]) { 844 case IP_VERSION(13, 0, 0): 845 /* no vf autoload, white list */ 846 if (ucode_id == AMDGPU_UCODE_ID_VCN1 || 847 ucode_id == AMDGPU_UCODE_ID_VCN) 848 return false; 849 else 850 return true; 851 case IP_VERSION(13, 0, 10): 852 /* white list */ 853 if (ucode_id == AMDGPU_UCODE_ID_CAP 854 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP 855 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME 856 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC 857 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK 858 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK 859 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK 860 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK 861 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK 862 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK 863 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK 864 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK 865 || ucode_id == AMDGPU_UCODE_ID_CP_MES 866 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA 867 || ucode_id == AMDGPU_UCODE_ID_CP_MES1 868 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA 869 || ucode_id == AMDGPU_UCODE_ID_VCN1 870 || ucode_id == AMDGPU_UCODE_ID_VCN) 871 return false; 872 else 873 return true; 874 default: 875 /* lagacy black list */ 876 if (ucode_id == AMDGPU_UCODE_ID_SDMA0 877 || ucode_id == AMDGPU_UCODE_ID_SDMA1 878 || ucode_id == AMDGPU_UCODE_ID_SDMA2 879 || ucode_id == AMDGPU_UCODE_ID_SDMA3 880 || ucode_id == AMDGPU_UCODE_ID_SDMA4 881 || ucode_id == AMDGPU_UCODE_ID_SDMA5 882 || ucode_id == AMDGPU_UCODE_ID_SDMA6 883 || ucode_id == AMDGPU_UCODE_ID_SDMA7 884 || ucode_id == AMDGPU_UCODE_ID_RLC_G 885 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 886 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 887 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 888 || ucode_id == AMDGPU_UCODE_ID_SMC) 889 return true; 890 else 891 return false; 892 } 893 } 894 895 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 896 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 897 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 898 { 899 uint32_t i; 900 901 if (!adev->virt.is_mm_bw_enabled) 902 return; 903 904 if (encode) { 905 for (i = 0; i < encode_array_size; i++) { 906 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 907 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 908 if (encode[i].max_width > 0) 909 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 910 else 911 encode[i].max_height = 0; 912 } 913 } 914 915 if (decode) { 916 for (i = 0; i < decode_array_size; i++) { 917 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 918 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 919 if (decode[i].max_width > 0) 920 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 921 else 922 decode[i].max_height = 0; 923 } 924 } 925 } 926 927 static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 928 u32 acc_flags, u32 hwip, 929 bool write, u32 *rlcg_flag) 930 { 931 bool ret = false; 932 933 switch (hwip) { 934 case GC_HWIP: 935 if (amdgpu_sriov_reg_indirect_gc(adev)) { 936 *rlcg_flag = 937 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ; 938 ret = true; 939 /* only in new version, AMDGPU_REGS_NO_KIQ and 940 * AMDGPU_REGS_RLC are enabled simultaneously */ 941 } else if ((acc_flags & AMDGPU_REGS_RLC) && 942 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { 943 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; 944 ret = true; 945 } 946 break; 947 case MMHUB_HWIP: 948 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 949 (acc_flags & AMDGPU_REGS_RLC) && write) { 950 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE; 951 ret = true; 952 } 953 break; 954 default: 955 break; 956 } 957 return ret; 958 } 959 960 static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag) 961 { 962 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 963 uint32_t timeout = 50000; 964 uint32_t i, tmp; 965 uint32_t ret = 0; 966 void *scratch_reg0; 967 void *scratch_reg1; 968 void *scratch_reg2; 969 void *scratch_reg3; 970 void *spare_int; 971 972 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 973 dev_err(adev->dev, 974 "indirect registers access through rlcg is not available\n"); 975 return 0; 976 } 977 978 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 979 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; 980 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; 981 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; 982 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; 983 if (reg_access_ctrl->spare_int) 984 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; 985 986 if (offset == reg_access_ctrl->grbm_cntl) { 987 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */ 988 writel(v, scratch_reg2); 989 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 990 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 991 } else if (offset == reg_access_ctrl->grbm_idx) { 992 /* if the target reg offset is grbm_idx, write to scratch_reg3 */ 993 writel(v, scratch_reg3); 994 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY) 995 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 996 } else { 997 /* 998 * SCRATCH_REG0 = read/write value 999 * SCRATCH_REG1[30:28] = command 1000 * SCRATCH_REG1[19:0] = address in dword 1001 * SCRATCH_REG1[26:24] = Error reporting 1002 */ 1003 writel(v, scratch_reg0); 1004 writel((offset | flag), scratch_reg1); 1005 if (reg_access_ctrl->spare_int) 1006 writel(1, spare_int); 1007 1008 for (i = 0; i < timeout; i++) { 1009 tmp = readl(scratch_reg1); 1010 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK)) 1011 break; 1012 udelay(10); 1013 } 1014 1015 if (i >= timeout) { 1016 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { 1017 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) { 1018 dev_err(adev->dev, 1019 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset); 1020 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) { 1021 dev_err(adev->dev, 1022 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset); 1023 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) { 1024 dev_err(adev->dev, 1025 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset); 1026 } else { 1027 dev_err(adev->dev, 1028 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset); 1029 } 1030 } else { 1031 dev_err(adev->dev, 1032 "timeout: rlcg faled to program reg: 0x%05x\n", offset); 1033 } 1034 } 1035 } 1036 1037 ret = readl(scratch_reg0); 1038 return ret; 1039 } 1040 1041 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 1042 u32 offset, u32 value, 1043 u32 acc_flags, u32 hwip) 1044 { 1045 u32 rlcg_flag; 1046 1047 if (!amdgpu_sriov_runtime(adev) && 1048 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1049 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag); 1050 return; 1051 } 1052 1053 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1054 WREG32_NO_KIQ(offset, value); 1055 else 1056 WREG32(offset, value); 1057 } 1058 1059 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 1060 u32 offset, u32 acc_flags, u32 hwip) 1061 { 1062 u32 rlcg_flag; 1063 1064 if (!amdgpu_sriov_runtime(adev) && 1065 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 1066 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag); 1067 1068 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1069 return RREG32_NO_KIQ(offset); 1070 else 1071 return RREG32(offset); 1072 } 1073