1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #define MAX_KIQ_REG_WAIT 100000 26 27 int amdgpu_allocate_static_csa(struct amdgpu_device *adev) 28 { 29 int r; 30 void *ptr; 31 32 r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE, 33 AMDGPU_GEM_DOMAIN_VRAM, &adev->virt.csa_obj, 34 &adev->virt.csa_vmid0_addr, &ptr); 35 if (r) 36 return r; 37 38 memset(ptr, 0, AMDGPU_CSA_SIZE); 39 return 0; 40 } 41 42 /* 43 * amdgpu_map_static_csa should be called during amdgpu_vm_init 44 * it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE" 45 * to this VM, and each command submission of GFX should use this virtual 46 * address within META_DATA init package to support SRIOV gfx preemption. 47 */ 48 49 int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, 50 struct amdgpu_bo_va **bo_va) 51 { 52 struct ww_acquire_ctx ticket; 53 struct list_head list; 54 struct amdgpu_bo_list_entry pd; 55 struct ttm_validate_buffer csa_tv; 56 int r; 57 58 INIT_LIST_HEAD(&list); 59 INIT_LIST_HEAD(&csa_tv.head); 60 csa_tv.bo = &adev->virt.csa_obj->tbo; 61 csa_tv.shared = true; 62 63 list_add(&csa_tv.head, &list); 64 amdgpu_vm_get_pd_bo(vm, &list, &pd); 65 66 r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL); 67 if (r) { 68 DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r); 69 return r; 70 } 71 72 *bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj); 73 if (!*bo_va) { 74 ttm_eu_backoff_reservation(&ticket, &list); 75 DRM_ERROR("failed to create bo_va for static CSA\n"); 76 return -ENOMEM; 77 } 78 79 r = amdgpu_vm_alloc_pts(adev, (*bo_va)->base.vm, AMDGPU_CSA_VADDR, 80 AMDGPU_CSA_SIZE); 81 if (r) { 82 DRM_ERROR("failed to allocate pts for static CSA, err=%d\n", r); 83 amdgpu_vm_bo_rmv(adev, *bo_va); 84 ttm_eu_backoff_reservation(&ticket, &list); 85 return r; 86 } 87 88 r = amdgpu_vm_bo_map(adev, *bo_va, AMDGPU_CSA_VADDR, 0, AMDGPU_CSA_SIZE, 89 AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | 90 AMDGPU_PTE_EXECUTABLE); 91 92 if (r) { 93 DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r); 94 amdgpu_vm_bo_rmv(adev, *bo_va); 95 ttm_eu_backoff_reservation(&ticket, &list); 96 return r; 97 } 98 99 ttm_eu_backoff_reservation(&ticket, &list); 100 return 0; 101 } 102 103 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 104 { 105 /* enable virtual display */ 106 adev->mode_info.num_crtc = 1; 107 adev->enable_virtual_display = true; 108 adev->cg_flags = 0; 109 adev->pg_flags = 0; 110 111 mutex_init(&adev->virt.lock_reset); 112 } 113 114 uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) 115 { 116 signed long r; 117 uint32_t val; 118 struct dma_fence *f; 119 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 120 struct amdgpu_ring *ring = &kiq->ring; 121 122 BUG_ON(!ring->funcs->emit_rreg); 123 124 mutex_lock(&kiq->ring_mutex); 125 amdgpu_ring_alloc(ring, 32); 126 amdgpu_ring_emit_rreg(ring, reg); 127 amdgpu_fence_emit(ring, &f); 128 amdgpu_ring_commit(ring); 129 mutex_unlock(&kiq->ring_mutex); 130 131 r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT)); 132 dma_fence_put(f); 133 if (r < 1) { 134 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 135 return ~0; 136 } 137 138 val = adev->wb.wb[adev->virt.reg_val_offs]; 139 140 return val; 141 } 142 143 void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) 144 { 145 signed long r; 146 struct dma_fence *f; 147 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 148 struct amdgpu_ring *ring = &kiq->ring; 149 150 BUG_ON(!ring->funcs->emit_wreg); 151 152 mutex_lock(&kiq->ring_mutex); 153 amdgpu_ring_alloc(ring, 32); 154 amdgpu_ring_emit_wreg(ring, reg, v); 155 amdgpu_fence_emit(ring, &f); 156 amdgpu_ring_commit(ring); 157 mutex_unlock(&kiq->ring_mutex); 158 159 r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT)); 160 if (r < 1) 161 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 162 dma_fence_put(f); 163 } 164 165 /** 166 * amdgpu_virt_request_full_gpu() - request full gpu access 167 * @amdgpu: amdgpu device. 168 * @init: is driver init time. 169 * When start to init/fini driver, first need to request full gpu access. 170 * Return: Zero if request success, otherwise will return error. 171 */ 172 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 173 { 174 struct amdgpu_virt *virt = &adev->virt; 175 int r; 176 177 if (virt->ops && virt->ops->req_full_gpu) { 178 r = virt->ops->req_full_gpu(adev, init); 179 if (r) 180 return r; 181 182 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 183 } 184 185 return 0; 186 } 187 188 /** 189 * amdgpu_virt_release_full_gpu() - release full gpu access 190 * @amdgpu: amdgpu device. 191 * @init: is driver init time. 192 * When finishing driver init/fini, need to release full gpu access. 193 * Return: Zero if release success, otherwise will returen error. 194 */ 195 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 196 { 197 struct amdgpu_virt *virt = &adev->virt; 198 int r; 199 200 if (virt->ops && virt->ops->rel_full_gpu) { 201 r = virt->ops->rel_full_gpu(adev, init); 202 if (r) 203 return r; 204 205 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 206 } 207 return 0; 208 } 209 210 /** 211 * amdgpu_virt_reset_gpu() - reset gpu 212 * @amdgpu: amdgpu device. 213 * Send reset command to GPU hypervisor to reset GPU that VM is using 214 * Return: Zero if reset success, otherwise will return error. 215 */ 216 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 217 { 218 struct amdgpu_virt *virt = &adev->virt; 219 int r; 220 221 if (virt->ops && virt->ops->reset_gpu) { 222 r = virt->ops->reset_gpu(adev); 223 if (r) 224 return r; 225 226 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 227 } 228 229 return 0; 230 } 231 232 /** 233 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 234 * @amdgpu: amdgpu device. 235 * MM table is used by UVD and VCE for its initialization 236 * Return: Zero if allocate success. 237 */ 238 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 239 { 240 int r; 241 242 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 243 return 0; 244 245 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 246 AMDGPU_GEM_DOMAIN_VRAM, 247 &adev->virt.mm_table.bo, 248 &adev->virt.mm_table.gpu_addr, 249 (void *)&adev->virt.mm_table.cpu_addr); 250 if (r) { 251 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 252 return r; 253 } 254 255 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 256 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 257 adev->virt.mm_table.gpu_addr, 258 adev->virt.mm_table.cpu_addr); 259 return 0; 260 } 261 262 /** 263 * amdgpu_virt_free_mm_table() - free mm table memory 264 * @amdgpu: amdgpu device. 265 * Free MM table memory 266 */ 267 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 268 { 269 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 270 return; 271 272 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 273 &adev->virt.mm_table.gpu_addr, 274 (void *)&adev->virt.mm_table.cpu_addr); 275 adev->virt.mm_table.gpu_addr = 0; 276 } 277