1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #include <drm/drm_drv.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ras.h" 30 #include "vi.h" 31 #include "soc15.h" 32 #include "nv.h" 33 34 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 35 do { \ 36 vf2pf_info->ucode_info[ucode].id = ucode; \ 37 vf2pf_info->ucode_info[ucode].version = ver; \ 38 } while (0) 39 40 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 41 { 42 /* By now all MMIO pages except mailbox are blocked */ 43 /* if blocking is enabled in hypervisor. Choose the */ 44 /* SCRATCH_REG0 to test. */ 45 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 46 } 47 48 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 49 { 50 struct drm_device *ddev = adev_to_drm(adev); 51 52 /* enable virtual display */ 53 if (adev->mode_info.num_crtc == 0) 54 adev->mode_info.num_crtc = 1; 55 adev->enable_virtual_display = true; 56 ddev->driver_features &= ~DRIVER_ATOMIC; 57 adev->cg_flags = 0; 58 adev->pg_flags = 0; 59 } 60 61 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 62 uint32_t reg0, uint32_t reg1, 63 uint32_t ref, uint32_t mask) 64 { 65 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 66 struct amdgpu_ring *ring = &kiq->ring; 67 signed long r, cnt = 0; 68 unsigned long flags; 69 uint32_t seq; 70 71 spin_lock_irqsave(&kiq->ring_lock, flags); 72 amdgpu_ring_alloc(ring, 32); 73 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, 74 ref, mask); 75 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 76 if (r) 77 goto failed_undo; 78 79 amdgpu_ring_commit(ring); 80 spin_unlock_irqrestore(&kiq->ring_lock, flags); 81 82 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 83 84 /* don't wait anymore for IRQ context */ 85 if (r < 1 && in_interrupt()) 86 goto failed_kiq; 87 88 might_sleep(); 89 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 90 91 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 92 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 93 } 94 95 if (cnt > MAX_KIQ_REG_TRY) 96 goto failed_kiq; 97 98 return; 99 100 failed_undo: 101 amdgpu_ring_undo(ring); 102 spin_unlock_irqrestore(&kiq->ring_lock, flags); 103 failed_kiq: 104 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1); 105 } 106 107 /** 108 * amdgpu_virt_request_full_gpu() - request full gpu access 109 * @adev: amdgpu device. 110 * @init: is driver init time. 111 * When start to init/fini driver, first need to request full gpu access. 112 * Return: Zero if request success, otherwise will return error. 113 */ 114 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 115 { 116 struct amdgpu_virt *virt = &adev->virt; 117 int r; 118 119 if (virt->ops && virt->ops->req_full_gpu) { 120 r = virt->ops->req_full_gpu(adev, init); 121 if (r) 122 return r; 123 124 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 125 } 126 127 return 0; 128 } 129 130 /** 131 * amdgpu_virt_release_full_gpu() - release full gpu access 132 * @adev: amdgpu device. 133 * @init: is driver init time. 134 * When finishing driver init/fini, need to release full gpu access. 135 * Return: Zero if release success, otherwise will returen error. 136 */ 137 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 138 { 139 struct amdgpu_virt *virt = &adev->virt; 140 int r; 141 142 if (virt->ops && virt->ops->rel_full_gpu) { 143 r = virt->ops->rel_full_gpu(adev, init); 144 if (r) 145 return r; 146 147 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 148 } 149 return 0; 150 } 151 152 /** 153 * amdgpu_virt_reset_gpu() - reset gpu 154 * @adev: amdgpu device. 155 * Send reset command to GPU hypervisor to reset GPU that VM is using 156 * Return: Zero if reset success, otherwise will return error. 157 */ 158 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 159 { 160 struct amdgpu_virt *virt = &adev->virt; 161 int r; 162 163 if (virt->ops && virt->ops->reset_gpu) { 164 r = virt->ops->reset_gpu(adev); 165 if (r) 166 return r; 167 168 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 169 } 170 171 return 0; 172 } 173 174 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 175 { 176 struct amdgpu_virt *virt = &adev->virt; 177 178 if (virt->ops && virt->ops->req_init_data) 179 virt->ops->req_init_data(adev); 180 181 if (adev->virt.req_init_data_ver > 0) 182 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 183 else 184 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 185 } 186 187 /** 188 * amdgpu_virt_wait_reset() - wait for reset gpu completed 189 * @adev: amdgpu device. 190 * Wait for GPU reset completed. 191 * Return: Zero if reset success, otherwise will return error. 192 */ 193 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 194 { 195 struct amdgpu_virt *virt = &adev->virt; 196 197 if (!virt->ops || !virt->ops->wait_reset) 198 return -EINVAL; 199 200 return virt->ops->wait_reset(adev); 201 } 202 203 /** 204 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 205 * @adev: amdgpu device. 206 * MM table is used by UVD and VCE for its initialization 207 * Return: Zero if allocate success. 208 */ 209 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 210 { 211 int r; 212 213 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 214 return 0; 215 216 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 217 AMDGPU_GEM_DOMAIN_VRAM, 218 &adev->virt.mm_table.bo, 219 &adev->virt.mm_table.gpu_addr, 220 (void *)&adev->virt.mm_table.cpu_addr); 221 if (r) { 222 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 223 return r; 224 } 225 226 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 227 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 228 adev->virt.mm_table.gpu_addr, 229 adev->virt.mm_table.cpu_addr); 230 return 0; 231 } 232 233 /** 234 * amdgpu_virt_free_mm_table() - free mm table memory 235 * @adev: amdgpu device. 236 * Free MM table memory 237 */ 238 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 239 { 240 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 241 return; 242 243 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 244 &adev->virt.mm_table.gpu_addr, 245 (void *)&adev->virt.mm_table.cpu_addr); 246 adev->virt.mm_table.gpu_addr = 0; 247 } 248 249 250 unsigned int amd_sriov_msg_checksum(void *obj, 251 unsigned long obj_size, 252 unsigned int key, 253 unsigned int checksum) 254 { 255 unsigned int ret = key; 256 unsigned long i = 0; 257 unsigned char *pos; 258 259 pos = (char *)obj; 260 /* calculate checksum */ 261 for (i = 0; i < obj_size; ++i) 262 ret += *(pos + i); 263 /* minus the checksum itself */ 264 pos = (char *)&checksum; 265 for (i = 0; i < sizeof(checksum); ++i) 266 ret -= *(pos + i); 267 return ret; 268 } 269 270 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 271 { 272 struct amdgpu_virt *virt = &adev->virt; 273 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 274 /* GPU will be marked bad on host if bp count more then 10, 275 * so alloc 512 is enough. 276 */ 277 unsigned int align_space = 512; 278 void *bps = NULL; 279 struct amdgpu_bo **bps_bo = NULL; 280 281 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 282 if (!*data) 283 return -ENOMEM; 284 285 bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL); 286 bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL); 287 288 if (!bps || !bps_bo) { 289 kfree(bps); 290 kfree(bps_bo); 291 kfree(*data); 292 return -ENOMEM; 293 } 294 295 (*data)->bps = bps; 296 (*data)->bps_bo = bps_bo; 297 (*data)->count = 0; 298 (*data)->last_reserved = 0; 299 300 virt->ras_init_done = true; 301 302 return 0; 303 } 304 305 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 306 { 307 struct amdgpu_virt *virt = &adev->virt; 308 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 309 struct amdgpu_bo *bo; 310 int i; 311 312 if (!data) 313 return; 314 315 for (i = data->last_reserved - 1; i >= 0; i--) { 316 bo = data->bps_bo[i]; 317 amdgpu_bo_free_kernel(&bo, NULL, NULL); 318 data->bps_bo[i] = bo; 319 data->last_reserved = i; 320 } 321 } 322 323 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 324 { 325 struct amdgpu_virt *virt = &adev->virt; 326 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 327 328 virt->ras_init_done = false; 329 330 if (!data) 331 return; 332 333 amdgpu_virt_ras_release_bp(adev); 334 335 kfree(data->bps); 336 kfree(data->bps_bo); 337 kfree(data); 338 virt->virt_eh_data = NULL; 339 } 340 341 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 342 struct eeprom_table_record *bps, int pages) 343 { 344 struct amdgpu_virt *virt = &adev->virt; 345 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 346 347 if (!data) 348 return; 349 350 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 351 data->count += pages; 352 } 353 354 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 355 { 356 struct amdgpu_virt *virt = &adev->virt; 357 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 358 struct amdgpu_bo *bo = NULL; 359 uint64_t bp; 360 int i; 361 362 if (!data) 363 return; 364 365 for (i = data->last_reserved; i < data->count; i++) { 366 bp = data->bps[i].retired_page; 367 368 /* There are two cases of reserve error should be ignored: 369 * 1) a ras bad page has been allocated (used by someone); 370 * 2) a ras bad page has been reserved (duplicate error injection 371 * for one page); 372 */ 373 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 374 AMDGPU_GPU_PAGE_SIZE, 375 AMDGPU_GEM_DOMAIN_VRAM, 376 &bo, NULL)) 377 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 378 379 data->bps_bo[i] = bo; 380 data->last_reserved = i + 1; 381 bo = NULL; 382 } 383 } 384 385 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 386 uint64_t retired_page) 387 { 388 struct amdgpu_virt *virt = &adev->virt; 389 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 390 int i; 391 392 if (!data) 393 return true; 394 395 for (i = 0; i < data->count; i++) 396 if (retired_page == data->bps[i].retired_page) 397 return true; 398 399 return false; 400 } 401 402 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 403 uint64_t bp_block_offset, uint32_t bp_block_size) 404 { 405 struct eeprom_table_record bp; 406 uint64_t retired_page; 407 uint32_t bp_idx, bp_cnt; 408 409 if (bp_block_size) { 410 bp_cnt = bp_block_size / sizeof(uint64_t); 411 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 412 retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va + 413 bp_block_offset + bp_idx * sizeof(uint64_t)); 414 bp.retired_page = retired_page; 415 416 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 417 continue; 418 419 amdgpu_virt_ras_add_bps(adev, &bp, 1); 420 421 amdgpu_virt_ras_reserve_bps(adev); 422 } 423 } 424 } 425 426 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 427 { 428 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 429 uint32_t checksum; 430 uint32_t checkval; 431 432 if (adev->virt.fw_reserve.p_pf2vf == NULL) 433 return -EINVAL; 434 435 if (pf2vf_info->size > 1024) { 436 DRM_ERROR("invalid pf2vf message size\n"); 437 return -EINVAL; 438 } 439 440 switch (pf2vf_info->version) { 441 case 1: 442 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 443 checkval = amd_sriov_msg_checksum( 444 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 445 adev->virt.fw_reserve.checksum_key, checksum); 446 if (checksum != checkval) { 447 DRM_ERROR("invalid pf2vf message\n"); 448 return -EINVAL; 449 } 450 451 adev->virt.gim_feature = 452 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 453 break; 454 case 2: 455 /* TODO: missing key, need to add it later */ 456 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 457 checkval = amd_sriov_msg_checksum( 458 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 459 0, checksum); 460 if (checksum != checkval) { 461 DRM_ERROR("invalid pf2vf message\n"); 462 return -EINVAL; 463 } 464 465 adev->virt.vf2pf_update_interval_ms = 466 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 467 adev->virt.gim_feature = 468 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 469 470 break; 471 default: 472 DRM_ERROR("invalid pf2vf version\n"); 473 return -EINVAL; 474 } 475 476 /* correct too large or too little interval value */ 477 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 478 adev->virt.vf2pf_update_interval_ms = 2000; 479 480 return 0; 481 } 482 483 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 484 { 485 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 486 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 487 488 if (adev->virt.fw_reserve.p_vf2pf == NULL) 489 return; 490 491 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 492 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 493 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 494 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 495 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 496 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 497 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 498 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 499 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 500 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 501 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 502 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 503 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos_fw_version); 504 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, adev->psp.asd_fw_version); 505 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, adev->psp.ta_ras_ucode_version); 506 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, adev->psp.ta_xgmi_ucode_version); 507 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 508 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 509 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 510 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 511 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 512 } 513 514 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 515 { 516 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 517 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 518 519 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 520 521 if (adev->virt.fw_reserve.p_vf2pf == NULL) 522 return -EINVAL; 523 524 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 525 526 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 527 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 528 529 #ifdef MODULE 530 if (THIS_MODULE->version != NULL) 531 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 532 else 533 #endif 534 strcpy(vf2pf_info->driver_version, "N/A"); 535 536 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 537 vf2pf_info->driver_cert = 0; 538 vf2pf_info->os_info.all = 0; 539 540 vf2pf_info->fb_usage = amdgpu_vram_mgr_usage(vram_man) >> 20; 541 vf2pf_info->fb_vis_usage = amdgpu_vram_mgr_vis_usage(vram_man) >> 20; 542 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 543 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 544 545 amdgpu_virt_populate_vf2pf_ucode_info(adev); 546 547 /* TODO: read dynamic info */ 548 vf2pf_info->gfx_usage = 0; 549 vf2pf_info->compute_usage = 0; 550 vf2pf_info->encode_usage = 0; 551 vf2pf_info->decode_usage = 0; 552 553 vf2pf_info->checksum = 554 amd_sriov_msg_checksum( 555 vf2pf_info, vf2pf_info->header.size, 0, 0); 556 557 return 0; 558 } 559 560 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 561 { 562 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 563 564 amdgpu_virt_read_pf2vf_data(adev); 565 amdgpu_virt_write_vf2pf_data(adev); 566 567 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 568 } 569 570 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 571 { 572 if (adev->virt.vf2pf_update_interval_ms != 0) { 573 DRM_INFO("clean up the vf2pf work item\n"); 574 flush_delayed_work(&adev->virt.vf2pf_work); 575 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 576 } 577 } 578 579 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 580 { 581 uint64_t bp_block_offset = 0; 582 uint32_t bp_block_size = 0; 583 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 584 585 adev->virt.fw_reserve.p_pf2vf = NULL; 586 adev->virt.fw_reserve.p_vf2pf = NULL; 587 adev->virt.vf2pf_update_interval_ms = 0; 588 589 if (adev->mman.fw_vram_usage_va != NULL) { 590 adev->virt.vf2pf_update_interval_ms = 2000; 591 592 adev->virt.fw_reserve.p_pf2vf = 593 (struct amd_sriov_msg_pf2vf_info_header *) 594 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 595 adev->virt.fw_reserve.p_vf2pf = 596 (struct amd_sriov_msg_vf2pf_info_header *) 597 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 598 599 amdgpu_virt_read_pf2vf_data(adev); 600 amdgpu_virt_write_vf2pf_data(adev); 601 602 /* bad page handling for version 2 */ 603 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 604 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 605 606 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 607 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 608 bp_block_size = pf2vf_v2->bp_block_size; 609 610 if (bp_block_size && !adev->virt.ras_init_done) 611 amdgpu_virt_init_ras_err_handler_data(adev); 612 613 if (adev->virt.ras_init_done) 614 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 615 } 616 } 617 618 if (adev->virt.vf2pf_update_interval_ms != 0) { 619 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 620 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 621 } 622 } 623 624 void amdgpu_detect_virtualization(struct amdgpu_device *adev) 625 { 626 uint32_t reg; 627 628 switch (adev->asic_type) { 629 case CHIP_TONGA: 630 case CHIP_FIJI: 631 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 632 break; 633 case CHIP_VEGA10: 634 case CHIP_VEGA20: 635 case CHIP_NAVI10: 636 case CHIP_NAVI12: 637 case CHIP_SIENNA_CICHLID: 638 case CHIP_ARCTURUS: 639 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 640 break; 641 default: /* other chip doesn't support SRIOV */ 642 reg = 0; 643 break; 644 } 645 646 if (reg & 1) 647 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 648 649 if (reg & 0x80000000) 650 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 651 652 if (!reg) { 653 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 654 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 655 } 656 657 /* we have the ability to check now */ 658 if (amdgpu_sriov_vf(adev)) { 659 switch (adev->asic_type) { 660 case CHIP_TONGA: 661 case CHIP_FIJI: 662 vi_set_virt_ops(adev); 663 break; 664 case CHIP_VEGA10: 665 case CHIP_VEGA20: 666 case CHIP_ARCTURUS: 667 soc15_set_virt_ops(adev); 668 break; 669 case CHIP_NAVI10: 670 case CHIP_NAVI12: 671 case CHIP_SIENNA_CICHLID: 672 nv_set_virt_ops(adev); 673 /* try send GPU_INIT_DATA request to host */ 674 amdgpu_virt_request_init_data(adev); 675 break; 676 default: /* other chip doesn't support SRIOV */ 677 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 678 break; 679 } 680 } 681 } 682 683 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 684 { 685 return amdgpu_sriov_is_debug(adev) ? true : false; 686 } 687 688 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 689 { 690 return amdgpu_sriov_is_normal(adev) ? true : false; 691 } 692 693 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 694 { 695 if (!amdgpu_sriov_vf(adev) || 696 amdgpu_virt_access_debugfs_is_kiq(adev)) 697 return 0; 698 699 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 700 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 701 else 702 return -EPERM; 703 704 return 0; 705 } 706 707 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 708 { 709 if (amdgpu_sriov_vf(adev)) 710 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 711 } 712 713 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 714 { 715 enum amdgpu_sriov_vf_mode mode; 716 717 if (amdgpu_sriov_vf(adev)) { 718 if (amdgpu_sriov_is_pp_one_vf(adev)) 719 mode = SRIOV_VF_MODE_ONE_VF; 720 else 721 mode = SRIOV_VF_MODE_MULTI_VF; 722 } else { 723 mode = SRIOV_VF_MODE_BARE_METAL; 724 } 725 726 return mode; 727 } 728