1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #ifdef CONFIG_X86 27 #include <asm/hypervisor.h> 28 #endif 29 30 #include <drm/drm_drv.h> 31 #include <xen/xen.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "vi.h" 36 #include "soc15.h" 37 #include "nv.h" 38 39 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 40 do { \ 41 vf2pf_info->ucode_info[ucode].id = ucode; \ 42 vf2pf_info->ucode_info[ucode].version = ver; \ 43 } while (0) 44 45 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 46 { 47 /* By now all MMIO pages except mailbox are blocked */ 48 /* if blocking is enabled in hypervisor. Choose the */ 49 /* SCRATCH_REG0 to test. */ 50 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 51 } 52 53 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 54 { 55 struct drm_device *ddev = adev_to_drm(adev); 56 57 /* enable virtual display */ 58 if (adev->asic_type != CHIP_ALDEBARAN && 59 adev->asic_type != CHIP_ARCTURUS) { 60 if (adev->mode_info.num_crtc == 0) 61 adev->mode_info.num_crtc = 1; 62 adev->enable_virtual_display = true; 63 } 64 ddev->driver_features &= ~DRIVER_ATOMIC; 65 adev->cg_flags = 0; 66 adev->pg_flags = 0; 67 68 /* enable mcbp for sriov asic_type before soc21 */ 69 amdgpu_mcbp = (adev->asic_type < CHIP_IP_DISCOVERY) ? 1 : 0; 70 71 } 72 73 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 74 uint32_t reg0, uint32_t reg1, 75 uint32_t ref, uint32_t mask) 76 { 77 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 78 struct amdgpu_ring *ring = &kiq->ring; 79 signed long r, cnt = 0; 80 unsigned long flags; 81 uint32_t seq; 82 83 if (adev->mes.ring.sched.ready) { 84 amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1, 85 ref, mask); 86 return; 87 } 88 89 spin_lock_irqsave(&kiq->ring_lock, flags); 90 amdgpu_ring_alloc(ring, 32); 91 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, 92 ref, mask); 93 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 94 if (r) 95 goto failed_undo; 96 97 amdgpu_ring_commit(ring); 98 spin_unlock_irqrestore(&kiq->ring_lock, flags); 99 100 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 101 102 /* don't wait anymore for IRQ context */ 103 if (r < 1 && in_interrupt()) 104 goto failed_kiq; 105 106 might_sleep(); 107 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 108 109 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 110 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 111 } 112 113 if (cnt > MAX_KIQ_REG_TRY) 114 goto failed_kiq; 115 116 return; 117 118 failed_undo: 119 amdgpu_ring_undo(ring); 120 spin_unlock_irqrestore(&kiq->ring_lock, flags); 121 failed_kiq: 122 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1); 123 } 124 125 /** 126 * amdgpu_virt_request_full_gpu() - request full gpu access 127 * @adev: amdgpu device. 128 * @init: is driver init time. 129 * When start to init/fini driver, first need to request full gpu access. 130 * Return: Zero if request success, otherwise will return error. 131 */ 132 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 133 { 134 struct amdgpu_virt *virt = &adev->virt; 135 int r; 136 137 if (virt->ops && virt->ops->req_full_gpu) { 138 r = virt->ops->req_full_gpu(adev, init); 139 if (r) 140 return r; 141 142 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 143 } 144 145 return 0; 146 } 147 148 /** 149 * amdgpu_virt_release_full_gpu() - release full gpu access 150 * @adev: amdgpu device. 151 * @init: is driver init time. 152 * When finishing driver init/fini, need to release full gpu access. 153 * Return: Zero if release success, otherwise will returen error. 154 */ 155 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 156 { 157 struct amdgpu_virt *virt = &adev->virt; 158 int r; 159 160 if (virt->ops && virt->ops->rel_full_gpu) { 161 r = virt->ops->rel_full_gpu(adev, init); 162 if (r) 163 return r; 164 165 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 166 } 167 return 0; 168 } 169 170 /** 171 * amdgpu_virt_reset_gpu() - reset gpu 172 * @adev: amdgpu device. 173 * Send reset command to GPU hypervisor to reset GPU that VM is using 174 * Return: Zero if reset success, otherwise will return error. 175 */ 176 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 177 { 178 struct amdgpu_virt *virt = &adev->virt; 179 int r; 180 181 if (virt->ops && virt->ops->reset_gpu) { 182 r = virt->ops->reset_gpu(adev); 183 if (r) 184 return r; 185 186 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 187 } 188 189 return 0; 190 } 191 192 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 193 { 194 struct amdgpu_virt *virt = &adev->virt; 195 196 if (virt->ops && virt->ops->req_init_data) 197 virt->ops->req_init_data(adev); 198 199 if (adev->virt.req_init_data_ver > 0) 200 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 201 else 202 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 203 } 204 205 /** 206 * amdgpu_virt_wait_reset() - wait for reset gpu completed 207 * @adev: amdgpu device. 208 * Wait for GPU reset completed. 209 * Return: Zero if reset success, otherwise will return error. 210 */ 211 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 212 { 213 struct amdgpu_virt *virt = &adev->virt; 214 215 if (!virt->ops || !virt->ops->wait_reset) 216 return -EINVAL; 217 218 return virt->ops->wait_reset(adev); 219 } 220 221 /** 222 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 223 * @adev: amdgpu device. 224 * MM table is used by UVD and VCE for its initialization 225 * Return: Zero if allocate success. 226 */ 227 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 228 { 229 int r; 230 231 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 232 return 0; 233 234 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 235 AMDGPU_GEM_DOMAIN_VRAM, 236 &adev->virt.mm_table.bo, 237 &adev->virt.mm_table.gpu_addr, 238 (void *)&adev->virt.mm_table.cpu_addr); 239 if (r) { 240 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 241 return r; 242 } 243 244 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 245 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 246 adev->virt.mm_table.gpu_addr, 247 adev->virt.mm_table.cpu_addr); 248 return 0; 249 } 250 251 /** 252 * amdgpu_virt_free_mm_table() - free mm table memory 253 * @adev: amdgpu device. 254 * Free MM table memory 255 */ 256 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 257 { 258 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 259 return; 260 261 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 262 &adev->virt.mm_table.gpu_addr, 263 (void *)&adev->virt.mm_table.cpu_addr); 264 adev->virt.mm_table.gpu_addr = 0; 265 } 266 267 268 unsigned int amd_sriov_msg_checksum(void *obj, 269 unsigned long obj_size, 270 unsigned int key, 271 unsigned int checksum) 272 { 273 unsigned int ret = key; 274 unsigned long i = 0; 275 unsigned char *pos; 276 277 pos = (char *)obj; 278 /* calculate checksum */ 279 for (i = 0; i < obj_size; ++i) 280 ret += *(pos + i); 281 /* minus the checksum itself */ 282 pos = (char *)&checksum; 283 for (i = 0; i < sizeof(checksum); ++i) 284 ret -= *(pos + i); 285 return ret; 286 } 287 288 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 289 { 290 struct amdgpu_virt *virt = &adev->virt; 291 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 292 /* GPU will be marked bad on host if bp count more then 10, 293 * so alloc 512 is enough. 294 */ 295 unsigned int align_space = 512; 296 void *bps = NULL; 297 struct amdgpu_bo **bps_bo = NULL; 298 299 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 300 if (!*data) 301 goto data_failure; 302 303 bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL); 304 if (!bps) 305 goto bps_failure; 306 307 bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL); 308 if (!bps_bo) 309 goto bps_bo_failure; 310 311 (*data)->bps = bps; 312 (*data)->bps_bo = bps_bo; 313 (*data)->count = 0; 314 (*data)->last_reserved = 0; 315 316 virt->ras_init_done = true; 317 318 return 0; 319 320 bps_bo_failure: 321 kfree(bps); 322 bps_failure: 323 kfree(*data); 324 data_failure: 325 return -ENOMEM; 326 } 327 328 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 329 { 330 struct amdgpu_virt *virt = &adev->virt; 331 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 332 struct amdgpu_bo *bo; 333 int i; 334 335 if (!data) 336 return; 337 338 for (i = data->last_reserved - 1; i >= 0; i--) { 339 bo = data->bps_bo[i]; 340 amdgpu_bo_free_kernel(&bo, NULL, NULL); 341 data->bps_bo[i] = bo; 342 data->last_reserved = i; 343 } 344 } 345 346 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 347 { 348 struct amdgpu_virt *virt = &adev->virt; 349 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 350 351 virt->ras_init_done = false; 352 353 if (!data) 354 return; 355 356 amdgpu_virt_ras_release_bp(adev); 357 358 kfree(data->bps); 359 kfree(data->bps_bo); 360 kfree(data); 361 virt->virt_eh_data = NULL; 362 } 363 364 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 365 struct eeprom_table_record *bps, int pages) 366 { 367 struct amdgpu_virt *virt = &adev->virt; 368 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 369 370 if (!data) 371 return; 372 373 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 374 data->count += pages; 375 } 376 377 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 378 { 379 struct amdgpu_virt *virt = &adev->virt; 380 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 381 struct amdgpu_bo *bo = NULL; 382 uint64_t bp; 383 int i; 384 385 if (!data) 386 return; 387 388 for (i = data->last_reserved; i < data->count; i++) { 389 bp = data->bps[i].retired_page; 390 391 /* There are two cases of reserve error should be ignored: 392 * 1) a ras bad page has been allocated (used by someone); 393 * 2) a ras bad page has been reserved (duplicate error injection 394 * for one page); 395 */ 396 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 397 AMDGPU_GPU_PAGE_SIZE, 398 AMDGPU_GEM_DOMAIN_VRAM, 399 &bo, NULL)) 400 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 401 402 data->bps_bo[i] = bo; 403 data->last_reserved = i + 1; 404 bo = NULL; 405 } 406 } 407 408 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 409 uint64_t retired_page) 410 { 411 struct amdgpu_virt *virt = &adev->virt; 412 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 413 int i; 414 415 if (!data) 416 return true; 417 418 for (i = 0; i < data->count; i++) 419 if (retired_page == data->bps[i].retired_page) 420 return true; 421 422 return false; 423 } 424 425 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 426 uint64_t bp_block_offset, uint32_t bp_block_size) 427 { 428 struct eeprom_table_record bp; 429 uint64_t retired_page; 430 uint32_t bp_idx, bp_cnt; 431 432 if (bp_block_size) { 433 bp_cnt = bp_block_size / sizeof(uint64_t); 434 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 435 retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va + 436 bp_block_offset + bp_idx * sizeof(uint64_t)); 437 bp.retired_page = retired_page; 438 439 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 440 continue; 441 442 amdgpu_virt_ras_add_bps(adev, &bp, 1); 443 444 amdgpu_virt_ras_reserve_bps(adev); 445 } 446 } 447 } 448 449 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 450 { 451 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 452 uint32_t checksum; 453 uint32_t checkval; 454 455 uint32_t i; 456 uint32_t tmp; 457 458 if (adev->virt.fw_reserve.p_pf2vf == NULL) 459 return -EINVAL; 460 461 if (pf2vf_info->size > 1024) { 462 DRM_ERROR("invalid pf2vf message size\n"); 463 return -EINVAL; 464 } 465 466 switch (pf2vf_info->version) { 467 case 1: 468 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 469 checkval = amd_sriov_msg_checksum( 470 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 471 adev->virt.fw_reserve.checksum_key, checksum); 472 if (checksum != checkval) { 473 DRM_ERROR("invalid pf2vf message\n"); 474 return -EINVAL; 475 } 476 477 adev->virt.gim_feature = 478 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 479 break; 480 case 2: 481 /* TODO: missing key, need to add it later */ 482 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 483 checkval = amd_sriov_msg_checksum( 484 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 485 0, checksum); 486 if (checksum != checkval) { 487 DRM_ERROR("invalid pf2vf message\n"); 488 return -EINVAL; 489 } 490 491 adev->virt.vf2pf_update_interval_ms = 492 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 493 adev->virt.gim_feature = 494 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 495 adev->virt.reg_access = 496 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 497 498 adev->virt.decode_max_dimension_pixels = 0; 499 adev->virt.decode_max_frame_pixels = 0; 500 adev->virt.encode_max_dimension_pixels = 0; 501 adev->virt.encode_max_frame_pixels = 0; 502 adev->virt.is_mm_bw_enabled = false; 503 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 504 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 505 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 506 507 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 508 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 509 510 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 511 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 512 513 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 514 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 515 } 516 if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 517 adev->virt.is_mm_bw_enabled = true; 518 519 adev->unique_id = 520 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 521 break; 522 default: 523 DRM_ERROR("invalid pf2vf version\n"); 524 return -EINVAL; 525 } 526 527 /* correct too large or too little interval value */ 528 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 529 adev->virt.vf2pf_update_interval_ms = 2000; 530 531 return 0; 532 } 533 534 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 535 { 536 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 537 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 538 539 if (adev->virt.fw_reserve.p_vf2pf == NULL) 540 return; 541 542 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 543 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 544 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 545 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 546 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 547 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 548 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 549 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 550 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 551 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 552 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 553 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 554 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_IMU, adev->gfx.imu_fw_version); 555 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 556 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, 557 adev->psp.asd_context.bin_desc.fw_version); 558 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, 559 adev->psp.ras_context.context.bin_desc.fw_version); 560 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, 561 adev->psp.xgmi_context.context.bin_desc.fw_version); 562 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 563 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 564 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 565 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 566 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 567 } 568 569 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 570 { 571 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 572 573 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 574 575 if (adev->virt.fw_reserve.p_vf2pf == NULL) 576 return -EINVAL; 577 578 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 579 580 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 581 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 582 583 #ifdef MODULE 584 if (THIS_MODULE->version != NULL) 585 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 586 else 587 #endif 588 strcpy(vf2pf_info->driver_version, "N/A"); 589 590 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 591 vf2pf_info->driver_cert = 0; 592 vf2pf_info->os_info.all = 0; 593 594 vf2pf_info->fb_usage = 595 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; 596 vf2pf_info->fb_vis_usage = 597 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 598 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 599 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 600 601 amdgpu_virt_populate_vf2pf_ucode_info(adev); 602 603 /* TODO: read dynamic info */ 604 vf2pf_info->gfx_usage = 0; 605 vf2pf_info->compute_usage = 0; 606 vf2pf_info->encode_usage = 0; 607 vf2pf_info->decode_usage = 0; 608 609 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; 610 vf2pf_info->checksum = 611 amd_sriov_msg_checksum( 612 vf2pf_info, vf2pf_info->header.size, 0, 0); 613 614 return 0; 615 } 616 617 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 618 { 619 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 620 int ret; 621 622 ret = amdgpu_virt_read_pf2vf_data(adev); 623 if (ret) 624 goto out; 625 amdgpu_virt_write_vf2pf_data(adev); 626 627 out: 628 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 629 } 630 631 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 632 { 633 if (adev->virt.vf2pf_update_interval_ms != 0) { 634 DRM_INFO("clean up the vf2pf work item\n"); 635 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 636 adev->virt.vf2pf_update_interval_ms = 0; 637 } 638 } 639 640 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 641 { 642 adev->virt.fw_reserve.p_pf2vf = NULL; 643 adev->virt.fw_reserve.p_vf2pf = NULL; 644 adev->virt.vf2pf_update_interval_ms = 0; 645 646 if (adev->mman.fw_vram_usage_va != NULL) { 647 /* go through this logic in ip_init and reset to init workqueue*/ 648 amdgpu_virt_exchange_data(adev); 649 650 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 651 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 652 } else if (adev->bios != NULL) { 653 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 654 adev->virt.fw_reserve.p_pf2vf = 655 (struct amd_sriov_msg_pf2vf_info_header *) 656 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 657 658 amdgpu_virt_read_pf2vf_data(adev); 659 } 660 } 661 662 663 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 664 { 665 uint64_t bp_block_offset = 0; 666 uint32_t bp_block_size = 0; 667 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 668 669 if (adev->mman.fw_vram_usage_va != NULL) { 670 671 adev->virt.fw_reserve.p_pf2vf = 672 (struct amd_sriov_msg_pf2vf_info_header *) 673 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 674 adev->virt.fw_reserve.p_vf2pf = 675 (struct amd_sriov_msg_vf2pf_info_header *) 676 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 677 678 amdgpu_virt_read_pf2vf_data(adev); 679 amdgpu_virt_write_vf2pf_data(adev); 680 681 /* bad page handling for version 2 */ 682 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 683 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 684 685 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 686 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 687 bp_block_size = pf2vf_v2->bp_block_size; 688 689 if (bp_block_size && !adev->virt.ras_init_done) 690 amdgpu_virt_init_ras_err_handler_data(adev); 691 692 if (adev->virt.ras_init_done) 693 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 694 } 695 } 696 } 697 698 void amdgpu_detect_virtualization(struct amdgpu_device *adev) 699 { 700 uint32_t reg; 701 702 switch (adev->asic_type) { 703 case CHIP_TONGA: 704 case CHIP_FIJI: 705 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 706 break; 707 case CHIP_VEGA10: 708 case CHIP_VEGA20: 709 case CHIP_NAVI10: 710 case CHIP_NAVI12: 711 case CHIP_SIENNA_CICHLID: 712 case CHIP_ARCTURUS: 713 case CHIP_ALDEBARAN: 714 case CHIP_IP_DISCOVERY: 715 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 716 break; 717 default: /* other chip doesn't support SRIOV */ 718 reg = 0; 719 break; 720 } 721 722 if (reg & 1) 723 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 724 725 if (reg & 0x80000000) 726 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 727 728 if (!reg) { 729 /* passthrough mode exclus sriov mod */ 730 if (is_virtual_machine() && !xen_initial_domain()) 731 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 732 } 733 734 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) 735 /* VF MMIO access (except mailbox range) from CPU 736 * will be blocked during sriov runtime 737 */ 738 adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT; 739 740 /* we have the ability to check now */ 741 if (amdgpu_sriov_vf(adev)) { 742 switch (adev->asic_type) { 743 case CHIP_TONGA: 744 case CHIP_FIJI: 745 vi_set_virt_ops(adev); 746 break; 747 case CHIP_VEGA10: 748 soc15_set_virt_ops(adev); 749 #ifdef CONFIG_X86 750 /* not send GPU_INIT_DATA with MS_HYPERV*/ 751 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV)) 752 #endif 753 /* send a dummy GPU_INIT_DATA request to host on vega10 */ 754 amdgpu_virt_request_init_data(adev); 755 break; 756 case CHIP_VEGA20: 757 case CHIP_ARCTURUS: 758 case CHIP_ALDEBARAN: 759 soc15_set_virt_ops(adev); 760 break; 761 case CHIP_NAVI10: 762 case CHIP_NAVI12: 763 case CHIP_SIENNA_CICHLID: 764 case CHIP_IP_DISCOVERY: 765 nv_set_virt_ops(adev); 766 /* try send GPU_INIT_DATA request to host */ 767 amdgpu_virt_request_init_data(adev); 768 break; 769 default: /* other chip doesn't support SRIOV */ 770 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 771 break; 772 } 773 } 774 } 775 776 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 777 { 778 return amdgpu_sriov_is_debug(adev) ? true : false; 779 } 780 781 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 782 { 783 return amdgpu_sriov_is_normal(adev) ? true : false; 784 } 785 786 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 787 { 788 if (!amdgpu_sriov_vf(adev) || 789 amdgpu_virt_access_debugfs_is_kiq(adev)) 790 return 0; 791 792 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 793 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 794 else 795 return -EPERM; 796 797 return 0; 798 } 799 800 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 801 { 802 if (amdgpu_sriov_vf(adev)) 803 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 804 } 805 806 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 807 { 808 enum amdgpu_sriov_vf_mode mode; 809 810 if (amdgpu_sriov_vf(adev)) { 811 if (amdgpu_sriov_is_pp_one_vf(adev)) 812 mode = SRIOV_VF_MODE_ONE_VF; 813 else 814 mode = SRIOV_VF_MODE_MULTI_VF; 815 } else { 816 mode = SRIOV_VF_MODE_BARE_METAL; 817 } 818 819 return mode; 820 } 821 822 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) 823 { 824 switch (adev->ip_versions[MP0_HWIP][0]) { 825 case IP_VERSION(13, 0, 0): 826 /* no vf autoload, white list */ 827 if (ucode_id == AMDGPU_UCODE_ID_VCN1 || 828 ucode_id == AMDGPU_UCODE_ID_VCN) 829 return false; 830 else 831 return true; 832 case IP_VERSION(13, 0, 10): 833 /* white list */ 834 if (ucode_id == AMDGPU_UCODE_ID_CAP 835 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP 836 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME 837 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC 838 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK 839 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK 840 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK 841 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK 842 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK 843 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK 844 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK 845 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK 846 || ucode_id == AMDGPU_UCODE_ID_CP_MES 847 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA 848 || ucode_id == AMDGPU_UCODE_ID_CP_MES1 849 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA 850 || ucode_id == AMDGPU_UCODE_ID_VCN1 851 || ucode_id == AMDGPU_UCODE_ID_VCN) 852 return false; 853 else 854 return true; 855 default: 856 /* lagacy black list */ 857 if (ucode_id == AMDGPU_UCODE_ID_SDMA0 858 || ucode_id == AMDGPU_UCODE_ID_SDMA1 859 || ucode_id == AMDGPU_UCODE_ID_SDMA2 860 || ucode_id == AMDGPU_UCODE_ID_SDMA3 861 || ucode_id == AMDGPU_UCODE_ID_SDMA4 862 || ucode_id == AMDGPU_UCODE_ID_SDMA5 863 || ucode_id == AMDGPU_UCODE_ID_SDMA6 864 || ucode_id == AMDGPU_UCODE_ID_SDMA7 865 || ucode_id == AMDGPU_UCODE_ID_RLC_G 866 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 867 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 868 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 869 || ucode_id == AMDGPU_UCODE_ID_SMC) 870 return true; 871 else 872 return false; 873 } 874 } 875 876 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 877 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 878 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 879 { 880 uint32_t i; 881 882 if (!adev->virt.is_mm_bw_enabled) 883 return; 884 885 if (encode) { 886 for (i = 0; i < encode_array_size; i++) { 887 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 888 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 889 if (encode[i].max_width > 0) 890 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 891 else 892 encode[i].max_height = 0; 893 } 894 } 895 896 if (decode) { 897 for (i = 0; i < decode_array_size; i++) { 898 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 899 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 900 if (decode[i].max_width > 0) 901 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 902 else 903 decode[i].max_height = 0; 904 } 905 } 906 } 907 908 static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 909 u32 acc_flags, u32 hwip, 910 bool write, u32 *rlcg_flag) 911 { 912 bool ret = false; 913 914 switch (hwip) { 915 case GC_HWIP: 916 if (amdgpu_sriov_reg_indirect_gc(adev)) { 917 *rlcg_flag = 918 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ; 919 ret = true; 920 /* only in new version, AMDGPU_REGS_NO_KIQ and 921 * AMDGPU_REGS_RLC are enabled simultaneously */ 922 } else if ((acc_flags & AMDGPU_REGS_RLC) && 923 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { 924 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; 925 ret = true; 926 } 927 break; 928 case MMHUB_HWIP: 929 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 930 (acc_flags & AMDGPU_REGS_RLC) && write) { 931 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE; 932 ret = true; 933 } 934 break; 935 default: 936 break; 937 } 938 return ret; 939 } 940 941 static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag) 942 { 943 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 944 uint32_t timeout = 50000; 945 uint32_t i, tmp; 946 uint32_t ret = 0; 947 void *scratch_reg0; 948 void *scratch_reg1; 949 void *scratch_reg2; 950 void *scratch_reg3; 951 void *spare_int; 952 953 if (!adev->gfx.rlc.rlcg_reg_access_supported) { 954 dev_err(adev->dev, 955 "indirect registers access through rlcg is not available\n"); 956 return 0; 957 } 958 959 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 960 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; 961 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; 962 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; 963 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; 964 if (reg_access_ctrl->spare_int) 965 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; 966 967 if (offset == reg_access_ctrl->grbm_cntl) { 968 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */ 969 writel(v, scratch_reg2); 970 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 971 } else if (offset == reg_access_ctrl->grbm_idx) { 972 /* if the target reg offset is grbm_idx, write to scratch_reg3 */ 973 writel(v, scratch_reg3); 974 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 975 } else { 976 /* 977 * SCRATCH_REG0 = read/write value 978 * SCRATCH_REG1[30:28] = command 979 * SCRATCH_REG1[19:0] = address in dword 980 * SCRATCH_REG1[26:24] = Error reporting 981 */ 982 writel(v, scratch_reg0); 983 writel((offset | flag), scratch_reg1); 984 if (reg_access_ctrl->spare_int) 985 writel(1, spare_int); 986 987 for (i = 0; i < timeout; i++) { 988 tmp = readl(scratch_reg1); 989 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK)) 990 break; 991 udelay(10); 992 } 993 994 if (i >= timeout) { 995 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { 996 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) { 997 dev_err(adev->dev, 998 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset); 999 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) { 1000 dev_err(adev->dev, 1001 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset); 1002 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) { 1003 dev_err(adev->dev, 1004 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset); 1005 } else { 1006 dev_err(adev->dev, 1007 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset); 1008 } 1009 } else { 1010 dev_err(adev->dev, 1011 "timeout: rlcg faled to program reg: 0x%05x\n", offset); 1012 } 1013 } 1014 } 1015 1016 ret = readl(scratch_reg0); 1017 return ret; 1018 } 1019 1020 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 1021 u32 offset, u32 value, 1022 u32 acc_flags, u32 hwip) 1023 { 1024 u32 rlcg_flag; 1025 1026 if (!amdgpu_sriov_runtime(adev) && 1027 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { 1028 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag); 1029 return; 1030 } 1031 1032 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1033 WREG32_NO_KIQ(offset, value); 1034 else 1035 WREG32(offset, value); 1036 } 1037 1038 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 1039 u32 offset, u32 acc_flags, u32 hwip) 1040 { 1041 u32 rlcg_flag; 1042 1043 if (!amdgpu_sriov_runtime(adev) && 1044 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) 1045 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag); 1046 1047 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1048 return RREG32_NO_KIQ(offset); 1049 else 1050 return RREG32(offset); 1051 } 1052