189041940SGavin Wan /* 289041940SGavin Wan * Copyright 2017 Advanced Micro Devices, Inc. 389041940SGavin Wan * 489041940SGavin Wan * Permission is hereby granted, free of charge, to any person obtaining a 589041940SGavin Wan * copy of this software and associated documentation files (the "Software"), 689041940SGavin Wan * to deal in the Software without restriction, including without limitation 789041940SGavin Wan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 889041940SGavin Wan * and/or sell copies of the Software, and to permit persons to whom the 989041940SGavin Wan * Software is furnished to do so, subject to the following conditions: 1089041940SGavin Wan * 1189041940SGavin Wan * The above copyright notice and this permission notice shall be included in 1289041940SGavin Wan * all copies or substantial portions of the Software. 1389041940SGavin Wan * 1489041940SGavin Wan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1589041940SGavin Wan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1689041940SGavin Wan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1789041940SGavin Wan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1889041940SGavin Wan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1989041940SGavin Wan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2089041940SGavin Wan * OTHER DEALINGS IN THE SOFTWARE. 2189041940SGavin Wan * 2289041940SGavin Wan */ 2389041940SGavin Wan 2489041940SGavin Wan #ifndef __VF_ERROR_H__ 2589041940SGavin Wan #define __VF_ERROR_H__ 2689041940SGavin Wan 2789041940SGavin Wan #define AMDGIM_ERROR_CODE_FLAGS_TO_MAILBOX(c,f) (((c & 0xFFFF) << 16) | (f & 0xFFFF)) 2889041940SGavin Wan #define AMDGIM_ERROR_CODE(t,c) (((t&0xF)<<12)|(c&0xFFF)) 2989041940SGavin Wan 3089041940SGavin Wan /* Please keep enum same as AMD GIM driver */ 3189041940SGavin Wan enum AMDGIM_ERROR_VF { 3289041940SGavin Wan AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL = 0, 3389041940SGavin Wan AMDGIM_ERROR_VF_NO_VBIOS, 3489041940SGavin Wan AMDGIM_ERROR_VF_GPU_POST_ERROR, 3589041940SGavin Wan AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 3689041940SGavin Wan AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 3789041940SGavin Wan 3889041940SGavin Wan AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 3989041940SGavin Wan AMDGIM_ERROR_VF_IB_INIT_FAIL, 4089041940SGavin Wan AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 4189041940SGavin Wan AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 4289041940SGavin Wan AMDGIM_ERROR_VF_GPU_RESET_FAIL, 4389041940SGavin Wan 4489041940SGavin Wan AMDGIM_ERROR_VF_TEST, 4589041940SGavin Wan AMDGIM_ERROR_VF_MAX 4689041940SGavin Wan }; 4789041940SGavin Wan 4889041940SGavin Wan enum AMDGIM_ERROR_CATEGORY { 4989041940SGavin Wan AMDGIM_ERROR_CATEGORY_NON_USED = 0, 5089041940SGavin Wan AMDGIM_ERROR_CATEGORY_GIM, 5189041940SGavin Wan AMDGIM_ERROR_CATEGORY_PF, 5289041940SGavin Wan AMDGIM_ERROR_CATEGORY_VF, 5389041940SGavin Wan AMDGIM_ERROR_CATEGORY_VBIOS, 5489041940SGavin Wan AMDGIM_ERROR_CATEGORY_MONITOR, 5589041940SGavin Wan 5689041940SGavin Wan AMDGIM_ERROR_CATEGORY_MAX 5789041940SGavin Wan }; 5889041940SGavin Wan 59e23b74aaSAlex Deucher void amdgpu_vf_error_put(struct amdgpu_device *adev, 60e23b74aaSAlex Deucher uint16_t sub_error_code, 61e23b74aaSAlex Deucher uint16_t error_flags, 62e23b74aaSAlex Deucher uint64_t error_data); 6389041940SGavin Wan void amdgpu_vf_error_trans_all (struct amdgpu_device *adev); 6489041940SGavin Wan 6589041940SGavin Wan #endif /* __VF_ERROR_H__ */ 66