1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_VCN_H__ 25 #define __AMDGPU_VCN_H__ 26 27 #define AMDGPU_VCN_STACK_SIZE (128*1024) 28 #define AMDGPU_VCN_CONTEXT_SIZE (512*1024) 29 30 #define AMDGPU_VCN_FIRMWARE_OFFSET 256 31 #define AMDGPU_VCN_MAX_ENC_RINGS 3 32 33 #define VCN_DEC_CMD_FENCE 0x00000000 34 #define VCN_DEC_CMD_TRAP 0x00000001 35 #define VCN_DEC_CMD_WRITE_REG 0x00000004 36 #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006 37 #define VCN_DEC_CMD_PACKET_START 0x0000000a 38 #define VCN_DEC_CMD_PACKET_END 0x0000000b 39 40 #define VCN_ENC_CMD_NO_OP 0x00000000 41 #define VCN_ENC_CMD_END 0x00000001 42 #define VCN_ENC_CMD_IB 0x00000002 43 #define VCN_ENC_CMD_FENCE 0x00000003 44 #define VCN_ENC_CMD_TRAP 0x00000004 45 #define VCN_ENC_CMD_REG_WRITE 0x0000000b 46 #define VCN_ENC_CMD_REG_WAIT 0x0000000c 47 48 #define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \ 49 ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ 50 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ 51 UVD_DPG_LMA_CTL__MASK_EN_MASK | \ 52 ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ 53 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 54 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 55 RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \ 56 }) 57 58 #define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \ 59 do { \ 60 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \ 61 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ 62 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ 63 UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ 64 ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ 65 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 66 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 67 } while (0) 68 69 enum engine_status_constants { 70 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, 71 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002, 72 UVD_STATUS__UVD_BUSY = 0x00000004, 73 GB_ADDR_CONFIG_DEFAULT = 0x26010011, 74 UVD_STATUS__IDLE = 0x2, 75 UVD_STATUS__BUSY = 0x5, 76 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1, 77 UVD_STATUS__RBC_BUSY = 0x1, 78 }; 79 80 enum internal_dpg_state { 81 VCN_DPG_STATE__UNPAUSE = 0, 82 VCN_DPG_STATE__PAUSE, 83 }; 84 85 struct dpg_pause_state { 86 enum internal_dpg_state fw_based; 87 enum internal_dpg_state jpeg; 88 }; 89 90 struct amdgpu_vcn { 91 struct amdgpu_bo *vcpu_bo; 92 void *cpu_addr; 93 uint64_t gpu_addr; 94 unsigned fw_version; 95 void *saved_bo; 96 struct delayed_work idle_work; 97 const struct firmware *fw; /* VCN firmware */ 98 struct amdgpu_ring ring_dec; 99 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; 100 struct amdgpu_ring ring_jpeg; 101 struct amdgpu_irq_src irq; 102 unsigned num_enc_rings; 103 enum amd_powergating_state cur_state; 104 struct dpg_pause_state pause_state; 105 int (*pause_dpg_mode)(struct amdgpu_device *adev, 106 struct dpg_pause_state *new_state); 107 }; 108 109 int amdgpu_vcn_sw_init(struct amdgpu_device *adev); 110 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); 111 int amdgpu_vcn_suspend(struct amdgpu_device *adev); 112 int amdgpu_vcn_resume(struct amdgpu_device *adev); 113 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); 114 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); 115 116 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); 117 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); 118 119 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); 120 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); 121 122 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring); 123 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout); 124 125 #endif 126