1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_VCN_H__ 25 #define __AMDGPU_VCN_H__ 26 27 #define AMDGPU_VCN_STACK_SIZE (128*1024) 28 #define AMDGPU_VCN_CONTEXT_SIZE (512*1024) 29 30 #define AMDGPU_VCN_FIRMWARE_OFFSET 256 31 #define AMDGPU_VCN_MAX_ENC_RINGS 3 32 33 #define AMDGPU_MAX_VCN_INSTANCES 2 34 35 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0) 36 #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1) 37 38 #define VCN_DEC_CMD_FENCE 0x00000000 39 #define VCN_DEC_CMD_TRAP 0x00000001 40 #define VCN_DEC_CMD_WRITE_REG 0x00000004 41 #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006 42 #define VCN_DEC_CMD_PACKET_START 0x0000000a 43 #define VCN_DEC_CMD_PACKET_END 0x0000000b 44 45 #define VCN_ENC_CMD_NO_OP 0x00000000 46 #define VCN_ENC_CMD_END 0x00000001 47 #define VCN_ENC_CMD_IB 0x00000002 48 #define VCN_ENC_CMD_FENCE 0x00000003 49 #define VCN_ENC_CMD_TRAP 0x00000004 50 #define VCN_ENC_CMD_REG_WRITE 0x0000000b 51 #define VCN_ENC_CMD_REG_WAIT 0x0000000c 52 53 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 54 #define VCN_AON_SOC_ADDRESS_2_0 0x1f800 55 #define VCN_VID_IP_ADDRESS_2_0 0x0 56 #define VCN_AON_IP_ADDRESS_2_0 0x30000 57 58 #define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \ 59 ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ 60 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ 61 UVD_DPG_LMA_CTL__MASK_EN_MASK | \ 62 ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ 63 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 64 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 65 RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \ 66 }) 67 68 #define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \ 69 do { \ 70 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \ 71 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ 72 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ 73 UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ 74 ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ 75 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 76 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 77 } while (0) 78 79 #define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) \ 80 ({ \ 81 uint32_t internal_reg_offset, addr; \ 82 bool video_range, aon_range; \ 83 \ 84 addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 85 addr <<= 2; \ 86 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \ 87 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \ 88 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \ 89 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \ 90 if (video_range) \ 91 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \ 92 (VCN_VID_IP_ADDRESS_2_0)); \ 93 else if (aon_range) \ 94 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \ 95 (VCN_AON_IP_ADDRESS_2_0)); \ 96 else \ 97 internal_reg_offset = (0xFFFFF & addr); \ 98 \ 99 internal_reg_offset >>= 2; \ 100 }) 101 102 #define RREG32_SOC15_DPG_MODE_2_0(offset, mask_en) \ 103 ({ \ 104 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \ 105 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 106 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 107 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 108 RREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA); \ 109 }) 110 111 #define WREG32_SOC15_DPG_MODE_2_0(offset, value, mask_en, indirect) \ 112 do { \ 113 if (!indirect) { \ 114 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA, value); \ 115 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \ 116 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 117 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 118 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 119 } else { \ 120 *adev->vcn.dpg_sram_curr_addr++ = offset; \ 121 *adev->vcn.dpg_sram_curr_addr++ = value; \ 122 } \ 123 } while (0) 124 125 enum engine_status_constants { 126 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, 127 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0, 128 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002, 129 UVD_STATUS__UVD_BUSY = 0x00000004, 130 GB_ADDR_CONFIG_DEFAULT = 0x26010011, 131 UVD_STATUS__IDLE = 0x2, 132 UVD_STATUS__BUSY = 0x5, 133 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1, 134 UVD_STATUS__RBC_BUSY = 0x1, 135 UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0, 136 }; 137 138 enum internal_dpg_state { 139 VCN_DPG_STATE__UNPAUSE = 0, 140 VCN_DPG_STATE__PAUSE, 141 }; 142 143 struct dpg_pause_state { 144 enum internal_dpg_state fw_based; 145 enum internal_dpg_state jpeg; 146 }; 147 148 struct amdgpu_vcn_reg{ 149 unsigned data0; 150 unsigned data1; 151 unsigned cmd; 152 unsigned nop; 153 unsigned context_id; 154 unsigned ib_vmid; 155 unsigned ib_bar_low; 156 unsigned ib_bar_high; 157 unsigned ib_size; 158 unsigned gp_scratch8; 159 unsigned scratch9; 160 unsigned jpeg_pitch; 161 }; 162 163 struct amdgpu_vcn_inst { 164 struct amdgpu_bo *vcpu_bo; 165 void *cpu_addr; 166 uint64_t gpu_addr; 167 void *saved_bo; 168 struct amdgpu_ring ring_dec; 169 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; 170 struct amdgpu_ring ring_jpeg; 171 struct amdgpu_irq_src irq; 172 struct amdgpu_vcn_reg external; 173 }; 174 175 struct amdgpu_vcn { 176 unsigned fw_version; 177 struct delayed_work idle_work; 178 const struct firmware *fw; /* VCN firmware */ 179 unsigned num_enc_rings; 180 enum amd_powergating_state cur_state; 181 struct dpg_pause_state pause_state; 182 183 bool indirect_sram; 184 struct amdgpu_bo *dpg_sram_bo; 185 void *dpg_sram_cpu_addr; 186 uint64_t dpg_sram_gpu_addr; 187 uint32_t *dpg_sram_curr_addr; 188 189 uint8_t num_vcn_inst; 190 struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES]; 191 struct amdgpu_vcn_reg internal; 192 193 unsigned harvest_config; 194 int (*pause_dpg_mode)(struct amdgpu_device *adev, 195 struct dpg_pause_state *new_state); 196 }; 197 198 int amdgpu_vcn_sw_init(struct amdgpu_device *adev); 199 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); 200 int amdgpu_vcn_suspend(struct amdgpu_device *adev); 201 int amdgpu_vcn_resume(struct amdgpu_device *adev); 202 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); 203 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); 204 205 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); 206 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); 207 208 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); 209 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); 210 211 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring); 212 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout); 213 214 #endif 215