1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_VCN_H__ 25 #define __AMDGPU_VCN_H__ 26 27 #define AMDGPU_VCN_STACK_SIZE (128*1024) 28 #define AMDGPU_VCN_CONTEXT_SIZE (512*1024) 29 30 #define AMDGPU_VCN_FIRMWARE_OFFSET 256 31 #define AMDGPU_VCN_MAX_ENC_RINGS 3 32 33 #define VCN_DEC_CMD_FENCE 0x00000000 34 #define VCN_DEC_CMD_TRAP 0x00000001 35 #define VCN_DEC_CMD_WRITE_REG 0x00000004 36 #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006 37 #define VCN_DEC_CMD_PACKET_START 0x0000000a 38 #define VCN_DEC_CMD_PACKET_END 0x0000000b 39 40 #define VCN_ENC_CMD_NO_OP 0x00000000 41 #define VCN_ENC_CMD_END 0x00000001 42 #define VCN_ENC_CMD_IB 0x00000002 43 #define VCN_ENC_CMD_FENCE 0x00000003 44 #define VCN_ENC_CMD_TRAP 0x00000004 45 #define VCN_ENC_CMD_REG_WRITE 0x0000000b 46 #define VCN_ENC_CMD_REG_WAIT 0x0000000c 47 48 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 49 #define VCN_AON_SOC_ADDRESS_2_0 0x1f800 50 #define VCN_VID_IP_ADDRESS_2_0 0x0 51 #define VCN_AON_IP_ADDRESS_2_0 0x30000 52 53 #define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \ 54 ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ 55 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ 56 UVD_DPG_LMA_CTL__MASK_EN_MASK | \ 57 ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ 58 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 59 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 60 RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \ 61 }) 62 63 #define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \ 64 do { \ 65 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \ 66 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ 67 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ 68 UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ 69 ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ 70 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 71 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 72 } while (0) 73 74 #define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) \ 75 ({ \ 76 uint32_t internal_reg_offset, addr; \ 77 bool video_range, aon_range; \ 78 \ 79 addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 80 addr <<= 2; \ 81 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \ 82 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \ 83 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \ 84 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \ 85 if (video_range) \ 86 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \ 87 (VCN_VID_IP_ADDRESS_2_0)); \ 88 else if (aon_range) \ 89 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \ 90 (VCN_AON_IP_ADDRESS_2_0)); \ 91 else \ 92 internal_reg_offset = (0xFFFFF & addr); \ 93 \ 94 internal_reg_offset >>= 2; \ 95 }) 96 97 #define RREG32_SOC15_DPG_MODE_2_0(offset, mask_en) \ 98 ({ \ 99 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \ 100 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 101 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 102 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 103 RREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA); \ 104 }) 105 106 #define WREG32_SOC15_DPG_MODE_2_0(offset, value, mask_en, indirect) \ 107 do { \ 108 if (!indirect) { \ 109 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA, value); \ 110 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \ 111 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 112 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 113 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 114 } else { \ 115 *adev->vcn.dpg_sram_curr_addr++ = offset; \ 116 *adev->vcn.dpg_sram_curr_addr++ = value; \ 117 } \ 118 } while (0) 119 120 enum engine_status_constants { 121 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, 122 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0, 123 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002, 124 UVD_STATUS__UVD_BUSY = 0x00000004, 125 GB_ADDR_CONFIG_DEFAULT = 0x26010011, 126 UVD_STATUS__IDLE = 0x2, 127 UVD_STATUS__BUSY = 0x5, 128 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1, 129 UVD_STATUS__RBC_BUSY = 0x1, 130 UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0, 131 }; 132 133 enum internal_dpg_state { 134 VCN_DPG_STATE__UNPAUSE = 0, 135 VCN_DPG_STATE__PAUSE, 136 }; 137 138 struct dpg_pause_state { 139 enum internal_dpg_state fw_based; 140 enum internal_dpg_state jpeg; 141 }; 142 143 struct amdgpu_vcn_reg{ 144 unsigned data0; 145 unsigned data1; 146 unsigned cmd; 147 unsigned nop; 148 unsigned scratch9; 149 unsigned jpeg_pitch; 150 }; 151 152 struct amdgpu_vcn { 153 struct amdgpu_bo *vcpu_bo; 154 void *cpu_addr; 155 uint64_t gpu_addr; 156 unsigned fw_version; 157 void *saved_bo; 158 struct delayed_work idle_work; 159 const struct firmware *fw; /* VCN firmware */ 160 struct amdgpu_ring ring_dec; 161 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; 162 struct amdgpu_ring ring_jpeg; 163 struct amdgpu_irq_src irq; 164 unsigned num_enc_rings; 165 enum amd_powergating_state cur_state; 166 struct dpg_pause_state pause_state; 167 struct amdgpu_vcn_reg internal, external; 168 int (*pause_dpg_mode)(struct amdgpu_device *adev, 169 struct dpg_pause_state *new_state); 170 171 bool indirect_sram; 172 struct amdgpu_bo *dpg_sram_bo; 173 void *dpg_sram_cpu_addr; 174 uint64_t dpg_sram_gpu_addr; 175 uint32_t *dpg_sram_curr_addr; 176 }; 177 178 int amdgpu_vcn_sw_init(struct amdgpu_device *adev); 179 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); 180 int amdgpu_vcn_suspend(struct amdgpu_device *adev); 181 int amdgpu_vcn_resume(struct amdgpu_device *adev); 182 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); 183 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); 184 185 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); 186 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); 187 188 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); 189 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); 190 191 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring); 192 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout); 193 194 #endif 195