1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/debugfs.h> 31 #include <drm/drm_drv.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_pm.h" 35 #include "amdgpu_vcn.h" 36 #include "soc15d.h" 37 38 /* Firmware Names */ 39 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 40 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 41 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 42 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 43 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 44 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 45 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 46 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 47 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 48 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 49 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 50 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 51 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 52 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 53 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 54 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 55 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 56 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 57 58 MODULE_FIRMWARE(FIRMWARE_RAVEN); 59 MODULE_FIRMWARE(FIRMWARE_PICASSO); 60 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 61 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 62 MODULE_FIRMWARE(FIRMWARE_RENOIR); 63 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 64 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 65 MODULE_FIRMWARE(FIRMWARE_NAVI10); 66 MODULE_FIRMWARE(FIRMWARE_NAVI14); 67 MODULE_FIRMWARE(FIRMWARE_NAVI12); 68 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 69 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 70 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 71 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 72 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 73 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 74 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 75 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 76 77 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 78 79 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 80 { 81 unsigned long bo_size; 82 const char *fw_name; 83 const struct common_firmware_header *hdr; 84 unsigned char fw_check; 85 unsigned int fw_shared_size, log_offset; 86 int i, r; 87 88 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 89 mutex_init(&adev->vcn.vcn_pg_lock); 90 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 91 atomic_set(&adev->vcn.total_submission_cnt, 0); 92 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 93 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 94 95 switch (adev->ip_versions[UVD_HWIP][0]) { 96 case IP_VERSION(1, 0, 0): 97 case IP_VERSION(1, 0, 1): 98 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 99 fw_name = FIRMWARE_RAVEN2; 100 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 101 fw_name = FIRMWARE_PICASSO; 102 else 103 fw_name = FIRMWARE_RAVEN; 104 break; 105 case IP_VERSION(2, 5, 0): 106 fw_name = FIRMWARE_ARCTURUS; 107 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 108 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 109 adev->vcn.indirect_sram = true; 110 break; 111 case IP_VERSION(2, 2, 0): 112 if (adev->apu_flags & AMD_APU_IS_RENOIR) 113 fw_name = FIRMWARE_RENOIR; 114 else 115 fw_name = FIRMWARE_GREEN_SARDINE; 116 117 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 118 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 119 adev->vcn.indirect_sram = true; 120 break; 121 case IP_VERSION(2, 6, 0): 122 fw_name = FIRMWARE_ALDEBARAN; 123 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 124 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 125 adev->vcn.indirect_sram = true; 126 break; 127 case IP_VERSION(2, 0, 0): 128 fw_name = FIRMWARE_NAVI10; 129 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 130 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 131 adev->vcn.indirect_sram = true; 132 break; 133 case IP_VERSION(2, 0, 2): 134 if (adev->asic_type == CHIP_NAVI12) 135 fw_name = FIRMWARE_NAVI12; 136 else 137 fw_name = FIRMWARE_NAVI14; 138 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 139 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 140 adev->vcn.indirect_sram = true; 141 break; 142 case IP_VERSION(3, 0, 0): 143 case IP_VERSION(3, 0, 64): 144 case IP_VERSION(3, 0, 192): 145 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 146 fw_name = FIRMWARE_SIENNA_CICHLID; 147 else 148 fw_name = FIRMWARE_NAVY_FLOUNDER; 149 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 150 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 151 adev->vcn.indirect_sram = true; 152 break; 153 case IP_VERSION(3, 0, 2): 154 fw_name = FIRMWARE_VANGOGH; 155 break; 156 case IP_VERSION(3, 0, 16): 157 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 158 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 159 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 160 adev->vcn.indirect_sram = true; 161 break; 162 case IP_VERSION(3, 0, 33): 163 fw_name = FIRMWARE_BEIGE_GOBY; 164 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 165 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 166 adev->vcn.indirect_sram = true; 167 break; 168 case IP_VERSION(3, 1, 1): 169 fw_name = FIRMWARE_YELLOW_CARP; 170 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 171 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 172 adev->vcn.indirect_sram = true; 173 break; 174 case IP_VERSION(3, 1, 2): 175 fw_name = FIRMWARE_VCN_3_1_2; 176 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 177 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 178 adev->vcn.indirect_sram = true; 179 break; 180 case IP_VERSION(4, 0, 0): 181 fw_name = FIRMWARE_VCN4_0_0; 182 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 183 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 184 adev->vcn.indirect_sram = true; 185 break; 186 default: 187 return -EINVAL; 188 } 189 190 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 191 if (r) { 192 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 193 fw_name); 194 return r; 195 } 196 197 r = amdgpu_ucode_validate(adev->vcn.fw); 198 if (r) { 199 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 200 fw_name); 201 release_firmware(adev->vcn.fw); 202 adev->vcn.fw = NULL; 203 return r; 204 } 205 206 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 207 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 208 209 /* Bit 20-23, it is encode major and non-zero for new naming convention. 210 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 211 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 212 * is zero in old naming convention, this field is always zero so far. 213 * These four bits are used to tell which naming convention is present. 214 */ 215 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 216 if (fw_check) { 217 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 218 219 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 220 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 221 enc_major = fw_check; 222 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 223 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 224 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 225 enc_major, enc_minor, dec_ver, vep, fw_rev); 226 } else { 227 unsigned int version_major, version_minor, family_id; 228 229 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 230 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 231 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 232 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 233 version_major, version_minor, family_id); 234 } 235 236 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 237 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 238 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 239 240 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){ 241 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 242 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 243 } else { 244 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 245 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 246 } 247 248 bo_size += fw_shared_size; 249 250 if (amdgpu_vcnfw_log) 251 bo_size += AMDGPU_VCNFW_LOG_SIZE; 252 253 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 254 if (adev->vcn.harvest_config & (1 << i)) 255 continue; 256 257 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 258 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 259 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 260 if (r) { 261 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 262 return r; 263 } 264 265 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 266 bo_size - fw_shared_size; 267 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 268 bo_size - fw_shared_size; 269 270 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 271 272 if (amdgpu_vcnfw_log) { 273 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 274 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 275 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 276 } 277 278 if (adev->vcn.indirect_sram) { 279 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 280 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 281 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 282 if (r) { 283 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 284 return r; 285 } 286 } 287 } 288 289 return 0; 290 } 291 292 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 293 { 294 int i, j; 295 296 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 297 if (adev->vcn.harvest_config & (1 << j)) 298 continue; 299 300 if (adev->vcn.indirect_sram) { 301 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 302 &adev->vcn.inst[j].dpg_sram_gpu_addr, 303 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 304 } 305 kvfree(adev->vcn.inst[j].saved_bo); 306 307 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 308 &adev->vcn.inst[j].gpu_addr, 309 (void **)&adev->vcn.inst[j].cpu_addr); 310 311 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 312 313 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 314 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 315 } 316 317 release_firmware(adev->vcn.fw); 318 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 319 mutex_destroy(&adev->vcn.vcn_pg_lock); 320 321 return 0; 322 } 323 324 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 325 { 326 bool ret = false; 327 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 328 329 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 330 ret = true; 331 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) { 332 ret = true; 333 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 334 ret = true; 335 } 336 337 return ret; 338 } 339 340 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 341 { 342 unsigned size; 343 void *ptr; 344 int i, idx; 345 346 cancel_delayed_work_sync(&adev->vcn.idle_work); 347 348 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 349 if (adev->vcn.harvest_config & (1 << i)) 350 continue; 351 if (adev->vcn.inst[i].vcpu_bo == NULL) 352 return 0; 353 354 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 355 ptr = adev->vcn.inst[i].cpu_addr; 356 357 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 358 if (!adev->vcn.inst[i].saved_bo) 359 return -ENOMEM; 360 361 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 362 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 363 drm_dev_exit(idx); 364 } 365 } 366 return 0; 367 } 368 369 int amdgpu_vcn_resume(struct amdgpu_device *adev) 370 { 371 unsigned size; 372 void *ptr; 373 int i, idx; 374 375 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 376 if (adev->vcn.harvest_config & (1 << i)) 377 continue; 378 if (adev->vcn.inst[i].vcpu_bo == NULL) 379 return -EINVAL; 380 381 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 382 ptr = adev->vcn.inst[i].cpu_addr; 383 384 if (adev->vcn.inst[i].saved_bo != NULL) { 385 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 386 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 387 drm_dev_exit(idx); 388 } 389 kvfree(adev->vcn.inst[i].saved_bo); 390 adev->vcn.inst[i].saved_bo = NULL; 391 } else { 392 const struct common_firmware_header *hdr; 393 unsigned offset; 394 395 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 396 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 397 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 398 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 399 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 400 le32_to_cpu(hdr->ucode_size_bytes)); 401 drm_dev_exit(idx); 402 } 403 size -= le32_to_cpu(hdr->ucode_size_bytes); 404 ptr += le32_to_cpu(hdr->ucode_size_bytes); 405 } 406 memset_io(ptr, 0, size); 407 } 408 } 409 return 0; 410 } 411 412 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 413 { 414 struct amdgpu_device *adev = 415 container_of(work, struct amdgpu_device, vcn.idle_work.work); 416 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 417 unsigned int i, j; 418 int r = 0; 419 420 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 421 if (adev->vcn.harvest_config & (1 << j)) 422 continue; 423 424 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 425 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 426 } 427 428 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 429 struct dpg_pause_state new_state; 430 431 if (fence[j] || 432 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 433 new_state.fw_based = VCN_DPG_STATE__PAUSE; 434 else 435 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 436 437 adev->vcn.pause_dpg_mode(adev, j, &new_state); 438 } 439 440 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 441 fences += fence[j]; 442 } 443 444 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 445 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 446 AMD_PG_STATE_GATE); 447 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 448 false); 449 if (r) 450 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 451 } else { 452 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 453 } 454 } 455 456 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 457 { 458 struct amdgpu_device *adev = ring->adev; 459 int r = 0; 460 461 atomic_inc(&adev->vcn.total_submission_cnt); 462 463 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 464 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 465 true); 466 if (r) 467 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 468 } 469 470 mutex_lock(&adev->vcn.vcn_pg_lock); 471 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 472 AMD_PG_STATE_UNGATE); 473 474 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 475 struct dpg_pause_state new_state; 476 477 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 478 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 479 new_state.fw_based = VCN_DPG_STATE__PAUSE; 480 } else { 481 unsigned int fences = 0; 482 unsigned int i; 483 484 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 485 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 486 487 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 488 new_state.fw_based = VCN_DPG_STATE__PAUSE; 489 else 490 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 491 } 492 493 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 494 } 495 mutex_unlock(&adev->vcn.vcn_pg_lock); 496 } 497 498 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 499 { 500 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 501 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 502 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 503 504 atomic_dec(&ring->adev->vcn.total_submission_cnt); 505 506 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 507 } 508 509 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 510 { 511 struct amdgpu_device *adev = ring->adev; 512 uint32_t tmp = 0; 513 unsigned i; 514 int r; 515 516 /* VCN in SRIOV does not support direct register read/write */ 517 if (amdgpu_sriov_vf(adev)) 518 return 0; 519 520 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 521 r = amdgpu_ring_alloc(ring, 3); 522 if (r) 523 return r; 524 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 525 amdgpu_ring_write(ring, 0xDEADBEEF); 526 amdgpu_ring_commit(ring); 527 for (i = 0; i < adev->usec_timeout; i++) { 528 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 529 if (tmp == 0xDEADBEEF) 530 break; 531 udelay(1); 532 } 533 534 if (i >= adev->usec_timeout) 535 r = -ETIMEDOUT; 536 537 return r; 538 } 539 540 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 541 { 542 struct amdgpu_device *adev = ring->adev; 543 uint32_t rptr; 544 unsigned int i; 545 int r; 546 547 if (amdgpu_sriov_vf(adev)) 548 return 0; 549 550 r = amdgpu_ring_alloc(ring, 16); 551 if (r) 552 return r; 553 554 rptr = amdgpu_ring_get_rptr(ring); 555 556 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 557 amdgpu_ring_commit(ring); 558 559 for (i = 0; i < adev->usec_timeout; i++) { 560 if (amdgpu_ring_get_rptr(ring) != rptr) 561 break; 562 udelay(1); 563 } 564 565 if (i >= adev->usec_timeout) 566 r = -ETIMEDOUT; 567 568 return r; 569 } 570 571 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 572 struct amdgpu_ib *ib_msg, 573 struct dma_fence **fence) 574 { 575 struct amdgpu_device *adev = ring->adev; 576 struct dma_fence *f = NULL; 577 struct amdgpu_job *job; 578 struct amdgpu_ib *ib; 579 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 580 int i, r; 581 582 r = amdgpu_job_alloc_with_ib(adev, 64, 583 AMDGPU_IB_POOL_DIRECT, &job); 584 if (r) 585 goto err; 586 587 ib = &job->ibs[0]; 588 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 589 ib->ptr[1] = addr; 590 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 591 ib->ptr[3] = addr >> 32; 592 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 593 ib->ptr[5] = 0; 594 for (i = 6; i < 16; i += 2) { 595 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 596 ib->ptr[i+1] = 0; 597 } 598 ib->length_dw = 16; 599 600 r = amdgpu_job_submit_direct(job, ring, &f); 601 if (r) 602 goto err_free; 603 604 amdgpu_ib_free(adev, ib_msg, f); 605 606 if (fence) 607 *fence = dma_fence_get(f); 608 dma_fence_put(f); 609 610 return 0; 611 612 err_free: 613 amdgpu_job_free(job); 614 err: 615 amdgpu_ib_free(adev, ib_msg, f); 616 return r; 617 } 618 619 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 620 struct amdgpu_ib *ib) 621 { 622 struct amdgpu_device *adev = ring->adev; 623 uint32_t *msg; 624 int r, i; 625 626 memset(ib, 0, sizeof(*ib)); 627 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 628 AMDGPU_IB_POOL_DIRECT, 629 ib); 630 if (r) 631 return r; 632 633 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 634 msg[0] = cpu_to_le32(0x00000028); 635 msg[1] = cpu_to_le32(0x00000038); 636 msg[2] = cpu_to_le32(0x00000001); 637 msg[3] = cpu_to_le32(0x00000000); 638 msg[4] = cpu_to_le32(handle); 639 msg[5] = cpu_to_le32(0x00000000); 640 msg[6] = cpu_to_le32(0x00000001); 641 msg[7] = cpu_to_le32(0x00000028); 642 msg[8] = cpu_to_le32(0x00000010); 643 msg[9] = cpu_to_le32(0x00000000); 644 msg[10] = cpu_to_le32(0x00000007); 645 msg[11] = cpu_to_le32(0x00000000); 646 msg[12] = cpu_to_le32(0x00000780); 647 msg[13] = cpu_to_le32(0x00000440); 648 for (i = 14; i < 1024; ++i) 649 msg[i] = cpu_to_le32(0x0); 650 651 return 0; 652 } 653 654 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 655 struct amdgpu_ib *ib) 656 { 657 struct amdgpu_device *adev = ring->adev; 658 uint32_t *msg; 659 int r, i; 660 661 memset(ib, 0, sizeof(*ib)); 662 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 663 AMDGPU_IB_POOL_DIRECT, 664 ib); 665 if (r) 666 return r; 667 668 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 669 msg[0] = cpu_to_le32(0x00000028); 670 msg[1] = cpu_to_le32(0x00000018); 671 msg[2] = cpu_to_le32(0x00000000); 672 msg[3] = cpu_to_le32(0x00000002); 673 msg[4] = cpu_to_le32(handle); 674 msg[5] = cpu_to_le32(0x00000000); 675 for (i = 6; i < 1024; ++i) 676 msg[i] = cpu_to_le32(0x0); 677 678 return 0; 679 } 680 681 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 682 { 683 struct dma_fence *fence = NULL; 684 struct amdgpu_ib ib; 685 long r; 686 687 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 688 if (r) 689 goto error; 690 691 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 692 if (r) 693 goto error; 694 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 695 if (r) 696 goto error; 697 698 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 699 if (r) 700 goto error; 701 702 r = dma_fence_wait_timeout(fence, false, timeout); 703 if (r == 0) 704 r = -ETIMEDOUT; 705 else if (r > 0) 706 r = 0; 707 708 dma_fence_put(fence); 709 error: 710 return r; 711 } 712 713 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 714 struct amdgpu_ib *ib_msg, 715 struct dma_fence **fence) 716 { 717 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 718 const unsigned int ib_size_dw = 64; 719 struct amdgpu_device *adev = ring->adev; 720 struct dma_fence *f = NULL; 721 struct amdgpu_job *job; 722 struct amdgpu_ib *ib; 723 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 724 int i, r; 725 726 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 727 AMDGPU_IB_POOL_DIRECT, &job); 728 if (r) 729 goto err; 730 731 ib = &job->ibs[0]; 732 ib->length_dw = 0; 733 734 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 735 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 736 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 737 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 738 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 739 740 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 741 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 742 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 743 744 for (i = ib->length_dw; i < ib_size_dw; ++i) 745 ib->ptr[i] = 0x0; 746 747 r = amdgpu_job_submit_direct(job, ring, &f); 748 if (r) 749 goto err_free; 750 751 amdgpu_ib_free(adev, ib_msg, f); 752 753 if (fence) 754 *fence = dma_fence_get(f); 755 dma_fence_put(f); 756 757 return 0; 758 759 err_free: 760 amdgpu_job_free(job); 761 err: 762 amdgpu_ib_free(adev, ib_msg, f); 763 return r; 764 } 765 766 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 767 { 768 struct dma_fence *fence = NULL; 769 struct amdgpu_ib ib; 770 long r; 771 772 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 773 if (r) 774 goto error; 775 776 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 777 if (r) 778 goto error; 779 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 780 if (r) 781 goto error; 782 783 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 784 if (r) 785 goto error; 786 787 r = dma_fence_wait_timeout(fence, false, timeout); 788 if (r == 0) 789 r = -ETIMEDOUT; 790 else if (r > 0) 791 r = 0; 792 793 dma_fence_put(fence); 794 error: 795 return r; 796 } 797 798 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 799 { 800 struct amdgpu_device *adev = ring->adev; 801 uint32_t rptr; 802 unsigned i; 803 int r; 804 805 if (amdgpu_sriov_vf(adev)) 806 return 0; 807 808 r = amdgpu_ring_alloc(ring, 16); 809 if (r) 810 return r; 811 812 rptr = amdgpu_ring_get_rptr(ring); 813 814 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 815 amdgpu_ring_commit(ring); 816 817 for (i = 0; i < adev->usec_timeout; i++) { 818 if (amdgpu_ring_get_rptr(ring) != rptr) 819 break; 820 udelay(1); 821 } 822 823 if (i >= adev->usec_timeout) 824 r = -ETIMEDOUT; 825 826 return r; 827 } 828 829 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 830 struct amdgpu_ib *ib_msg, 831 struct dma_fence **fence) 832 { 833 const unsigned ib_size_dw = 16; 834 struct amdgpu_job *job; 835 struct amdgpu_ib *ib; 836 struct dma_fence *f = NULL; 837 uint64_t addr; 838 int i, r; 839 840 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 841 AMDGPU_IB_POOL_DIRECT, &job); 842 if (r) 843 return r; 844 845 ib = &job->ibs[0]; 846 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 847 848 ib->length_dw = 0; 849 ib->ptr[ib->length_dw++] = 0x00000018; 850 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 851 ib->ptr[ib->length_dw++] = handle; 852 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 853 ib->ptr[ib->length_dw++] = addr; 854 ib->ptr[ib->length_dw++] = 0x0000000b; 855 856 ib->ptr[ib->length_dw++] = 0x00000014; 857 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 858 ib->ptr[ib->length_dw++] = 0x0000001c; 859 ib->ptr[ib->length_dw++] = 0x00000000; 860 ib->ptr[ib->length_dw++] = 0x00000000; 861 862 ib->ptr[ib->length_dw++] = 0x00000008; 863 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 864 865 for (i = ib->length_dw; i < ib_size_dw; ++i) 866 ib->ptr[i] = 0x0; 867 868 r = amdgpu_job_submit_direct(job, ring, &f); 869 if (r) 870 goto err; 871 872 if (fence) 873 *fence = dma_fence_get(f); 874 dma_fence_put(f); 875 876 return 0; 877 878 err: 879 amdgpu_job_free(job); 880 return r; 881 } 882 883 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 884 struct amdgpu_ib *ib_msg, 885 struct dma_fence **fence) 886 { 887 const unsigned ib_size_dw = 16; 888 struct amdgpu_job *job; 889 struct amdgpu_ib *ib; 890 struct dma_fence *f = NULL; 891 uint64_t addr; 892 int i, r; 893 894 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 895 AMDGPU_IB_POOL_DIRECT, &job); 896 if (r) 897 return r; 898 899 ib = &job->ibs[0]; 900 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 901 902 ib->length_dw = 0; 903 ib->ptr[ib->length_dw++] = 0x00000018; 904 ib->ptr[ib->length_dw++] = 0x00000001; 905 ib->ptr[ib->length_dw++] = handle; 906 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 907 ib->ptr[ib->length_dw++] = addr; 908 ib->ptr[ib->length_dw++] = 0x0000000b; 909 910 ib->ptr[ib->length_dw++] = 0x00000014; 911 ib->ptr[ib->length_dw++] = 0x00000002; 912 ib->ptr[ib->length_dw++] = 0x0000001c; 913 ib->ptr[ib->length_dw++] = 0x00000000; 914 ib->ptr[ib->length_dw++] = 0x00000000; 915 916 ib->ptr[ib->length_dw++] = 0x00000008; 917 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 918 919 for (i = ib->length_dw; i < ib_size_dw; ++i) 920 ib->ptr[i] = 0x0; 921 922 r = amdgpu_job_submit_direct(job, ring, &f); 923 if (r) 924 goto err; 925 926 if (fence) 927 *fence = dma_fence_get(f); 928 dma_fence_put(f); 929 930 return 0; 931 932 err: 933 amdgpu_job_free(job); 934 return r; 935 } 936 937 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 938 { 939 struct amdgpu_device *adev = ring->adev; 940 struct dma_fence *fence = NULL; 941 struct amdgpu_ib ib; 942 long r; 943 944 memset(&ib, 0, sizeof(ib)); 945 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 946 AMDGPU_IB_POOL_DIRECT, 947 &ib); 948 if (r) 949 return r; 950 951 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 952 if (r) 953 goto error; 954 955 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 956 if (r) 957 goto error; 958 959 r = dma_fence_wait_timeout(fence, false, timeout); 960 if (r == 0) 961 r = -ETIMEDOUT; 962 else if (r > 0) 963 r = 0; 964 965 error: 966 amdgpu_ib_free(adev, &ib, fence); 967 dma_fence_put(fence); 968 969 return r; 970 } 971 972 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 973 { 974 switch(ring) { 975 case 0: 976 return AMDGPU_RING_PRIO_0; 977 case 1: 978 return AMDGPU_RING_PRIO_1; 979 case 2: 980 return AMDGPU_RING_PRIO_2; 981 default: 982 return AMDGPU_RING_PRIO_0; 983 } 984 } 985 986 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 987 { 988 int i; 989 unsigned int idx; 990 991 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 992 const struct common_firmware_header *hdr; 993 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 994 995 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 996 if (adev->vcn.harvest_config & (1 << i)) 997 continue; 998 /* currently only support 2 FW instances */ 999 if (i >= 2) { 1000 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1001 break; 1002 } 1003 idx = AMDGPU_UCODE_ID_VCN + i; 1004 adev->firmware.ucode[idx].ucode_id = idx; 1005 adev->firmware.ucode[idx].fw = adev->vcn.fw; 1006 adev->firmware.fw_size += 1007 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1008 } 1009 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 1010 } 1011 } 1012 1013 /* 1014 * debugfs for mapping vcn firmware log buffer. 1015 */ 1016 #if defined(CONFIG_DEBUG_FS) 1017 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1018 size_t size, loff_t *pos) 1019 { 1020 struct amdgpu_vcn_inst *vcn; 1021 void *log_buf; 1022 volatile struct amdgpu_vcn_fwlog *plog; 1023 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1024 unsigned int read_num[2] = {0}; 1025 1026 vcn = file_inode(f)->i_private; 1027 if (!vcn) 1028 return -ENODEV; 1029 1030 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1031 return -EFAULT; 1032 1033 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1034 1035 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1036 read_pos = plog->rptr; 1037 write_pos = plog->wptr; 1038 1039 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1040 return -EFAULT; 1041 1042 if (!size || (read_pos == write_pos)) 1043 return 0; 1044 1045 if (write_pos > read_pos) { 1046 available = write_pos - read_pos; 1047 read_num[0] = min(size, (size_t)available); 1048 } else { 1049 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1050 available = read_num[0] + write_pos - plog->header_size; 1051 if (size > available) 1052 read_num[1] = write_pos - plog->header_size; 1053 else if (size > read_num[0]) 1054 read_num[1] = size - read_num[0]; 1055 else 1056 read_num[0] = size; 1057 } 1058 1059 for (i = 0; i < 2; i++) { 1060 if (read_num[i]) { 1061 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1062 read_pos = plog->header_size; 1063 if (read_num[i] == copy_to_user((buf + read_bytes), 1064 (log_buf + read_pos), read_num[i])) 1065 return -EFAULT; 1066 1067 read_bytes += read_num[i]; 1068 read_pos += read_num[i]; 1069 } 1070 } 1071 1072 plog->rptr = read_pos; 1073 *pos += read_bytes; 1074 return read_bytes; 1075 } 1076 1077 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1078 .owner = THIS_MODULE, 1079 .read = amdgpu_debugfs_vcn_fwlog_read, 1080 .llseek = default_llseek 1081 }; 1082 #endif 1083 1084 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1085 struct amdgpu_vcn_inst *vcn) 1086 { 1087 #if defined(CONFIG_DEBUG_FS) 1088 struct drm_minor *minor = adev_to_drm(adev)->primary; 1089 struct dentry *root = minor->debugfs_root; 1090 char name[32]; 1091 1092 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1093 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn, 1094 &amdgpu_debugfs_vcnfwlog_fops, 1095 AMDGPU_VCNFW_LOG_SIZE); 1096 #endif 1097 } 1098 1099 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1100 { 1101 #if defined(CONFIG_DEBUG_FS) 1102 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1103 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1104 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1105 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1106 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1107 + vcn->fw_shared.log_offset; 1108 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1109 fw_log->is_enabled = 1; 1110 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1111 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1112 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1113 1114 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1115 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1116 log_buf->rptr = log_buf->header_size; 1117 log_buf->wptr = log_buf->header_size; 1118 log_buf->wrapped = 0; 1119 #endif 1120 } 1121