1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 31 #include "amdgpu.h" 32 #include "amdgpu_pm.h" 33 #include "amdgpu_vcn.h" 34 #include "soc15d.h" 35 36 /* Firmware Names */ 37 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 38 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 39 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 40 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 41 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 42 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 43 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 44 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 45 46 MODULE_FIRMWARE(FIRMWARE_RAVEN); 47 MODULE_FIRMWARE(FIRMWARE_PICASSO); 48 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 49 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 50 MODULE_FIRMWARE(FIRMWARE_RENOIR); 51 MODULE_FIRMWARE(FIRMWARE_NAVI10); 52 MODULE_FIRMWARE(FIRMWARE_NAVI14); 53 MODULE_FIRMWARE(FIRMWARE_NAVI12); 54 55 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 56 57 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 58 { 59 unsigned long bo_size; 60 const char *fw_name; 61 const struct common_firmware_header *hdr; 62 unsigned char fw_check; 63 int i, r; 64 65 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 66 67 switch (adev->asic_type) { 68 case CHIP_RAVEN: 69 if (adev->rev_id >= 8) 70 fw_name = FIRMWARE_RAVEN2; 71 else if (adev->pdev->device == 0x15d8) 72 fw_name = FIRMWARE_PICASSO; 73 else 74 fw_name = FIRMWARE_RAVEN; 75 break; 76 case CHIP_ARCTURUS: 77 fw_name = FIRMWARE_ARCTURUS; 78 break; 79 case CHIP_RENOIR: 80 fw_name = FIRMWARE_RENOIR; 81 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 82 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 83 adev->vcn.indirect_sram = true; 84 break; 85 case CHIP_NAVI10: 86 fw_name = FIRMWARE_NAVI10; 87 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 88 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 89 adev->vcn.indirect_sram = true; 90 break; 91 case CHIP_NAVI14: 92 fw_name = FIRMWARE_NAVI14; 93 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 94 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 95 adev->vcn.indirect_sram = true; 96 break; 97 case CHIP_NAVI12: 98 fw_name = FIRMWARE_NAVI12; 99 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 100 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 101 adev->vcn.indirect_sram = true; 102 break; 103 default: 104 return -EINVAL; 105 } 106 107 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 108 if (r) { 109 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 110 fw_name); 111 return r; 112 } 113 114 r = amdgpu_ucode_validate(adev->vcn.fw); 115 if (r) { 116 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 117 fw_name); 118 release_firmware(adev->vcn.fw); 119 adev->vcn.fw = NULL; 120 return r; 121 } 122 123 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 124 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 125 126 /* Bit 20-23, it is encode major and non-zero for new naming convention. 127 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 128 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 129 * is zero in old naming convention, this field is always zero so far. 130 * These four bits are used to tell which naming convention is present. 131 */ 132 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 133 if (fw_check) { 134 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 135 136 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 137 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 138 enc_major = fw_check; 139 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 140 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 141 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n", 142 enc_major, enc_minor, dec_ver, vep, fw_rev); 143 } else { 144 unsigned int version_major, version_minor, family_id; 145 146 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 147 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 148 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 149 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n", 150 version_major, version_minor, family_id); 151 } 152 153 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 154 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 155 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 156 157 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 158 if (adev->vcn.harvest_config & (1 << i)) 159 continue; 160 161 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 162 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 163 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 164 if (r) { 165 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 166 return r; 167 } 168 } 169 170 if (adev->vcn.indirect_sram) { 171 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 172 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.dpg_sram_bo, 173 &adev->vcn.dpg_sram_gpu_addr, &adev->vcn.dpg_sram_cpu_addr); 174 if (r) { 175 dev_err(adev->dev, "(%d) failed to allocate DPG bo\n", r); 176 return r; 177 } 178 } 179 180 return 0; 181 } 182 183 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 184 { 185 int i, j; 186 187 cancel_delayed_work_sync(&adev->vcn.idle_work); 188 189 if (adev->vcn.indirect_sram) { 190 amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo, 191 &adev->vcn.dpg_sram_gpu_addr, 192 (void **)&adev->vcn.dpg_sram_cpu_addr); 193 } 194 195 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 196 if (adev->vcn.harvest_config & (1 << j)) 197 continue; 198 kvfree(adev->vcn.inst[j].saved_bo); 199 200 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 201 &adev->vcn.inst[j].gpu_addr, 202 (void **)&adev->vcn.inst[j].cpu_addr); 203 204 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 205 206 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 207 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 208 } 209 210 release_firmware(adev->vcn.fw); 211 212 return 0; 213 } 214 215 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 216 { 217 unsigned size; 218 void *ptr; 219 int i; 220 221 cancel_delayed_work_sync(&adev->vcn.idle_work); 222 223 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 224 if (adev->vcn.harvest_config & (1 << i)) 225 continue; 226 if (adev->vcn.inst[i].vcpu_bo == NULL) 227 return 0; 228 229 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 230 ptr = adev->vcn.inst[i].cpu_addr; 231 232 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 233 if (!adev->vcn.inst[i].saved_bo) 234 return -ENOMEM; 235 236 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 237 } 238 return 0; 239 } 240 241 int amdgpu_vcn_resume(struct amdgpu_device *adev) 242 { 243 unsigned size; 244 void *ptr; 245 int i; 246 247 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 248 if (adev->vcn.harvest_config & (1 << i)) 249 continue; 250 if (adev->vcn.inst[i].vcpu_bo == NULL) 251 return -EINVAL; 252 253 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 254 ptr = adev->vcn.inst[i].cpu_addr; 255 256 if (adev->vcn.inst[i].saved_bo != NULL) { 257 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 258 kvfree(adev->vcn.inst[i].saved_bo); 259 adev->vcn.inst[i].saved_bo = NULL; 260 } else { 261 const struct common_firmware_header *hdr; 262 unsigned offset; 263 264 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 265 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 266 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 267 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 268 le32_to_cpu(hdr->ucode_size_bytes)); 269 size -= le32_to_cpu(hdr->ucode_size_bytes); 270 ptr += le32_to_cpu(hdr->ucode_size_bytes); 271 } 272 memset_io(ptr, 0, size); 273 } 274 } 275 return 0; 276 } 277 278 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 279 { 280 struct amdgpu_device *adev = 281 container_of(work, struct amdgpu_device, vcn.idle_work.work); 282 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 283 unsigned int i, j; 284 285 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 286 if (adev->vcn.harvest_config & (1 << j)) 287 continue; 288 289 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 290 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 291 } 292 293 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 294 struct dpg_pause_state new_state; 295 296 if (fence[j]) 297 new_state.fw_based = VCN_DPG_STATE__PAUSE; 298 else 299 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 300 301 adev->vcn.pause_dpg_mode(adev, &new_state); 302 } 303 304 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 305 fences += fence[j]; 306 } 307 308 if (fences == 0) { 309 amdgpu_gfx_off_ctrl(adev, true); 310 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 311 AMD_PG_STATE_GATE); 312 } else { 313 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 314 } 315 } 316 317 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 318 { 319 struct amdgpu_device *adev = ring->adev; 320 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 321 322 if (set_clocks) { 323 amdgpu_gfx_off_ctrl(adev, false); 324 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 325 AMD_PG_STATE_UNGATE); 326 } 327 328 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 329 struct dpg_pause_state new_state; 330 unsigned int fences = 0; 331 unsigned int i; 332 333 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 334 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 335 } 336 if (fences) 337 new_state.fw_based = VCN_DPG_STATE__PAUSE; 338 else 339 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 340 341 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 342 new_state.fw_based = VCN_DPG_STATE__PAUSE; 343 344 adev->vcn.pause_dpg_mode(adev, &new_state); 345 } 346 } 347 348 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 349 { 350 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 351 } 352 353 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 354 { 355 struct amdgpu_device *adev = ring->adev; 356 uint32_t tmp = 0; 357 unsigned i; 358 int r; 359 360 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 361 r = amdgpu_ring_alloc(ring, 3); 362 if (r) 363 return r; 364 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 365 amdgpu_ring_write(ring, 0xDEADBEEF); 366 amdgpu_ring_commit(ring); 367 for (i = 0; i < adev->usec_timeout; i++) { 368 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 369 if (tmp == 0xDEADBEEF) 370 break; 371 udelay(1); 372 } 373 374 if (i >= adev->usec_timeout) 375 r = -ETIMEDOUT; 376 377 return r; 378 } 379 380 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 381 struct amdgpu_bo *bo, 382 struct dma_fence **fence) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 struct dma_fence *f = NULL; 386 struct amdgpu_job *job; 387 struct amdgpu_ib *ib; 388 uint64_t addr; 389 int i, r; 390 391 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 392 if (r) 393 goto err; 394 395 ib = &job->ibs[0]; 396 addr = amdgpu_bo_gpu_offset(bo); 397 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 398 ib->ptr[1] = addr; 399 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 400 ib->ptr[3] = addr >> 32; 401 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 402 ib->ptr[5] = 0; 403 for (i = 6; i < 16; i += 2) { 404 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 405 ib->ptr[i+1] = 0; 406 } 407 ib->length_dw = 16; 408 409 r = amdgpu_job_submit_direct(job, ring, &f); 410 if (r) 411 goto err_free; 412 413 amdgpu_bo_fence(bo, f, false); 414 amdgpu_bo_unreserve(bo); 415 amdgpu_bo_unref(&bo); 416 417 if (fence) 418 *fence = dma_fence_get(f); 419 dma_fence_put(f); 420 421 return 0; 422 423 err_free: 424 amdgpu_job_free(job); 425 426 err: 427 amdgpu_bo_unreserve(bo); 428 amdgpu_bo_unref(&bo); 429 return r; 430 } 431 432 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 433 struct dma_fence **fence) 434 { 435 struct amdgpu_device *adev = ring->adev; 436 struct amdgpu_bo *bo = NULL; 437 uint32_t *msg; 438 int r, i; 439 440 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 441 AMDGPU_GEM_DOMAIN_VRAM, 442 &bo, NULL, (void **)&msg); 443 if (r) 444 return r; 445 446 msg[0] = cpu_to_le32(0x00000028); 447 msg[1] = cpu_to_le32(0x00000038); 448 msg[2] = cpu_to_le32(0x00000001); 449 msg[3] = cpu_to_le32(0x00000000); 450 msg[4] = cpu_to_le32(handle); 451 msg[5] = cpu_to_le32(0x00000000); 452 msg[6] = cpu_to_le32(0x00000001); 453 msg[7] = cpu_to_le32(0x00000028); 454 msg[8] = cpu_to_le32(0x00000010); 455 msg[9] = cpu_to_le32(0x00000000); 456 msg[10] = cpu_to_le32(0x00000007); 457 msg[11] = cpu_to_le32(0x00000000); 458 msg[12] = cpu_to_le32(0x00000780); 459 msg[13] = cpu_to_le32(0x00000440); 460 for (i = 14; i < 1024; ++i) 461 msg[i] = cpu_to_le32(0x0); 462 463 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 464 } 465 466 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 467 struct dma_fence **fence) 468 { 469 struct amdgpu_device *adev = ring->adev; 470 struct amdgpu_bo *bo = NULL; 471 uint32_t *msg; 472 int r, i; 473 474 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 475 AMDGPU_GEM_DOMAIN_VRAM, 476 &bo, NULL, (void **)&msg); 477 if (r) 478 return r; 479 480 msg[0] = cpu_to_le32(0x00000028); 481 msg[1] = cpu_to_le32(0x00000018); 482 msg[2] = cpu_to_le32(0x00000000); 483 msg[3] = cpu_to_le32(0x00000002); 484 msg[4] = cpu_to_le32(handle); 485 msg[5] = cpu_to_le32(0x00000000); 486 for (i = 6; i < 1024; ++i) 487 msg[i] = cpu_to_le32(0x0); 488 489 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 490 } 491 492 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 493 { 494 struct dma_fence *fence; 495 long r; 496 497 r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL); 498 if (r) 499 goto error; 500 501 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence); 502 if (r) 503 goto error; 504 505 r = dma_fence_wait_timeout(fence, false, timeout); 506 if (r == 0) 507 r = -ETIMEDOUT; 508 else if (r > 0) 509 r = 0; 510 511 dma_fence_put(fence); 512 error: 513 return r; 514 } 515 516 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 517 { 518 struct amdgpu_device *adev = ring->adev; 519 uint32_t rptr; 520 unsigned i; 521 int r; 522 523 r = amdgpu_ring_alloc(ring, 16); 524 if (r) 525 return r; 526 527 rptr = amdgpu_ring_get_rptr(ring); 528 529 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 530 amdgpu_ring_commit(ring); 531 532 for (i = 0; i < adev->usec_timeout; i++) { 533 if (amdgpu_ring_get_rptr(ring) != rptr) 534 break; 535 udelay(1); 536 } 537 538 if (i >= adev->usec_timeout) 539 r = -ETIMEDOUT; 540 541 return r; 542 } 543 544 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 545 struct amdgpu_bo *bo, 546 struct dma_fence **fence) 547 { 548 const unsigned ib_size_dw = 16; 549 struct amdgpu_job *job; 550 struct amdgpu_ib *ib; 551 struct dma_fence *f = NULL; 552 uint64_t addr; 553 int i, r; 554 555 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 556 if (r) 557 return r; 558 559 ib = &job->ibs[0]; 560 addr = amdgpu_bo_gpu_offset(bo); 561 562 ib->length_dw = 0; 563 ib->ptr[ib->length_dw++] = 0x00000018; 564 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 565 ib->ptr[ib->length_dw++] = handle; 566 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 567 ib->ptr[ib->length_dw++] = addr; 568 ib->ptr[ib->length_dw++] = 0x0000000b; 569 570 ib->ptr[ib->length_dw++] = 0x00000014; 571 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 572 ib->ptr[ib->length_dw++] = 0x0000001c; 573 ib->ptr[ib->length_dw++] = 0x00000000; 574 ib->ptr[ib->length_dw++] = 0x00000000; 575 576 ib->ptr[ib->length_dw++] = 0x00000008; 577 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 578 579 for (i = ib->length_dw; i < ib_size_dw; ++i) 580 ib->ptr[i] = 0x0; 581 582 r = amdgpu_job_submit_direct(job, ring, &f); 583 if (r) 584 goto err; 585 586 if (fence) 587 *fence = dma_fence_get(f); 588 dma_fence_put(f); 589 590 return 0; 591 592 err: 593 amdgpu_job_free(job); 594 return r; 595 } 596 597 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 598 struct amdgpu_bo *bo, 599 struct dma_fence **fence) 600 { 601 const unsigned ib_size_dw = 16; 602 struct amdgpu_job *job; 603 struct amdgpu_ib *ib; 604 struct dma_fence *f = NULL; 605 uint64_t addr; 606 int i, r; 607 608 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 609 if (r) 610 return r; 611 612 ib = &job->ibs[0]; 613 addr = amdgpu_bo_gpu_offset(bo); 614 615 ib->length_dw = 0; 616 ib->ptr[ib->length_dw++] = 0x00000018; 617 ib->ptr[ib->length_dw++] = 0x00000001; 618 ib->ptr[ib->length_dw++] = handle; 619 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 620 ib->ptr[ib->length_dw++] = addr; 621 ib->ptr[ib->length_dw++] = 0x0000000b; 622 623 ib->ptr[ib->length_dw++] = 0x00000014; 624 ib->ptr[ib->length_dw++] = 0x00000002; 625 ib->ptr[ib->length_dw++] = 0x0000001c; 626 ib->ptr[ib->length_dw++] = 0x00000000; 627 ib->ptr[ib->length_dw++] = 0x00000000; 628 629 ib->ptr[ib->length_dw++] = 0x00000008; 630 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 631 632 for (i = ib->length_dw; i < ib_size_dw; ++i) 633 ib->ptr[i] = 0x0; 634 635 r = amdgpu_job_submit_direct(job, ring, &f); 636 if (r) 637 goto err; 638 639 if (fence) 640 *fence = dma_fence_get(f); 641 dma_fence_put(f); 642 643 return 0; 644 645 err: 646 amdgpu_job_free(job); 647 return r; 648 } 649 650 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 651 { 652 struct dma_fence *fence = NULL; 653 struct amdgpu_bo *bo = NULL; 654 long r; 655 656 r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE, 657 AMDGPU_GEM_DOMAIN_VRAM, 658 &bo, NULL, NULL); 659 if (r) 660 return r; 661 662 r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL); 663 if (r) 664 goto error; 665 666 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence); 667 if (r) 668 goto error; 669 670 r = dma_fence_wait_timeout(fence, false, timeout); 671 if (r == 0) 672 r = -ETIMEDOUT; 673 else if (r > 0) 674 r = 0; 675 676 error: 677 dma_fence_put(fence); 678 amdgpu_bo_unreserve(bo); 679 amdgpu_bo_unref(&bo); 680 return r; 681 } 682