1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 31 #include <drm/drm.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_pm.h" 35 #include "amdgpu_vcn.h" 36 #include "soc15d.h" 37 #include "soc15_common.h" 38 39 #include "vcn/vcn_1_0_offset.h" 40 #include "vcn/vcn_1_0_sh_mask.h" 41 42 /* 1 second timeout */ 43 #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) 44 45 /* Firmware Names */ 46 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 47 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 48 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 49 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 50 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 51 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 52 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 53 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 54 55 MODULE_FIRMWARE(FIRMWARE_RAVEN); 56 MODULE_FIRMWARE(FIRMWARE_PICASSO); 57 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 59 MODULE_FIRMWARE(FIRMWARE_RENOIR); 60 MODULE_FIRMWARE(FIRMWARE_NAVI10); 61 MODULE_FIRMWARE(FIRMWARE_NAVI14); 62 MODULE_FIRMWARE(FIRMWARE_NAVI12); 63 64 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 65 66 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 67 { 68 unsigned long bo_size; 69 const char *fw_name; 70 const struct common_firmware_header *hdr; 71 unsigned char fw_check; 72 int i, r; 73 74 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 75 76 switch (adev->asic_type) { 77 case CHIP_RAVEN: 78 if (adev->rev_id >= 8) 79 fw_name = FIRMWARE_RAVEN2; 80 else if (adev->pdev->device == 0x15d8) 81 fw_name = FIRMWARE_PICASSO; 82 else 83 fw_name = FIRMWARE_RAVEN; 84 break; 85 case CHIP_ARCTURUS: 86 fw_name = FIRMWARE_ARCTURUS; 87 break; 88 case CHIP_RENOIR: 89 fw_name = FIRMWARE_RENOIR; 90 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 91 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 92 adev->vcn.indirect_sram = true; 93 break; 94 case CHIP_NAVI10: 95 fw_name = FIRMWARE_NAVI10; 96 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 97 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 98 adev->vcn.indirect_sram = true; 99 break; 100 case CHIP_NAVI14: 101 fw_name = FIRMWARE_NAVI14; 102 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 103 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 104 adev->vcn.indirect_sram = true; 105 break; 106 case CHIP_NAVI12: 107 fw_name = FIRMWARE_NAVI12; 108 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 109 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 110 adev->vcn.indirect_sram = true; 111 break; 112 default: 113 return -EINVAL; 114 } 115 116 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 117 if (r) { 118 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 119 fw_name); 120 return r; 121 } 122 123 r = amdgpu_ucode_validate(adev->vcn.fw); 124 if (r) { 125 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 126 fw_name); 127 release_firmware(adev->vcn.fw); 128 adev->vcn.fw = NULL; 129 return r; 130 } 131 132 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 133 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 134 135 /* Bit 20-23, it is encode major and non-zero for new naming convention. 136 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 137 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 138 * is zero in old naming convention, this field is always zero so far. 139 * These four bits are used to tell which naming convention is present. 140 */ 141 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 142 if (fw_check) { 143 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 144 145 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 146 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 147 enc_major = fw_check; 148 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 149 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 150 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n", 151 enc_major, enc_minor, dec_ver, vep, fw_rev); 152 } else { 153 unsigned int version_major, version_minor, family_id; 154 155 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 156 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 157 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 158 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n", 159 version_major, version_minor, family_id); 160 } 161 162 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 163 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 164 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 165 166 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 167 if (adev->vcn.harvest_config & (1 << i)) 168 continue; 169 170 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 171 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 172 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 173 if (r) { 174 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 175 return r; 176 } 177 } 178 179 if (adev->vcn.indirect_sram) { 180 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 181 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.dpg_sram_bo, 182 &adev->vcn.dpg_sram_gpu_addr, &adev->vcn.dpg_sram_cpu_addr); 183 if (r) { 184 dev_err(adev->dev, "(%d) failed to allocate DPG bo\n", r); 185 return r; 186 } 187 } 188 189 return 0; 190 } 191 192 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 193 { 194 int i, j; 195 196 cancel_delayed_work_sync(&adev->vcn.idle_work); 197 198 if (adev->vcn.indirect_sram) { 199 amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo, 200 &adev->vcn.dpg_sram_gpu_addr, 201 (void **)&adev->vcn.dpg_sram_cpu_addr); 202 } 203 204 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 205 if (adev->vcn.harvest_config & (1 << j)) 206 continue; 207 kvfree(adev->vcn.inst[j].saved_bo); 208 209 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 210 &adev->vcn.inst[j].gpu_addr, 211 (void **)&adev->vcn.inst[j].cpu_addr); 212 213 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 214 215 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 216 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 217 218 amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg); 219 } 220 221 release_firmware(adev->vcn.fw); 222 223 return 0; 224 } 225 226 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 227 { 228 unsigned size; 229 void *ptr; 230 int i; 231 232 cancel_delayed_work_sync(&adev->vcn.idle_work); 233 234 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 235 if (adev->vcn.harvest_config & (1 << i)) 236 continue; 237 if (adev->vcn.inst[i].vcpu_bo == NULL) 238 return 0; 239 240 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 241 ptr = adev->vcn.inst[i].cpu_addr; 242 243 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 244 if (!adev->vcn.inst[i].saved_bo) 245 return -ENOMEM; 246 247 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 248 } 249 return 0; 250 } 251 252 int amdgpu_vcn_resume(struct amdgpu_device *adev) 253 { 254 unsigned size; 255 void *ptr; 256 int i; 257 258 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 259 if (adev->vcn.harvest_config & (1 << i)) 260 continue; 261 if (adev->vcn.inst[i].vcpu_bo == NULL) 262 return -EINVAL; 263 264 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 265 ptr = adev->vcn.inst[i].cpu_addr; 266 267 if (adev->vcn.inst[i].saved_bo != NULL) { 268 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 269 kvfree(adev->vcn.inst[i].saved_bo); 270 adev->vcn.inst[i].saved_bo = NULL; 271 } else { 272 const struct common_firmware_header *hdr; 273 unsigned offset; 274 275 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 276 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 277 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 278 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 279 le32_to_cpu(hdr->ucode_size_bytes)); 280 size -= le32_to_cpu(hdr->ucode_size_bytes); 281 ptr += le32_to_cpu(hdr->ucode_size_bytes); 282 } 283 memset_io(ptr, 0, size); 284 } 285 } 286 return 0; 287 } 288 289 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 290 { 291 struct amdgpu_device *adev = 292 container_of(work, struct amdgpu_device, vcn.idle_work.work); 293 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 294 unsigned int i, j; 295 296 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 297 if (adev->vcn.harvest_config & (1 << j)) 298 continue; 299 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 300 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 301 } 302 303 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 304 struct dpg_pause_state new_state; 305 306 if (fence[j]) 307 new_state.fw_based = VCN_DPG_STATE__PAUSE; 308 else 309 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 310 311 if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg)) 312 new_state.jpeg = VCN_DPG_STATE__PAUSE; 313 else 314 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 315 316 adev->vcn.pause_dpg_mode(adev, &new_state); 317 } 318 319 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg); 320 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 321 fences += fence[j]; 322 } 323 324 if (fences == 0) { 325 amdgpu_gfx_off_ctrl(adev, true); 326 if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled) 327 amdgpu_dpm_enable_uvd(adev, false); 328 else 329 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 330 AMD_PG_STATE_GATE); 331 } else { 332 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 333 } 334 } 335 336 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 337 { 338 struct amdgpu_device *adev = ring->adev; 339 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 340 341 if (set_clocks) { 342 amdgpu_gfx_off_ctrl(adev, false); 343 if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled) 344 amdgpu_dpm_enable_uvd(adev, true); 345 else 346 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 347 AMD_PG_STATE_UNGATE); 348 } 349 350 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 351 struct dpg_pause_state new_state; 352 unsigned int fences = 0; 353 unsigned int i; 354 355 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 356 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 357 } 358 if (fences) 359 new_state.fw_based = VCN_DPG_STATE__PAUSE; 360 else 361 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 362 363 if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg)) 364 new_state.jpeg = VCN_DPG_STATE__PAUSE; 365 else 366 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 367 368 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 369 new_state.fw_based = VCN_DPG_STATE__PAUSE; 370 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 371 new_state.jpeg = VCN_DPG_STATE__PAUSE; 372 373 adev->vcn.pause_dpg_mode(adev, &new_state); 374 } 375 } 376 377 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 378 { 379 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 380 } 381 382 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 uint32_t tmp = 0; 386 unsigned i; 387 int r; 388 389 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 390 r = amdgpu_ring_alloc(ring, 3); 391 if (r) 392 return r; 393 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 394 amdgpu_ring_write(ring, 0xDEADBEEF); 395 amdgpu_ring_commit(ring); 396 for (i = 0; i < adev->usec_timeout; i++) { 397 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 398 if (tmp == 0xDEADBEEF) 399 break; 400 udelay(1); 401 } 402 403 if (i >= adev->usec_timeout) 404 r = -ETIMEDOUT; 405 406 return r; 407 } 408 409 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 410 struct amdgpu_bo *bo, 411 struct dma_fence **fence) 412 { 413 struct amdgpu_device *adev = ring->adev; 414 struct dma_fence *f = NULL; 415 struct amdgpu_job *job; 416 struct amdgpu_ib *ib; 417 uint64_t addr; 418 int i, r; 419 420 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 421 if (r) 422 goto err; 423 424 ib = &job->ibs[0]; 425 addr = amdgpu_bo_gpu_offset(bo); 426 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 427 ib->ptr[1] = addr; 428 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 429 ib->ptr[3] = addr >> 32; 430 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 431 ib->ptr[5] = 0; 432 for (i = 6; i < 16; i += 2) { 433 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 434 ib->ptr[i+1] = 0; 435 } 436 ib->length_dw = 16; 437 438 r = amdgpu_job_submit_direct(job, ring, &f); 439 if (r) 440 goto err_free; 441 442 amdgpu_bo_fence(bo, f, false); 443 amdgpu_bo_unreserve(bo); 444 amdgpu_bo_unref(&bo); 445 446 if (fence) 447 *fence = dma_fence_get(f); 448 dma_fence_put(f); 449 450 return 0; 451 452 err_free: 453 amdgpu_job_free(job); 454 455 err: 456 amdgpu_bo_unreserve(bo); 457 amdgpu_bo_unref(&bo); 458 return r; 459 } 460 461 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 462 struct dma_fence **fence) 463 { 464 struct amdgpu_device *adev = ring->adev; 465 struct amdgpu_bo *bo = NULL; 466 uint32_t *msg; 467 int r, i; 468 469 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 470 AMDGPU_GEM_DOMAIN_VRAM, 471 &bo, NULL, (void **)&msg); 472 if (r) 473 return r; 474 475 msg[0] = cpu_to_le32(0x00000028); 476 msg[1] = cpu_to_le32(0x00000038); 477 msg[2] = cpu_to_le32(0x00000001); 478 msg[3] = cpu_to_le32(0x00000000); 479 msg[4] = cpu_to_le32(handle); 480 msg[5] = cpu_to_le32(0x00000000); 481 msg[6] = cpu_to_le32(0x00000001); 482 msg[7] = cpu_to_le32(0x00000028); 483 msg[8] = cpu_to_le32(0x00000010); 484 msg[9] = cpu_to_le32(0x00000000); 485 msg[10] = cpu_to_le32(0x00000007); 486 msg[11] = cpu_to_le32(0x00000000); 487 msg[12] = cpu_to_le32(0x00000780); 488 msg[13] = cpu_to_le32(0x00000440); 489 for (i = 14; i < 1024; ++i) 490 msg[i] = cpu_to_le32(0x0); 491 492 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 493 } 494 495 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 496 struct dma_fence **fence) 497 { 498 struct amdgpu_device *adev = ring->adev; 499 struct amdgpu_bo *bo = NULL; 500 uint32_t *msg; 501 int r, i; 502 503 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 504 AMDGPU_GEM_DOMAIN_VRAM, 505 &bo, NULL, (void **)&msg); 506 if (r) 507 return r; 508 509 msg[0] = cpu_to_le32(0x00000028); 510 msg[1] = cpu_to_le32(0x00000018); 511 msg[2] = cpu_to_le32(0x00000000); 512 msg[3] = cpu_to_le32(0x00000002); 513 msg[4] = cpu_to_le32(handle); 514 msg[5] = cpu_to_le32(0x00000000); 515 for (i = 6; i < 1024; ++i) 516 msg[i] = cpu_to_le32(0x0); 517 518 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 519 } 520 521 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 522 { 523 struct dma_fence *fence; 524 long r; 525 526 r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL); 527 if (r) 528 goto error; 529 530 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence); 531 if (r) 532 goto error; 533 534 r = dma_fence_wait_timeout(fence, false, timeout); 535 if (r == 0) 536 r = -ETIMEDOUT; 537 else if (r > 0) 538 r = 0; 539 540 dma_fence_put(fence); 541 error: 542 return r; 543 } 544 545 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 546 { 547 struct amdgpu_device *adev = ring->adev; 548 uint32_t rptr; 549 unsigned i; 550 int r; 551 552 r = amdgpu_ring_alloc(ring, 16); 553 if (r) 554 return r; 555 556 rptr = amdgpu_ring_get_rptr(ring); 557 558 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 559 amdgpu_ring_commit(ring); 560 561 for (i = 0; i < adev->usec_timeout; i++) { 562 if (amdgpu_ring_get_rptr(ring) != rptr) 563 break; 564 udelay(1); 565 } 566 567 if (i >= adev->usec_timeout) 568 r = -ETIMEDOUT; 569 570 return r; 571 } 572 573 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 574 struct amdgpu_bo *bo, 575 struct dma_fence **fence) 576 { 577 const unsigned ib_size_dw = 16; 578 struct amdgpu_job *job; 579 struct amdgpu_ib *ib; 580 struct dma_fence *f = NULL; 581 uint64_t addr; 582 int i, r; 583 584 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 585 if (r) 586 return r; 587 588 ib = &job->ibs[0]; 589 addr = amdgpu_bo_gpu_offset(bo); 590 591 ib->length_dw = 0; 592 ib->ptr[ib->length_dw++] = 0x00000018; 593 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 594 ib->ptr[ib->length_dw++] = handle; 595 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 596 ib->ptr[ib->length_dw++] = addr; 597 ib->ptr[ib->length_dw++] = 0x0000000b; 598 599 ib->ptr[ib->length_dw++] = 0x00000014; 600 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 601 ib->ptr[ib->length_dw++] = 0x0000001c; 602 ib->ptr[ib->length_dw++] = 0x00000000; 603 ib->ptr[ib->length_dw++] = 0x00000000; 604 605 ib->ptr[ib->length_dw++] = 0x00000008; 606 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 607 608 for (i = ib->length_dw; i < ib_size_dw; ++i) 609 ib->ptr[i] = 0x0; 610 611 r = amdgpu_job_submit_direct(job, ring, &f); 612 if (r) 613 goto err; 614 615 if (fence) 616 *fence = dma_fence_get(f); 617 dma_fence_put(f); 618 619 return 0; 620 621 err: 622 amdgpu_job_free(job); 623 return r; 624 } 625 626 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 627 struct amdgpu_bo *bo, 628 struct dma_fence **fence) 629 { 630 const unsigned ib_size_dw = 16; 631 struct amdgpu_job *job; 632 struct amdgpu_ib *ib; 633 struct dma_fence *f = NULL; 634 uint64_t addr; 635 int i, r; 636 637 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 638 if (r) 639 return r; 640 641 ib = &job->ibs[0]; 642 addr = amdgpu_bo_gpu_offset(bo); 643 644 ib->length_dw = 0; 645 ib->ptr[ib->length_dw++] = 0x00000018; 646 ib->ptr[ib->length_dw++] = 0x00000001; 647 ib->ptr[ib->length_dw++] = handle; 648 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 649 ib->ptr[ib->length_dw++] = addr; 650 ib->ptr[ib->length_dw++] = 0x0000000b; 651 652 ib->ptr[ib->length_dw++] = 0x00000014; 653 ib->ptr[ib->length_dw++] = 0x00000002; 654 ib->ptr[ib->length_dw++] = 0x0000001c; 655 ib->ptr[ib->length_dw++] = 0x00000000; 656 ib->ptr[ib->length_dw++] = 0x00000000; 657 658 ib->ptr[ib->length_dw++] = 0x00000008; 659 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 660 661 for (i = ib->length_dw; i < ib_size_dw; ++i) 662 ib->ptr[i] = 0x0; 663 664 r = amdgpu_job_submit_direct(job, ring, &f); 665 if (r) 666 goto err; 667 668 if (fence) 669 *fence = dma_fence_get(f); 670 dma_fence_put(f); 671 672 return 0; 673 674 err: 675 amdgpu_job_free(job); 676 return r; 677 } 678 679 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 680 { 681 struct dma_fence *fence = NULL; 682 struct amdgpu_bo *bo = NULL; 683 long r; 684 685 r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE, 686 AMDGPU_GEM_DOMAIN_VRAM, 687 &bo, NULL, NULL); 688 if (r) 689 return r; 690 691 r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL); 692 if (r) 693 goto error; 694 695 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence); 696 if (r) 697 goto error; 698 699 r = dma_fence_wait_timeout(fence, false, timeout); 700 if (r == 0) 701 r = -ETIMEDOUT; 702 else if (r > 0) 703 r = 0; 704 705 error: 706 dma_fence_put(fence); 707 amdgpu_bo_unreserve(bo); 708 amdgpu_bo_unref(&bo); 709 return r; 710 } 711 712 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring) 713 { 714 struct amdgpu_device *adev = ring->adev; 715 uint32_t tmp = 0; 716 unsigned i; 717 int r; 718 719 WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD); 720 r = amdgpu_ring_alloc(ring, 3); 721 if (r) 722 return r; 723 724 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0)); 725 amdgpu_ring_write(ring, 0xDEADBEEF); 726 amdgpu_ring_commit(ring); 727 728 for (i = 0; i < adev->usec_timeout; i++) { 729 tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); 730 if (tmp == 0xDEADBEEF) 731 break; 732 udelay(1); 733 } 734 735 if (i >= adev->usec_timeout) 736 r = -ETIMEDOUT; 737 738 return r; 739 } 740 741 static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle, 742 struct dma_fence **fence) 743 { 744 struct amdgpu_device *adev = ring->adev; 745 struct amdgpu_job *job; 746 struct amdgpu_ib *ib; 747 struct dma_fence *f = NULL; 748 const unsigned ib_size_dw = 16; 749 int i, r; 750 751 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 752 if (r) 753 return r; 754 755 ib = &job->ibs[0]; 756 757 ib->ptr[0] = PACKETJ(adev->vcn.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0); 758 ib->ptr[1] = 0xDEADBEEF; 759 for (i = 2; i < 16; i += 2) { 760 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); 761 ib->ptr[i+1] = 0; 762 } 763 ib->length_dw = 16; 764 765 r = amdgpu_job_submit_direct(job, ring, &f); 766 if (r) 767 goto err; 768 769 if (fence) 770 *fence = dma_fence_get(f); 771 dma_fence_put(f); 772 773 return 0; 774 775 err: 776 amdgpu_job_free(job); 777 return r; 778 } 779 780 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout) 781 { 782 struct amdgpu_device *adev = ring->adev; 783 uint32_t tmp = 0; 784 unsigned i; 785 struct dma_fence *fence = NULL; 786 long r = 0; 787 788 r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence); 789 if (r) 790 goto error; 791 792 r = dma_fence_wait_timeout(fence, false, timeout); 793 if (r == 0) { 794 r = -ETIMEDOUT; 795 goto error; 796 } else if (r < 0) { 797 goto error; 798 } else { 799 r = 0; 800 } 801 802 for (i = 0; i < adev->usec_timeout; i++) { 803 tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); 804 if (tmp == 0xDEADBEEF) 805 break; 806 udelay(1); 807 } 808 809 if (i >= adev->usec_timeout) 810 r = -ETIMEDOUT; 811 812 dma_fence_put(fence); 813 error: 814 return r; 815 } 816