1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 31 #include "amdgpu.h" 32 #include "amdgpu_pm.h" 33 #include "amdgpu_vcn.h" 34 #include "soc15d.h" 35 36 /* Firmware Names */ 37 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 38 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 39 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 40 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 41 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 42 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 43 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 44 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 45 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 46 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 47 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 48 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 49 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 50 51 MODULE_FIRMWARE(FIRMWARE_RAVEN); 52 MODULE_FIRMWARE(FIRMWARE_PICASSO); 53 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 54 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 55 MODULE_FIRMWARE(FIRMWARE_RENOIR); 56 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 57 MODULE_FIRMWARE(FIRMWARE_NAVI10); 58 MODULE_FIRMWARE(FIRMWARE_NAVI14); 59 MODULE_FIRMWARE(FIRMWARE_NAVI12); 60 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 61 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 62 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 63 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 64 65 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 66 67 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 68 { 69 unsigned long bo_size; 70 const char *fw_name; 71 const struct common_firmware_header *hdr; 72 unsigned char fw_check; 73 int i, r; 74 75 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 76 mutex_init(&adev->vcn.vcn_pg_lock); 77 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 78 atomic_set(&adev->vcn.total_submission_cnt, 0); 79 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 80 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 81 82 switch (adev->asic_type) { 83 case CHIP_RAVEN: 84 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 85 fw_name = FIRMWARE_RAVEN2; 86 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 87 fw_name = FIRMWARE_PICASSO; 88 else 89 fw_name = FIRMWARE_RAVEN; 90 break; 91 case CHIP_ARCTURUS: 92 fw_name = FIRMWARE_ARCTURUS; 93 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 94 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 95 adev->vcn.indirect_sram = true; 96 break; 97 case CHIP_RENOIR: 98 if (adev->apu_flags & AMD_APU_IS_RENOIR) 99 fw_name = FIRMWARE_RENOIR; 100 else 101 fw_name = FIRMWARE_GREEN_SARDINE; 102 103 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 104 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 105 adev->vcn.indirect_sram = true; 106 break; 107 case CHIP_NAVI10: 108 fw_name = FIRMWARE_NAVI10; 109 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 110 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 111 adev->vcn.indirect_sram = true; 112 break; 113 case CHIP_NAVI14: 114 fw_name = FIRMWARE_NAVI14; 115 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 116 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 117 adev->vcn.indirect_sram = true; 118 break; 119 case CHIP_NAVI12: 120 fw_name = FIRMWARE_NAVI12; 121 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 122 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 123 adev->vcn.indirect_sram = true; 124 break; 125 case CHIP_SIENNA_CICHLID: 126 fw_name = FIRMWARE_SIENNA_CICHLID; 127 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 128 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 129 adev->vcn.indirect_sram = true; 130 break; 131 case CHIP_NAVY_FLOUNDER: 132 fw_name = FIRMWARE_NAVY_FLOUNDER; 133 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 134 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 135 adev->vcn.indirect_sram = true; 136 break; 137 case CHIP_VANGOGH: 138 fw_name = FIRMWARE_VANGOGH; 139 break; 140 case CHIP_DIMGREY_CAVEFISH: 141 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 142 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 143 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 144 adev->vcn.indirect_sram = true; 145 break; 146 default: 147 return -EINVAL; 148 } 149 150 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 151 if (r) { 152 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 153 fw_name); 154 return r; 155 } 156 157 r = amdgpu_ucode_validate(adev->vcn.fw); 158 if (r) { 159 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 160 fw_name); 161 release_firmware(adev->vcn.fw); 162 adev->vcn.fw = NULL; 163 return r; 164 } 165 166 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 167 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 168 169 /* Bit 20-23, it is encode major and non-zero for new naming convention. 170 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 171 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 172 * is zero in old naming convention, this field is always zero so far. 173 * These four bits are used to tell which naming convention is present. 174 */ 175 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 176 if (fw_check) { 177 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 178 179 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 180 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 181 enc_major = fw_check; 182 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 183 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 184 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n", 185 enc_major, enc_minor, dec_ver, vep, fw_rev); 186 } else { 187 unsigned int version_major, version_minor, family_id; 188 189 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 190 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 191 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 192 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n", 193 version_major, version_minor, family_id); 194 } 195 196 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 197 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 198 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 199 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 200 201 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 202 if (adev->vcn.harvest_config & (1 << i)) 203 continue; 204 205 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 206 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 207 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 208 if (r) { 209 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 210 return r; 211 } 212 213 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr + 214 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 215 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr + 216 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 217 218 if (adev->vcn.indirect_sram) { 219 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 220 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 221 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 222 if (r) { 223 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 224 return r; 225 } 226 } 227 } 228 229 return 0; 230 } 231 232 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 233 { 234 int i, j; 235 236 cancel_delayed_work_sync(&adev->vcn.idle_work); 237 238 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 239 if (adev->vcn.harvest_config & (1 << j)) 240 continue; 241 242 if (adev->vcn.indirect_sram) { 243 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 244 &adev->vcn.inst[j].dpg_sram_gpu_addr, 245 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 246 } 247 kvfree(adev->vcn.inst[j].saved_bo); 248 249 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 250 &adev->vcn.inst[j].gpu_addr, 251 (void **)&adev->vcn.inst[j].cpu_addr); 252 253 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 254 255 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 256 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 257 } 258 259 release_firmware(adev->vcn.fw); 260 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 261 mutex_destroy(&adev->vcn.vcn_pg_lock); 262 263 return 0; 264 } 265 266 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 267 { 268 unsigned size; 269 void *ptr; 270 int i; 271 272 cancel_delayed_work_sync(&adev->vcn.idle_work); 273 274 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 275 if (adev->vcn.harvest_config & (1 << i)) 276 continue; 277 if (adev->vcn.inst[i].vcpu_bo == NULL) 278 return 0; 279 280 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 281 ptr = adev->vcn.inst[i].cpu_addr; 282 283 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 284 if (!adev->vcn.inst[i].saved_bo) 285 return -ENOMEM; 286 287 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 288 } 289 return 0; 290 } 291 292 int amdgpu_vcn_resume(struct amdgpu_device *adev) 293 { 294 unsigned size; 295 void *ptr; 296 int i; 297 298 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 299 if (adev->vcn.harvest_config & (1 << i)) 300 continue; 301 if (adev->vcn.inst[i].vcpu_bo == NULL) 302 return -EINVAL; 303 304 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 305 ptr = adev->vcn.inst[i].cpu_addr; 306 307 if (adev->vcn.inst[i].saved_bo != NULL) { 308 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 309 kvfree(adev->vcn.inst[i].saved_bo); 310 adev->vcn.inst[i].saved_bo = NULL; 311 } else { 312 const struct common_firmware_header *hdr; 313 unsigned offset; 314 315 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 316 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 317 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 318 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 319 le32_to_cpu(hdr->ucode_size_bytes)); 320 size -= le32_to_cpu(hdr->ucode_size_bytes); 321 ptr += le32_to_cpu(hdr->ucode_size_bytes); 322 } 323 memset_io(ptr, 0, size); 324 } 325 } 326 return 0; 327 } 328 329 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 330 { 331 struct amdgpu_device *adev = 332 container_of(work, struct amdgpu_device, vcn.idle_work.work); 333 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 334 unsigned int i, j; 335 336 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 337 if (adev->vcn.harvest_config & (1 << j)) 338 continue; 339 340 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 341 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 342 } 343 344 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 345 struct dpg_pause_state new_state; 346 347 if (fence[j] || 348 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 349 new_state.fw_based = VCN_DPG_STATE__PAUSE; 350 else 351 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 352 353 adev->vcn.pause_dpg_mode(adev, j, &new_state); 354 } 355 356 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 357 fences += fence[j]; 358 } 359 360 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 361 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 362 AMD_PG_STATE_GATE); 363 } else { 364 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 365 } 366 } 367 368 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 369 { 370 struct amdgpu_device *adev = ring->adev; 371 372 atomic_inc(&adev->vcn.total_submission_cnt); 373 cancel_delayed_work_sync(&adev->vcn.idle_work); 374 375 mutex_lock(&adev->vcn.vcn_pg_lock); 376 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 377 AMD_PG_STATE_UNGATE); 378 379 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 380 struct dpg_pause_state new_state; 381 382 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 383 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 384 new_state.fw_based = VCN_DPG_STATE__PAUSE; 385 } else { 386 unsigned int fences = 0; 387 unsigned int i; 388 389 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 390 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 391 392 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 393 new_state.fw_based = VCN_DPG_STATE__PAUSE; 394 else 395 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 396 } 397 398 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 399 } 400 mutex_unlock(&adev->vcn.vcn_pg_lock); 401 } 402 403 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 404 { 405 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 406 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 407 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 408 409 atomic_dec(&ring->adev->vcn.total_submission_cnt); 410 411 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 412 } 413 414 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 415 { 416 struct amdgpu_device *adev = ring->adev; 417 uint32_t tmp = 0; 418 unsigned i; 419 int r; 420 421 /* VCN in SRIOV does not support direct register read/write */ 422 if (amdgpu_sriov_vf(adev)) 423 return 0; 424 425 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 426 r = amdgpu_ring_alloc(ring, 3); 427 if (r) 428 return r; 429 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 430 amdgpu_ring_write(ring, 0xDEADBEEF); 431 amdgpu_ring_commit(ring); 432 for (i = 0; i < adev->usec_timeout; i++) { 433 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 434 if (tmp == 0xDEADBEEF) 435 break; 436 udelay(1); 437 } 438 439 if (i >= adev->usec_timeout) 440 r = -ETIMEDOUT; 441 442 return r; 443 } 444 445 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 446 struct amdgpu_bo *bo, 447 struct dma_fence **fence) 448 { 449 struct amdgpu_device *adev = ring->adev; 450 struct dma_fence *f = NULL; 451 struct amdgpu_job *job; 452 struct amdgpu_ib *ib; 453 uint64_t addr; 454 int i, r; 455 456 r = amdgpu_job_alloc_with_ib(adev, 64, 457 AMDGPU_IB_POOL_DIRECT, &job); 458 if (r) 459 goto err; 460 461 ib = &job->ibs[0]; 462 addr = amdgpu_bo_gpu_offset(bo); 463 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 464 ib->ptr[1] = addr; 465 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 466 ib->ptr[3] = addr >> 32; 467 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 468 ib->ptr[5] = 0; 469 for (i = 6; i < 16; i += 2) { 470 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 471 ib->ptr[i+1] = 0; 472 } 473 ib->length_dw = 16; 474 475 r = amdgpu_job_submit_direct(job, ring, &f); 476 if (r) 477 goto err_free; 478 479 amdgpu_bo_fence(bo, f, false); 480 amdgpu_bo_unreserve(bo); 481 amdgpu_bo_unref(&bo); 482 483 if (fence) 484 *fence = dma_fence_get(f); 485 dma_fence_put(f); 486 487 return 0; 488 489 err_free: 490 amdgpu_job_free(job); 491 492 err: 493 amdgpu_bo_unreserve(bo); 494 amdgpu_bo_unref(&bo); 495 return r; 496 } 497 498 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 499 struct dma_fence **fence) 500 { 501 struct amdgpu_device *adev = ring->adev; 502 struct amdgpu_bo *bo = NULL; 503 uint32_t *msg; 504 int r, i; 505 506 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 507 AMDGPU_GEM_DOMAIN_VRAM, 508 &bo, NULL, (void **)&msg); 509 if (r) 510 return r; 511 512 msg[0] = cpu_to_le32(0x00000028); 513 msg[1] = cpu_to_le32(0x00000038); 514 msg[2] = cpu_to_le32(0x00000001); 515 msg[3] = cpu_to_le32(0x00000000); 516 msg[4] = cpu_to_le32(handle); 517 msg[5] = cpu_to_le32(0x00000000); 518 msg[6] = cpu_to_le32(0x00000001); 519 msg[7] = cpu_to_le32(0x00000028); 520 msg[8] = cpu_to_le32(0x00000010); 521 msg[9] = cpu_to_le32(0x00000000); 522 msg[10] = cpu_to_le32(0x00000007); 523 msg[11] = cpu_to_le32(0x00000000); 524 msg[12] = cpu_to_le32(0x00000780); 525 msg[13] = cpu_to_le32(0x00000440); 526 for (i = 14; i < 1024; ++i) 527 msg[i] = cpu_to_le32(0x0); 528 529 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 530 } 531 532 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 533 struct dma_fence **fence) 534 { 535 struct amdgpu_device *adev = ring->adev; 536 struct amdgpu_bo *bo = NULL; 537 uint32_t *msg; 538 int r, i; 539 540 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 541 AMDGPU_GEM_DOMAIN_VRAM, 542 &bo, NULL, (void **)&msg); 543 if (r) 544 return r; 545 546 msg[0] = cpu_to_le32(0x00000028); 547 msg[1] = cpu_to_le32(0x00000018); 548 msg[2] = cpu_to_le32(0x00000000); 549 msg[3] = cpu_to_le32(0x00000002); 550 msg[4] = cpu_to_le32(handle); 551 msg[5] = cpu_to_le32(0x00000000); 552 for (i = 6; i < 1024; ++i) 553 msg[i] = cpu_to_le32(0x0); 554 555 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 556 } 557 558 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 559 { 560 struct dma_fence *fence; 561 long r; 562 563 r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL); 564 if (r) 565 goto error; 566 567 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence); 568 if (r) 569 goto error; 570 571 r = dma_fence_wait_timeout(fence, false, timeout); 572 if (r == 0) 573 r = -ETIMEDOUT; 574 else if (r > 0) 575 r = 0; 576 577 dma_fence_put(fence); 578 error: 579 return r; 580 } 581 582 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 583 { 584 struct amdgpu_device *adev = ring->adev; 585 uint32_t rptr; 586 unsigned i; 587 int r; 588 589 if (amdgpu_sriov_vf(adev)) 590 return 0; 591 592 r = amdgpu_ring_alloc(ring, 16); 593 if (r) 594 return r; 595 596 rptr = amdgpu_ring_get_rptr(ring); 597 598 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 599 amdgpu_ring_commit(ring); 600 601 for (i = 0; i < adev->usec_timeout; i++) { 602 if (amdgpu_ring_get_rptr(ring) != rptr) 603 break; 604 udelay(1); 605 } 606 607 if (i >= adev->usec_timeout) 608 r = -ETIMEDOUT; 609 610 return r; 611 } 612 613 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 614 struct amdgpu_bo *bo, 615 struct dma_fence **fence) 616 { 617 const unsigned ib_size_dw = 16; 618 struct amdgpu_job *job; 619 struct amdgpu_ib *ib; 620 struct dma_fence *f = NULL; 621 uint64_t addr; 622 int i, r; 623 624 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 625 AMDGPU_IB_POOL_DIRECT, &job); 626 if (r) 627 return r; 628 629 ib = &job->ibs[0]; 630 addr = amdgpu_bo_gpu_offset(bo); 631 632 ib->length_dw = 0; 633 ib->ptr[ib->length_dw++] = 0x00000018; 634 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 635 ib->ptr[ib->length_dw++] = handle; 636 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 637 ib->ptr[ib->length_dw++] = addr; 638 ib->ptr[ib->length_dw++] = 0x0000000b; 639 640 ib->ptr[ib->length_dw++] = 0x00000014; 641 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 642 ib->ptr[ib->length_dw++] = 0x0000001c; 643 ib->ptr[ib->length_dw++] = 0x00000000; 644 ib->ptr[ib->length_dw++] = 0x00000000; 645 646 ib->ptr[ib->length_dw++] = 0x00000008; 647 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 648 649 for (i = ib->length_dw; i < ib_size_dw; ++i) 650 ib->ptr[i] = 0x0; 651 652 r = amdgpu_job_submit_direct(job, ring, &f); 653 if (r) 654 goto err; 655 656 if (fence) 657 *fence = dma_fence_get(f); 658 dma_fence_put(f); 659 660 return 0; 661 662 err: 663 amdgpu_job_free(job); 664 return r; 665 } 666 667 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 668 struct amdgpu_bo *bo, 669 struct dma_fence **fence) 670 { 671 const unsigned ib_size_dw = 16; 672 struct amdgpu_job *job; 673 struct amdgpu_ib *ib; 674 struct dma_fence *f = NULL; 675 uint64_t addr; 676 int i, r; 677 678 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 679 AMDGPU_IB_POOL_DIRECT, &job); 680 if (r) 681 return r; 682 683 ib = &job->ibs[0]; 684 addr = amdgpu_bo_gpu_offset(bo); 685 686 ib->length_dw = 0; 687 ib->ptr[ib->length_dw++] = 0x00000018; 688 ib->ptr[ib->length_dw++] = 0x00000001; 689 ib->ptr[ib->length_dw++] = handle; 690 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 691 ib->ptr[ib->length_dw++] = addr; 692 ib->ptr[ib->length_dw++] = 0x0000000b; 693 694 ib->ptr[ib->length_dw++] = 0x00000014; 695 ib->ptr[ib->length_dw++] = 0x00000002; 696 ib->ptr[ib->length_dw++] = 0x0000001c; 697 ib->ptr[ib->length_dw++] = 0x00000000; 698 ib->ptr[ib->length_dw++] = 0x00000000; 699 700 ib->ptr[ib->length_dw++] = 0x00000008; 701 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 702 703 for (i = ib->length_dw; i < ib_size_dw; ++i) 704 ib->ptr[i] = 0x0; 705 706 r = amdgpu_job_submit_direct(job, ring, &f); 707 if (r) 708 goto err; 709 710 if (fence) 711 *fence = dma_fence_get(f); 712 dma_fence_put(f); 713 714 return 0; 715 716 err: 717 amdgpu_job_free(job); 718 return r; 719 } 720 721 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 722 { 723 struct dma_fence *fence = NULL; 724 struct amdgpu_bo *bo = NULL; 725 long r; 726 727 r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE, 728 AMDGPU_GEM_DOMAIN_VRAM, 729 &bo, NULL, NULL); 730 if (r) 731 return r; 732 733 r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL); 734 if (r) 735 goto error; 736 737 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence); 738 if (r) 739 goto error; 740 741 r = dma_fence_wait_timeout(fence, false, timeout); 742 if (r == 0) 743 r = -ETIMEDOUT; 744 else if (r > 0) 745 r = 0; 746 747 error: 748 dma_fence_put(fence); 749 amdgpu_bo_unreserve(bo); 750 amdgpu_bo_unref(&bo); 751 return r; 752 } 753