1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 31 #include <drm/drm.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_pm.h" 35 #include "amdgpu_vcn.h" 36 #include "soc15d.h" 37 #include "soc15_common.h" 38 39 #include "vcn/vcn_1_0_offset.h" 40 #include "vcn/vcn_1_0_sh_mask.h" 41 42 /* 1 second timeout */ 43 #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) 44 45 /* Firmware Names */ 46 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 47 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 48 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 49 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 50 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 51 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 52 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 53 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 54 55 MODULE_FIRMWARE(FIRMWARE_RAVEN); 56 MODULE_FIRMWARE(FIRMWARE_PICASSO); 57 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 59 MODULE_FIRMWARE(FIRMWARE_RENOIR); 60 MODULE_FIRMWARE(FIRMWARE_NAVI10); 61 MODULE_FIRMWARE(FIRMWARE_NAVI14); 62 MODULE_FIRMWARE(FIRMWARE_NAVI12); 63 64 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 65 66 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 67 { 68 unsigned long bo_size; 69 const char *fw_name; 70 const struct common_firmware_header *hdr; 71 unsigned char fw_check; 72 int i, r; 73 74 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 75 76 switch (adev->asic_type) { 77 case CHIP_RAVEN: 78 if (adev->rev_id >= 8) 79 fw_name = FIRMWARE_RAVEN2; 80 else if (adev->pdev->device == 0x15d8) 81 fw_name = FIRMWARE_PICASSO; 82 else 83 fw_name = FIRMWARE_RAVEN; 84 break; 85 case CHIP_ARCTURUS: 86 fw_name = FIRMWARE_ARCTURUS; 87 break; 88 case CHIP_RENOIR: 89 fw_name = FIRMWARE_RENOIR; 90 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 91 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 92 adev->vcn.indirect_sram = true; 93 break; 94 case CHIP_NAVI10: 95 fw_name = FIRMWARE_NAVI10; 96 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 97 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 98 adev->vcn.indirect_sram = true; 99 break; 100 case CHIP_NAVI14: 101 fw_name = FIRMWARE_NAVI14; 102 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 103 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) && 104 adev->asic_type != CHIP_RENOIR) /* to be removed while vcn psp loading works */ 105 adev->vcn.indirect_sram = true; 106 break; 107 case CHIP_NAVI12: 108 fw_name = FIRMWARE_NAVI12; 109 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 110 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 111 adev->vcn.indirect_sram = true; 112 break; 113 default: 114 return -EINVAL; 115 } 116 117 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 118 if (r) { 119 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 120 fw_name); 121 return r; 122 } 123 124 r = amdgpu_ucode_validate(adev->vcn.fw); 125 if (r) { 126 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 127 fw_name); 128 release_firmware(adev->vcn.fw); 129 adev->vcn.fw = NULL; 130 return r; 131 } 132 133 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 134 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 135 136 /* Bit 20-23, it is encode major and non-zero for new naming convention. 137 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 138 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 139 * is zero in old naming convention, this field is always zero so far. 140 * These four bits are used to tell which naming convention is present. 141 */ 142 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 143 if (fw_check) { 144 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 145 146 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 147 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 148 enc_major = fw_check; 149 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 150 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 151 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n", 152 enc_major, enc_minor, dec_ver, vep, fw_rev); 153 } else { 154 unsigned int version_major, version_minor, family_id; 155 156 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 157 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 158 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 159 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n", 160 version_major, version_minor, family_id); 161 } 162 163 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 164 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || 165 adev->asic_type == CHIP_RENOIR) 166 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 167 168 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 169 if (adev->vcn.harvest_config & (1 << i)) 170 continue; 171 172 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 173 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 174 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 175 if (r) { 176 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 177 return r; 178 } 179 } 180 181 if (adev->vcn.indirect_sram) { 182 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 183 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.dpg_sram_bo, 184 &adev->vcn.dpg_sram_gpu_addr, &adev->vcn.dpg_sram_cpu_addr); 185 if (r) { 186 dev_err(adev->dev, "(%d) failed to allocate DPG bo\n", r); 187 return r; 188 } 189 } 190 191 return 0; 192 } 193 194 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 195 { 196 int i, j; 197 198 if (adev->vcn.indirect_sram) { 199 amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo, 200 &adev->vcn.dpg_sram_gpu_addr, 201 (void **)&adev->vcn.dpg_sram_cpu_addr); 202 } 203 204 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 205 if (adev->vcn.harvest_config & (1 << j)) 206 continue; 207 kvfree(adev->vcn.inst[j].saved_bo); 208 209 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 210 &adev->vcn.inst[j].gpu_addr, 211 (void **)&adev->vcn.inst[j].cpu_addr); 212 213 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 214 215 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 216 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 217 218 amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg); 219 } 220 221 release_firmware(adev->vcn.fw); 222 223 return 0; 224 } 225 226 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 227 { 228 unsigned size; 229 void *ptr; 230 int i; 231 232 cancel_delayed_work_sync(&adev->vcn.idle_work); 233 234 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 235 if (adev->vcn.harvest_config & (1 << i)) 236 continue; 237 if (adev->vcn.inst[i].vcpu_bo == NULL) 238 return 0; 239 240 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 241 ptr = adev->vcn.inst[i].cpu_addr; 242 243 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 244 if (!adev->vcn.inst[i].saved_bo) 245 return -ENOMEM; 246 247 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 248 } 249 return 0; 250 } 251 252 int amdgpu_vcn_resume(struct amdgpu_device *adev) 253 { 254 unsigned size; 255 void *ptr; 256 int i; 257 258 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 259 if (adev->vcn.harvest_config & (1 << i)) 260 continue; 261 if (adev->vcn.inst[i].vcpu_bo == NULL) 262 return -EINVAL; 263 264 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 265 ptr = adev->vcn.inst[i].cpu_addr; 266 267 if (adev->vcn.inst[i].saved_bo != NULL) { 268 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 269 kvfree(adev->vcn.inst[i].saved_bo); 270 adev->vcn.inst[i].saved_bo = NULL; 271 } else { 272 const struct common_firmware_header *hdr; 273 unsigned offset; 274 275 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 276 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || 277 adev->asic_type == CHIP_RENOIR) { 278 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 279 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 280 le32_to_cpu(hdr->ucode_size_bytes)); 281 size -= le32_to_cpu(hdr->ucode_size_bytes); 282 ptr += le32_to_cpu(hdr->ucode_size_bytes); 283 } 284 memset_io(ptr, 0, size); 285 } 286 } 287 return 0; 288 } 289 290 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 291 { 292 struct amdgpu_device *adev = 293 container_of(work, struct amdgpu_device, vcn.idle_work.work); 294 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 295 unsigned int i, j; 296 297 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 298 if (adev->vcn.harvest_config & (1 << j)) 299 continue; 300 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 301 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 302 } 303 304 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 305 struct dpg_pause_state new_state; 306 307 if (fence[j]) 308 new_state.fw_based = VCN_DPG_STATE__PAUSE; 309 else 310 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 311 312 if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg)) 313 new_state.jpeg = VCN_DPG_STATE__PAUSE; 314 else 315 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 316 317 adev->vcn.pause_dpg_mode(adev, &new_state); 318 } 319 320 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg); 321 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 322 fences += fence[j]; 323 } 324 325 if (fences == 0) { 326 amdgpu_gfx_off_ctrl(adev, true); 327 if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled) 328 amdgpu_dpm_enable_uvd(adev, false); 329 else 330 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 331 AMD_PG_STATE_GATE); 332 } else { 333 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 334 } 335 } 336 337 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 338 { 339 struct amdgpu_device *adev = ring->adev; 340 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 341 342 if (set_clocks) { 343 amdgpu_gfx_off_ctrl(adev, false); 344 if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled) 345 amdgpu_dpm_enable_uvd(adev, true); 346 else 347 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 348 AMD_PG_STATE_UNGATE); 349 } 350 351 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 352 struct dpg_pause_state new_state; 353 unsigned int fences = 0; 354 unsigned int i; 355 356 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 357 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 358 } 359 if (fences) 360 new_state.fw_based = VCN_DPG_STATE__PAUSE; 361 else 362 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 363 364 if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg)) 365 new_state.jpeg = VCN_DPG_STATE__PAUSE; 366 else 367 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 368 369 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 370 new_state.fw_based = VCN_DPG_STATE__PAUSE; 371 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 372 new_state.jpeg = VCN_DPG_STATE__PAUSE; 373 374 adev->vcn.pause_dpg_mode(adev, &new_state); 375 } 376 } 377 378 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 379 { 380 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 381 } 382 383 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 384 { 385 struct amdgpu_device *adev = ring->adev; 386 uint32_t tmp = 0; 387 unsigned i; 388 int r; 389 390 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 391 r = amdgpu_ring_alloc(ring, 3); 392 if (r) 393 return r; 394 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 395 amdgpu_ring_write(ring, 0xDEADBEEF); 396 amdgpu_ring_commit(ring); 397 for (i = 0; i < adev->usec_timeout; i++) { 398 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 399 if (tmp == 0xDEADBEEF) 400 break; 401 udelay(1); 402 } 403 404 if (i >= adev->usec_timeout) 405 r = -ETIMEDOUT; 406 407 return r; 408 } 409 410 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 411 struct amdgpu_bo *bo, 412 struct dma_fence **fence) 413 { 414 struct amdgpu_device *adev = ring->adev; 415 struct dma_fence *f = NULL; 416 struct amdgpu_job *job; 417 struct amdgpu_ib *ib; 418 uint64_t addr; 419 int i, r; 420 421 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 422 if (r) 423 goto err; 424 425 ib = &job->ibs[0]; 426 addr = amdgpu_bo_gpu_offset(bo); 427 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 428 ib->ptr[1] = addr; 429 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 430 ib->ptr[3] = addr >> 32; 431 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 432 ib->ptr[5] = 0; 433 for (i = 6; i < 16; i += 2) { 434 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 435 ib->ptr[i+1] = 0; 436 } 437 ib->length_dw = 16; 438 439 r = amdgpu_job_submit_direct(job, ring, &f); 440 if (r) 441 goto err_free; 442 443 amdgpu_bo_fence(bo, f, false); 444 amdgpu_bo_unreserve(bo); 445 amdgpu_bo_unref(&bo); 446 447 if (fence) 448 *fence = dma_fence_get(f); 449 dma_fence_put(f); 450 451 return 0; 452 453 err_free: 454 amdgpu_job_free(job); 455 456 err: 457 amdgpu_bo_unreserve(bo); 458 amdgpu_bo_unref(&bo); 459 return r; 460 } 461 462 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 463 struct dma_fence **fence) 464 { 465 struct amdgpu_device *adev = ring->adev; 466 struct amdgpu_bo *bo = NULL; 467 uint32_t *msg; 468 int r, i; 469 470 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 471 AMDGPU_GEM_DOMAIN_VRAM, 472 &bo, NULL, (void **)&msg); 473 if (r) 474 return r; 475 476 msg[0] = cpu_to_le32(0x00000028); 477 msg[1] = cpu_to_le32(0x00000038); 478 msg[2] = cpu_to_le32(0x00000001); 479 msg[3] = cpu_to_le32(0x00000000); 480 msg[4] = cpu_to_le32(handle); 481 msg[5] = cpu_to_le32(0x00000000); 482 msg[6] = cpu_to_le32(0x00000001); 483 msg[7] = cpu_to_le32(0x00000028); 484 msg[8] = cpu_to_le32(0x00000010); 485 msg[9] = cpu_to_le32(0x00000000); 486 msg[10] = cpu_to_le32(0x00000007); 487 msg[11] = cpu_to_le32(0x00000000); 488 msg[12] = cpu_to_le32(0x00000780); 489 msg[13] = cpu_to_le32(0x00000440); 490 for (i = 14; i < 1024; ++i) 491 msg[i] = cpu_to_le32(0x0); 492 493 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 494 } 495 496 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 497 struct dma_fence **fence) 498 { 499 struct amdgpu_device *adev = ring->adev; 500 struct amdgpu_bo *bo = NULL; 501 uint32_t *msg; 502 int r, i; 503 504 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 505 AMDGPU_GEM_DOMAIN_VRAM, 506 &bo, NULL, (void **)&msg); 507 if (r) 508 return r; 509 510 msg[0] = cpu_to_le32(0x00000028); 511 msg[1] = cpu_to_le32(0x00000018); 512 msg[2] = cpu_to_le32(0x00000000); 513 msg[3] = cpu_to_le32(0x00000002); 514 msg[4] = cpu_to_le32(handle); 515 msg[5] = cpu_to_le32(0x00000000); 516 for (i = 6; i < 1024; ++i) 517 msg[i] = cpu_to_le32(0x0); 518 519 return amdgpu_vcn_dec_send_msg(ring, bo, fence); 520 } 521 522 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 523 { 524 struct dma_fence *fence; 525 long r; 526 527 r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL); 528 if (r) 529 goto error; 530 531 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence); 532 if (r) 533 goto error; 534 535 r = dma_fence_wait_timeout(fence, false, timeout); 536 if (r == 0) 537 r = -ETIMEDOUT; 538 else if (r > 0) 539 r = 0; 540 541 dma_fence_put(fence); 542 error: 543 return r; 544 } 545 546 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 547 { 548 struct amdgpu_device *adev = ring->adev; 549 uint32_t rptr; 550 unsigned i; 551 int r; 552 553 r = amdgpu_ring_alloc(ring, 16); 554 if (r) 555 return r; 556 557 rptr = amdgpu_ring_get_rptr(ring); 558 559 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 560 amdgpu_ring_commit(ring); 561 562 for (i = 0; i < adev->usec_timeout; i++) { 563 if (amdgpu_ring_get_rptr(ring) != rptr) 564 break; 565 udelay(1); 566 } 567 568 if (i >= adev->usec_timeout) 569 r = -ETIMEDOUT; 570 571 return r; 572 } 573 574 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 575 struct dma_fence **fence) 576 { 577 const unsigned ib_size_dw = 16; 578 struct amdgpu_job *job; 579 struct amdgpu_ib *ib; 580 struct dma_fence *f = NULL; 581 uint64_t dummy; 582 int i, r; 583 584 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 585 if (r) 586 return r; 587 588 ib = &job->ibs[0]; 589 dummy = ib->gpu_addr + 1024; 590 591 ib->length_dw = 0; 592 ib->ptr[ib->length_dw++] = 0x00000018; 593 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 594 ib->ptr[ib->length_dw++] = handle; 595 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 596 ib->ptr[ib->length_dw++] = dummy; 597 ib->ptr[ib->length_dw++] = 0x0000000b; 598 599 ib->ptr[ib->length_dw++] = 0x00000014; 600 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 601 ib->ptr[ib->length_dw++] = 0x0000001c; 602 ib->ptr[ib->length_dw++] = 0x00000000; 603 ib->ptr[ib->length_dw++] = 0x00000000; 604 605 ib->ptr[ib->length_dw++] = 0x00000008; 606 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 607 608 for (i = ib->length_dw; i < ib_size_dw; ++i) 609 ib->ptr[i] = 0x0; 610 611 r = amdgpu_job_submit_direct(job, ring, &f); 612 if (r) 613 goto err; 614 615 if (fence) 616 *fence = dma_fence_get(f); 617 dma_fence_put(f); 618 619 return 0; 620 621 err: 622 amdgpu_job_free(job); 623 return r; 624 } 625 626 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 627 struct dma_fence **fence) 628 { 629 const unsigned ib_size_dw = 16; 630 struct amdgpu_job *job; 631 struct amdgpu_ib *ib; 632 struct dma_fence *f = NULL; 633 uint64_t dummy; 634 int i, r; 635 636 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 637 if (r) 638 return r; 639 640 ib = &job->ibs[0]; 641 dummy = ib->gpu_addr + 1024; 642 643 ib->length_dw = 0; 644 ib->ptr[ib->length_dw++] = 0x00000018; 645 ib->ptr[ib->length_dw++] = 0x00000001; 646 ib->ptr[ib->length_dw++] = handle; 647 ib->ptr[ib->length_dw++] = upper_32_bits(dummy); 648 ib->ptr[ib->length_dw++] = dummy; 649 ib->ptr[ib->length_dw++] = 0x0000000b; 650 651 ib->ptr[ib->length_dw++] = 0x00000014; 652 ib->ptr[ib->length_dw++] = 0x00000002; 653 ib->ptr[ib->length_dw++] = 0x0000001c; 654 ib->ptr[ib->length_dw++] = 0x00000000; 655 ib->ptr[ib->length_dw++] = 0x00000000; 656 657 ib->ptr[ib->length_dw++] = 0x00000008; 658 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 659 660 for (i = ib->length_dw; i < ib_size_dw; ++i) 661 ib->ptr[i] = 0x0; 662 663 r = amdgpu_job_submit_direct(job, ring, &f); 664 if (r) 665 goto err; 666 667 if (fence) 668 *fence = dma_fence_get(f); 669 dma_fence_put(f); 670 671 return 0; 672 673 err: 674 amdgpu_job_free(job); 675 return r; 676 } 677 678 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 679 { 680 struct dma_fence *fence = NULL; 681 long r; 682 683 r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL); 684 if (r) 685 goto error; 686 687 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence); 688 if (r) 689 goto error; 690 691 r = dma_fence_wait_timeout(fence, false, timeout); 692 if (r == 0) 693 r = -ETIMEDOUT; 694 else if (r > 0) 695 r = 0; 696 697 error: 698 dma_fence_put(fence); 699 return r; 700 } 701 702 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring) 703 { 704 struct amdgpu_device *adev = ring->adev; 705 uint32_t tmp = 0; 706 unsigned i; 707 int r; 708 709 WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD); 710 r = amdgpu_ring_alloc(ring, 3); 711 if (r) 712 return r; 713 714 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0)); 715 amdgpu_ring_write(ring, 0xDEADBEEF); 716 amdgpu_ring_commit(ring); 717 718 for (i = 0; i < adev->usec_timeout; i++) { 719 tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); 720 if (tmp == 0xDEADBEEF) 721 break; 722 udelay(1); 723 } 724 725 if (i >= adev->usec_timeout) 726 r = -ETIMEDOUT; 727 728 return r; 729 } 730 731 static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle, 732 struct dma_fence **fence) 733 { 734 struct amdgpu_device *adev = ring->adev; 735 struct amdgpu_job *job; 736 struct amdgpu_ib *ib; 737 struct dma_fence *f = NULL; 738 const unsigned ib_size_dw = 16; 739 int i, r; 740 741 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); 742 if (r) 743 return r; 744 745 ib = &job->ibs[0]; 746 747 ib->ptr[0] = PACKETJ(adev->vcn.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0); 748 ib->ptr[1] = 0xDEADBEEF; 749 for (i = 2; i < 16; i += 2) { 750 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); 751 ib->ptr[i+1] = 0; 752 } 753 ib->length_dw = 16; 754 755 r = amdgpu_job_submit_direct(job, ring, &f); 756 if (r) 757 goto err; 758 759 if (fence) 760 *fence = dma_fence_get(f); 761 dma_fence_put(f); 762 763 return 0; 764 765 err: 766 amdgpu_job_free(job); 767 return r; 768 } 769 770 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout) 771 { 772 struct amdgpu_device *adev = ring->adev; 773 uint32_t tmp = 0; 774 unsigned i; 775 struct dma_fence *fence = NULL; 776 long r = 0; 777 778 r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence); 779 if (r) 780 goto error; 781 782 r = dma_fence_wait_timeout(fence, false, timeout); 783 if (r == 0) { 784 r = -ETIMEDOUT; 785 goto error; 786 } else if (r < 0) { 787 goto error; 788 } else { 789 r = 0; 790 } 791 792 for (i = 0; i < adev->usec_timeout; i++) { 793 tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); 794 if (tmp == 0xDEADBEEF) 795 break; 796 udelay(1); 797 } 798 799 if (i >= adev->usec_timeout) 800 r = -ETIMEDOUT; 801 802 dma_fence_put(fence); 803 error: 804 return r; 805 } 806