1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <drm/drm_drv.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_vcn.h" 35 #include "soc15d.h" 36 37 /* Firmware Names */ 38 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 39 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 40 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 41 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 42 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 43 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 44 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 45 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 46 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 48 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 49 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 50 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 51 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 52 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 53 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 54 55 MODULE_FIRMWARE(FIRMWARE_RAVEN); 56 MODULE_FIRMWARE(FIRMWARE_PICASSO); 57 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 59 MODULE_FIRMWARE(FIRMWARE_RENOIR); 60 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 61 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 62 MODULE_FIRMWARE(FIRMWARE_NAVI10); 63 MODULE_FIRMWARE(FIRMWARE_NAVI14); 64 MODULE_FIRMWARE(FIRMWARE_NAVI12); 65 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 66 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 67 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 68 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 69 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 70 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 71 72 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 73 74 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 75 { 76 unsigned long bo_size; 77 const char *fw_name; 78 const struct common_firmware_header *hdr; 79 unsigned char fw_check; 80 int i, r; 81 82 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 83 mutex_init(&adev->vcn.vcn_pg_lock); 84 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 85 atomic_set(&adev->vcn.total_submission_cnt, 0); 86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 87 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 88 89 switch (adev->ip_versions[UVD_HWIP][0]) { 90 case IP_VERSION(1, 0, 0): 91 case IP_VERSION(1, 0, 1): 92 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 93 fw_name = FIRMWARE_RAVEN2; 94 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 95 fw_name = FIRMWARE_PICASSO; 96 else 97 fw_name = FIRMWARE_RAVEN; 98 break; 99 case IP_VERSION(2, 5, 0): 100 fw_name = FIRMWARE_ARCTURUS; 101 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 102 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 103 adev->vcn.indirect_sram = true; 104 break; 105 case IP_VERSION(2, 2, 0): 106 if (adev->apu_flags & AMD_APU_IS_RENOIR) 107 fw_name = FIRMWARE_RENOIR; 108 else 109 fw_name = FIRMWARE_GREEN_SARDINE; 110 111 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 112 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 113 adev->vcn.indirect_sram = true; 114 break; 115 case IP_VERSION(2, 6, 0): 116 fw_name = FIRMWARE_ALDEBARAN; 117 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 118 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 119 adev->vcn.indirect_sram = true; 120 break; 121 case IP_VERSION(2, 0, 0): 122 fw_name = FIRMWARE_NAVI10; 123 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 124 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 125 adev->vcn.indirect_sram = true; 126 break; 127 case IP_VERSION(2, 0, 2): 128 if (adev->asic_type == CHIP_NAVI12) 129 fw_name = FIRMWARE_NAVI12; 130 else 131 fw_name = FIRMWARE_NAVI14; 132 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 133 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 134 adev->vcn.indirect_sram = true; 135 break; 136 case IP_VERSION(3, 0, 0): 137 case IP_VERSION(3, 0, 64): 138 case IP_VERSION(3, 0, 192): 139 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 140 fw_name = FIRMWARE_SIENNA_CICHLID; 141 else 142 fw_name = FIRMWARE_NAVY_FLOUNDER; 143 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 144 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 145 adev->vcn.indirect_sram = true; 146 break; 147 case IP_VERSION(3, 0, 2): 148 fw_name = FIRMWARE_VANGOGH; 149 break; 150 case IP_VERSION(3, 0, 16): 151 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 152 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 153 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 154 adev->vcn.indirect_sram = true; 155 break; 156 case IP_VERSION(3, 0, 33): 157 fw_name = FIRMWARE_BEIGE_GOBY; 158 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 159 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 160 adev->vcn.indirect_sram = true; 161 break; 162 case IP_VERSION(3, 1, 1): 163 fw_name = FIRMWARE_YELLOW_CARP; 164 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 165 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 166 adev->vcn.indirect_sram = true; 167 break; 168 default: 169 return -EINVAL; 170 } 171 172 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 173 if (r) { 174 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 175 fw_name); 176 return r; 177 } 178 179 r = amdgpu_ucode_validate(adev->vcn.fw); 180 if (r) { 181 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 182 fw_name); 183 release_firmware(adev->vcn.fw); 184 adev->vcn.fw = NULL; 185 return r; 186 } 187 188 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 189 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 190 191 /* Bit 20-23, it is encode major and non-zero for new naming convention. 192 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 193 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 194 * is zero in old naming convention, this field is always zero so far. 195 * These four bits are used to tell which naming convention is present. 196 */ 197 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 198 if (fw_check) { 199 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 200 201 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 202 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 203 enc_major = fw_check; 204 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 205 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 206 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 207 enc_major, enc_minor, dec_ver, vep, fw_rev); 208 } else { 209 unsigned int version_major, version_minor, family_id; 210 211 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 212 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 213 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 214 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 215 version_major, version_minor, family_id); 216 } 217 218 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 219 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 220 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 221 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 222 223 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 224 if (adev->vcn.harvest_config & (1 << i)) 225 continue; 226 227 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 228 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 229 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 230 if (r) { 231 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 232 return r; 233 } 234 235 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr + 236 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 237 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr + 238 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 239 240 if (adev->vcn.indirect_sram) { 241 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 242 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 243 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 244 if (r) { 245 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 246 return r; 247 } 248 } 249 } 250 251 return 0; 252 } 253 254 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 255 { 256 int i, j; 257 258 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 259 if (adev->vcn.harvest_config & (1 << j)) 260 continue; 261 262 if (adev->vcn.indirect_sram) { 263 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 264 &adev->vcn.inst[j].dpg_sram_gpu_addr, 265 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 266 } 267 kvfree(adev->vcn.inst[j].saved_bo); 268 269 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 270 &adev->vcn.inst[j].gpu_addr, 271 (void **)&adev->vcn.inst[j].cpu_addr); 272 273 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 274 275 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 276 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 277 } 278 279 release_firmware(adev->vcn.fw); 280 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 281 mutex_destroy(&adev->vcn.vcn_pg_lock); 282 283 return 0; 284 } 285 286 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 287 { 288 bool ret = false; 289 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 290 291 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 292 ret = true; 293 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) { 294 ret = true; 295 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 296 ret = true; 297 } 298 299 return ret; 300 } 301 302 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 303 { 304 unsigned size; 305 void *ptr; 306 int i, idx; 307 308 cancel_delayed_work_sync(&adev->vcn.idle_work); 309 310 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 311 if (adev->vcn.harvest_config & (1 << i)) 312 continue; 313 if (adev->vcn.inst[i].vcpu_bo == NULL) 314 return 0; 315 316 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 317 ptr = adev->vcn.inst[i].cpu_addr; 318 319 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 320 if (!adev->vcn.inst[i].saved_bo) 321 return -ENOMEM; 322 323 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 324 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 325 drm_dev_exit(idx); 326 } 327 } 328 return 0; 329 } 330 331 int amdgpu_vcn_resume(struct amdgpu_device *adev) 332 { 333 unsigned size; 334 void *ptr; 335 int i, idx; 336 337 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 338 if (adev->vcn.harvest_config & (1 << i)) 339 continue; 340 if (adev->vcn.inst[i].vcpu_bo == NULL) 341 return -EINVAL; 342 343 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 344 ptr = adev->vcn.inst[i].cpu_addr; 345 346 if (adev->vcn.inst[i].saved_bo != NULL) { 347 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 348 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 349 drm_dev_exit(idx); 350 } 351 kvfree(adev->vcn.inst[i].saved_bo); 352 adev->vcn.inst[i].saved_bo = NULL; 353 } else { 354 const struct common_firmware_header *hdr; 355 unsigned offset; 356 357 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 358 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 359 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 360 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 361 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 362 le32_to_cpu(hdr->ucode_size_bytes)); 363 drm_dev_exit(idx); 364 } 365 size -= le32_to_cpu(hdr->ucode_size_bytes); 366 ptr += le32_to_cpu(hdr->ucode_size_bytes); 367 } 368 memset_io(ptr, 0, size); 369 } 370 } 371 return 0; 372 } 373 374 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 375 { 376 struct amdgpu_device *adev = 377 container_of(work, struct amdgpu_device, vcn.idle_work.work); 378 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 379 unsigned int i, j; 380 int r = 0; 381 382 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 383 if (adev->vcn.harvest_config & (1 << j)) 384 continue; 385 386 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 387 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 388 } 389 390 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 391 struct dpg_pause_state new_state; 392 393 if (fence[j] || 394 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 395 new_state.fw_based = VCN_DPG_STATE__PAUSE; 396 else 397 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 398 399 adev->vcn.pause_dpg_mode(adev, j, &new_state); 400 } 401 402 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 403 fences += fence[j]; 404 } 405 406 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 407 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 408 AMD_PG_STATE_GATE); 409 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 410 false); 411 if (r) 412 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 413 } else { 414 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 415 } 416 } 417 418 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 419 { 420 struct amdgpu_device *adev = ring->adev; 421 int r = 0; 422 423 atomic_inc(&adev->vcn.total_submission_cnt); 424 425 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 426 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 427 true); 428 if (r) 429 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 430 } 431 432 mutex_lock(&adev->vcn.vcn_pg_lock); 433 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 434 AMD_PG_STATE_UNGATE); 435 436 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 437 struct dpg_pause_state new_state; 438 439 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 440 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 441 new_state.fw_based = VCN_DPG_STATE__PAUSE; 442 } else { 443 unsigned int fences = 0; 444 unsigned int i; 445 446 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 447 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 448 449 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 450 new_state.fw_based = VCN_DPG_STATE__PAUSE; 451 else 452 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 453 } 454 455 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 456 } 457 mutex_unlock(&adev->vcn.vcn_pg_lock); 458 } 459 460 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 461 { 462 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 463 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 464 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 465 466 atomic_dec(&ring->adev->vcn.total_submission_cnt); 467 468 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 469 } 470 471 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 472 { 473 struct amdgpu_device *adev = ring->adev; 474 uint32_t tmp = 0; 475 unsigned i; 476 int r; 477 478 /* VCN in SRIOV does not support direct register read/write */ 479 if (amdgpu_sriov_vf(adev)) 480 return 0; 481 482 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 483 r = amdgpu_ring_alloc(ring, 3); 484 if (r) 485 return r; 486 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 487 amdgpu_ring_write(ring, 0xDEADBEEF); 488 amdgpu_ring_commit(ring); 489 for (i = 0; i < adev->usec_timeout; i++) { 490 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 491 if (tmp == 0xDEADBEEF) 492 break; 493 udelay(1); 494 } 495 496 if (i >= adev->usec_timeout) 497 r = -ETIMEDOUT; 498 499 return r; 500 } 501 502 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 503 { 504 struct amdgpu_device *adev = ring->adev; 505 uint32_t rptr; 506 unsigned int i; 507 int r; 508 509 if (amdgpu_sriov_vf(adev)) 510 return 0; 511 512 r = amdgpu_ring_alloc(ring, 16); 513 if (r) 514 return r; 515 516 rptr = amdgpu_ring_get_rptr(ring); 517 518 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 519 amdgpu_ring_commit(ring); 520 521 for (i = 0; i < adev->usec_timeout; i++) { 522 if (amdgpu_ring_get_rptr(ring) != rptr) 523 break; 524 udelay(1); 525 } 526 527 if (i >= adev->usec_timeout) 528 r = -ETIMEDOUT; 529 530 return r; 531 } 532 533 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 534 struct amdgpu_ib *ib_msg, 535 struct dma_fence **fence) 536 { 537 struct amdgpu_device *adev = ring->adev; 538 struct dma_fence *f = NULL; 539 struct amdgpu_job *job; 540 struct amdgpu_ib *ib; 541 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 542 int i, r; 543 544 r = amdgpu_job_alloc_with_ib(adev, 64, 545 AMDGPU_IB_POOL_DIRECT, &job); 546 if (r) 547 goto err; 548 549 ib = &job->ibs[0]; 550 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 551 ib->ptr[1] = addr; 552 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 553 ib->ptr[3] = addr >> 32; 554 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 555 ib->ptr[5] = 0; 556 for (i = 6; i < 16; i += 2) { 557 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 558 ib->ptr[i+1] = 0; 559 } 560 ib->length_dw = 16; 561 562 r = amdgpu_job_submit_direct(job, ring, &f); 563 if (r) 564 goto err_free; 565 566 amdgpu_ib_free(adev, ib_msg, f); 567 568 if (fence) 569 *fence = dma_fence_get(f); 570 dma_fence_put(f); 571 572 return 0; 573 574 err_free: 575 amdgpu_job_free(job); 576 err: 577 amdgpu_ib_free(adev, ib_msg, f); 578 return r; 579 } 580 581 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 582 struct amdgpu_ib *ib) 583 { 584 struct amdgpu_device *adev = ring->adev; 585 uint32_t *msg; 586 int r, i; 587 588 memset(ib, 0, sizeof(*ib)); 589 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 590 AMDGPU_IB_POOL_DIRECT, 591 ib); 592 if (r) 593 return r; 594 595 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 596 msg[0] = cpu_to_le32(0x00000028); 597 msg[1] = cpu_to_le32(0x00000038); 598 msg[2] = cpu_to_le32(0x00000001); 599 msg[3] = cpu_to_le32(0x00000000); 600 msg[4] = cpu_to_le32(handle); 601 msg[5] = cpu_to_le32(0x00000000); 602 msg[6] = cpu_to_le32(0x00000001); 603 msg[7] = cpu_to_le32(0x00000028); 604 msg[8] = cpu_to_le32(0x00000010); 605 msg[9] = cpu_to_le32(0x00000000); 606 msg[10] = cpu_to_le32(0x00000007); 607 msg[11] = cpu_to_le32(0x00000000); 608 msg[12] = cpu_to_le32(0x00000780); 609 msg[13] = cpu_to_le32(0x00000440); 610 for (i = 14; i < 1024; ++i) 611 msg[i] = cpu_to_le32(0x0); 612 613 return 0; 614 } 615 616 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 617 struct amdgpu_ib *ib) 618 { 619 struct amdgpu_device *adev = ring->adev; 620 uint32_t *msg; 621 int r, i; 622 623 memset(ib, 0, sizeof(*ib)); 624 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 625 AMDGPU_IB_POOL_DIRECT, 626 ib); 627 if (r) 628 return r; 629 630 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 631 msg[0] = cpu_to_le32(0x00000028); 632 msg[1] = cpu_to_le32(0x00000018); 633 msg[2] = cpu_to_le32(0x00000000); 634 msg[3] = cpu_to_le32(0x00000002); 635 msg[4] = cpu_to_le32(handle); 636 msg[5] = cpu_to_le32(0x00000000); 637 for (i = 6; i < 1024; ++i) 638 msg[i] = cpu_to_le32(0x0); 639 640 return 0; 641 } 642 643 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 644 { 645 struct dma_fence *fence = NULL; 646 struct amdgpu_ib ib; 647 long r; 648 649 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 650 if (r) 651 goto error; 652 653 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 654 if (r) 655 goto error; 656 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 657 if (r) 658 goto error; 659 660 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 661 if (r) 662 goto error; 663 664 r = dma_fence_wait_timeout(fence, false, timeout); 665 if (r == 0) 666 r = -ETIMEDOUT; 667 else if (r > 0) 668 r = 0; 669 670 dma_fence_put(fence); 671 error: 672 return r; 673 } 674 675 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 676 struct amdgpu_ib *ib_msg, 677 struct dma_fence **fence) 678 { 679 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 680 const unsigned int ib_size_dw = 64; 681 struct amdgpu_device *adev = ring->adev; 682 struct dma_fence *f = NULL; 683 struct amdgpu_job *job; 684 struct amdgpu_ib *ib; 685 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 686 int i, r; 687 688 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 689 AMDGPU_IB_POOL_DIRECT, &job); 690 if (r) 691 goto err; 692 693 ib = &job->ibs[0]; 694 ib->length_dw = 0; 695 696 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 697 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 698 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 699 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 700 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 701 702 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 703 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 704 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 705 706 for (i = ib->length_dw; i < ib_size_dw; ++i) 707 ib->ptr[i] = 0x0; 708 709 r = amdgpu_job_submit_direct(job, ring, &f); 710 if (r) 711 goto err_free; 712 713 amdgpu_ib_free(adev, ib_msg, f); 714 715 if (fence) 716 *fence = dma_fence_get(f); 717 dma_fence_put(f); 718 719 return 0; 720 721 err_free: 722 amdgpu_job_free(job); 723 err: 724 amdgpu_ib_free(adev, ib_msg, f); 725 return r; 726 } 727 728 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 729 { 730 struct dma_fence *fence = NULL; 731 struct amdgpu_ib ib; 732 long r; 733 734 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 735 if (r) 736 goto error; 737 738 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 739 if (r) 740 goto error; 741 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 742 if (r) 743 goto error; 744 745 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 746 if (r) 747 goto error; 748 749 r = dma_fence_wait_timeout(fence, false, timeout); 750 if (r == 0) 751 r = -ETIMEDOUT; 752 else if (r > 0) 753 r = 0; 754 755 dma_fence_put(fence); 756 error: 757 return r; 758 } 759 760 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 761 { 762 struct amdgpu_device *adev = ring->adev; 763 uint32_t rptr; 764 unsigned i; 765 int r; 766 767 if (amdgpu_sriov_vf(adev)) 768 return 0; 769 770 r = amdgpu_ring_alloc(ring, 16); 771 if (r) 772 return r; 773 774 rptr = amdgpu_ring_get_rptr(ring); 775 776 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 777 amdgpu_ring_commit(ring); 778 779 for (i = 0; i < adev->usec_timeout; i++) { 780 if (amdgpu_ring_get_rptr(ring) != rptr) 781 break; 782 udelay(1); 783 } 784 785 if (i >= adev->usec_timeout) 786 r = -ETIMEDOUT; 787 788 return r; 789 } 790 791 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 792 struct amdgpu_ib *ib_msg, 793 struct dma_fence **fence) 794 { 795 const unsigned ib_size_dw = 16; 796 struct amdgpu_job *job; 797 struct amdgpu_ib *ib; 798 struct dma_fence *f = NULL; 799 uint64_t addr; 800 int i, r; 801 802 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 803 AMDGPU_IB_POOL_DIRECT, &job); 804 if (r) 805 return r; 806 807 ib = &job->ibs[0]; 808 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 809 810 ib->length_dw = 0; 811 ib->ptr[ib->length_dw++] = 0x00000018; 812 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 813 ib->ptr[ib->length_dw++] = handle; 814 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 815 ib->ptr[ib->length_dw++] = addr; 816 ib->ptr[ib->length_dw++] = 0x0000000b; 817 818 ib->ptr[ib->length_dw++] = 0x00000014; 819 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 820 ib->ptr[ib->length_dw++] = 0x0000001c; 821 ib->ptr[ib->length_dw++] = 0x00000000; 822 ib->ptr[ib->length_dw++] = 0x00000000; 823 824 ib->ptr[ib->length_dw++] = 0x00000008; 825 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 826 827 for (i = ib->length_dw; i < ib_size_dw; ++i) 828 ib->ptr[i] = 0x0; 829 830 r = amdgpu_job_submit_direct(job, ring, &f); 831 if (r) 832 goto err; 833 834 if (fence) 835 *fence = dma_fence_get(f); 836 dma_fence_put(f); 837 838 return 0; 839 840 err: 841 amdgpu_job_free(job); 842 return r; 843 } 844 845 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 846 struct amdgpu_ib *ib_msg, 847 struct dma_fence **fence) 848 { 849 const unsigned ib_size_dw = 16; 850 struct amdgpu_job *job; 851 struct amdgpu_ib *ib; 852 struct dma_fence *f = NULL; 853 uint64_t addr; 854 int i, r; 855 856 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 857 AMDGPU_IB_POOL_DIRECT, &job); 858 if (r) 859 return r; 860 861 ib = &job->ibs[0]; 862 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 863 864 ib->length_dw = 0; 865 ib->ptr[ib->length_dw++] = 0x00000018; 866 ib->ptr[ib->length_dw++] = 0x00000001; 867 ib->ptr[ib->length_dw++] = handle; 868 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 869 ib->ptr[ib->length_dw++] = addr; 870 ib->ptr[ib->length_dw++] = 0x0000000b; 871 872 ib->ptr[ib->length_dw++] = 0x00000014; 873 ib->ptr[ib->length_dw++] = 0x00000002; 874 ib->ptr[ib->length_dw++] = 0x0000001c; 875 ib->ptr[ib->length_dw++] = 0x00000000; 876 ib->ptr[ib->length_dw++] = 0x00000000; 877 878 ib->ptr[ib->length_dw++] = 0x00000008; 879 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 880 881 for (i = ib->length_dw; i < ib_size_dw; ++i) 882 ib->ptr[i] = 0x0; 883 884 r = amdgpu_job_submit_direct(job, ring, &f); 885 if (r) 886 goto err; 887 888 if (fence) 889 *fence = dma_fence_get(f); 890 dma_fence_put(f); 891 892 return 0; 893 894 err: 895 amdgpu_job_free(job); 896 return r; 897 } 898 899 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 900 { 901 struct amdgpu_device *adev = ring->adev; 902 struct dma_fence *fence = NULL; 903 struct amdgpu_ib ib; 904 long r; 905 906 memset(&ib, 0, sizeof(ib)); 907 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 908 AMDGPU_IB_POOL_DIRECT, 909 &ib); 910 if (r) 911 return r; 912 913 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 914 if (r) 915 goto error; 916 917 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 918 if (r) 919 goto error; 920 921 r = dma_fence_wait_timeout(fence, false, timeout); 922 if (r == 0) 923 r = -ETIMEDOUT; 924 else if (r > 0) 925 r = 0; 926 927 error: 928 amdgpu_ib_free(adev, &ib, fence); 929 dma_fence_put(fence); 930 931 return r; 932 } 933 934 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 935 { 936 switch(ring) { 937 case 0: 938 return AMDGPU_RING_PRIO_0; 939 case 1: 940 return AMDGPU_RING_PRIO_1; 941 case 2: 942 return AMDGPU_RING_PRIO_2; 943 default: 944 return AMDGPU_RING_PRIO_0; 945 } 946 } 947 948 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 949 { 950 int i; 951 unsigned int idx; 952 953 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 954 const struct common_firmware_header *hdr; 955 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 956 957 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 958 if (adev->vcn.harvest_config & (1 << i)) 959 continue; 960 /* currently only support 2 FW instances */ 961 if (i >= 2) { 962 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 963 break; 964 } 965 idx = AMDGPU_UCODE_ID_VCN + i; 966 adev->firmware.ucode[idx].ucode_id = idx; 967 adev->firmware.ucode[idx].fw = adev->vcn.fw; 968 adev->firmware.fw_size += 969 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 970 } 971 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 972 } 973 } 974