1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/debugfs.h> 31 #include <drm/drm_drv.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_pm.h" 35 #include "amdgpu_vcn.h" 36 #include "soc15d.h" 37 38 /* Firmware Names */ 39 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 40 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 41 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 42 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 43 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 44 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 45 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 46 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 47 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 48 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 49 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 50 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 51 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 52 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 53 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 54 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 55 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 56 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 57 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 58 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 59 60 MODULE_FIRMWARE(FIRMWARE_RAVEN); 61 MODULE_FIRMWARE(FIRMWARE_PICASSO); 62 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 63 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 64 MODULE_FIRMWARE(FIRMWARE_RENOIR); 65 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 66 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 67 MODULE_FIRMWARE(FIRMWARE_NAVI10); 68 MODULE_FIRMWARE(FIRMWARE_NAVI14); 69 MODULE_FIRMWARE(FIRMWARE_NAVI12); 70 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 71 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 72 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 73 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 74 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 75 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 76 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 77 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 78 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 79 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 80 81 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 82 83 int amdgpu_vcn_early_init(struct amdgpu_device *adev) 84 { 85 char ucode_prefix[30]; 86 char fw_name[40]; 87 int r; 88 89 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 90 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 91 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name); 92 if (r) 93 amdgpu_ucode_release(&adev->vcn.fw); 94 95 return r; 96 } 97 98 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 99 { 100 unsigned long bo_size; 101 const struct common_firmware_header *hdr; 102 unsigned char fw_check; 103 unsigned int fw_shared_size, log_offset; 104 int i, r; 105 106 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 107 mutex_init(&adev->vcn.vcn_pg_lock); 108 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 109 atomic_set(&adev->vcn.total_submission_cnt, 0); 110 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 111 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 112 113 switch (adev->ip_versions[UVD_HWIP][0]) { 114 case IP_VERSION(1, 0, 0): 115 case IP_VERSION(1, 0, 1): 116 case IP_VERSION(2, 5, 0): 117 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 118 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 119 adev->vcn.indirect_sram = true; 120 break; 121 case IP_VERSION(2, 2, 0): 122 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 123 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 124 adev->vcn.indirect_sram = true; 125 break; 126 case IP_VERSION(2, 6, 0): 127 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 128 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 129 adev->vcn.indirect_sram = true; 130 break; 131 case IP_VERSION(2, 0, 0): 132 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 133 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 134 adev->vcn.indirect_sram = true; 135 break; 136 case IP_VERSION(2, 0, 2): 137 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 138 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 139 adev->vcn.indirect_sram = true; 140 break; 141 case IP_VERSION(3, 0, 0): 142 case IP_VERSION(3, 0, 64): 143 case IP_VERSION(3, 0, 192): 144 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 145 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 146 adev->vcn.indirect_sram = true; 147 break; 148 case IP_VERSION(3, 0, 2): 149 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 150 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 151 adev->vcn.indirect_sram = true; 152 break; 153 case IP_VERSION(3, 0, 16): 154 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 155 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 156 adev->vcn.indirect_sram = true; 157 break; 158 case IP_VERSION(3, 0, 33): 159 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 160 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 161 adev->vcn.indirect_sram = true; 162 break; 163 case IP_VERSION(3, 1, 1): 164 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 165 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 166 adev->vcn.indirect_sram = true; 167 break; 168 case IP_VERSION(3, 1, 2): 169 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 170 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 171 adev->vcn.indirect_sram = true; 172 break; 173 case IP_VERSION(4, 0, 0): 174 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 175 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 176 adev->vcn.indirect_sram = true; 177 break; 178 case IP_VERSION(4, 0, 2): 179 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 180 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 181 adev->vcn.indirect_sram = true; 182 break; 183 case IP_VERSION(4, 0, 4): 184 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 185 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 186 adev->vcn.indirect_sram = true; 187 break; 188 default: 189 return -EINVAL; 190 } 191 192 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 193 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 194 195 /* Bit 20-23, it is encode major and non-zero for new naming convention. 196 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 197 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 198 * is zero in old naming convention, this field is always zero so far. 199 * These four bits are used to tell which naming convention is present. 200 */ 201 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 202 if (fw_check) { 203 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 204 205 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 206 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 207 enc_major = fw_check; 208 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 209 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 210 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 211 enc_major, enc_minor, dec_ver, vep, fw_rev); 212 } else { 213 unsigned int version_major, version_minor, family_id; 214 215 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 216 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 217 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 218 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 219 version_major, version_minor, family_id); 220 } 221 222 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 223 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 224 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 225 226 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){ 227 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 228 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 229 } else { 230 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 231 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 232 } 233 234 bo_size += fw_shared_size; 235 236 if (amdgpu_vcnfw_log) 237 bo_size += AMDGPU_VCNFW_LOG_SIZE; 238 239 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 240 if (adev->vcn.harvest_config & (1 << i)) 241 continue; 242 243 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 244 AMDGPU_GEM_DOMAIN_VRAM | 245 AMDGPU_GEM_DOMAIN_GTT, 246 &adev->vcn.inst[i].vcpu_bo, 247 &adev->vcn.inst[i].gpu_addr, 248 &adev->vcn.inst[i].cpu_addr); 249 if (r) { 250 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 251 return r; 252 } 253 254 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 255 bo_size - fw_shared_size; 256 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 257 bo_size - fw_shared_size; 258 259 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 260 261 if (amdgpu_vcnfw_log) { 262 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 263 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 264 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 265 } 266 267 if (adev->vcn.indirect_sram) { 268 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 269 AMDGPU_GEM_DOMAIN_VRAM | 270 AMDGPU_GEM_DOMAIN_GTT, 271 &adev->vcn.inst[i].dpg_sram_bo, 272 &adev->vcn.inst[i].dpg_sram_gpu_addr, 273 &adev->vcn.inst[i].dpg_sram_cpu_addr); 274 if (r) { 275 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 276 return r; 277 } 278 } 279 } 280 281 return 0; 282 } 283 284 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 285 { 286 int i, j; 287 288 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 289 if (adev->vcn.harvest_config & (1 << j)) 290 continue; 291 292 if (adev->vcn.indirect_sram) { 293 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 294 &adev->vcn.inst[j].dpg_sram_gpu_addr, 295 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 296 } 297 kvfree(adev->vcn.inst[j].saved_bo); 298 299 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 300 &adev->vcn.inst[j].gpu_addr, 301 (void **)&adev->vcn.inst[j].cpu_addr); 302 303 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 304 305 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 306 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 307 } 308 309 amdgpu_ucode_release(&adev->vcn.fw); 310 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 311 mutex_destroy(&adev->vcn.vcn_pg_lock); 312 313 return 0; 314 } 315 316 /* from vcn4 and above, only unified queue is used */ 317 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) 318 { 319 struct amdgpu_device *adev = ring->adev; 320 bool ret = false; 321 322 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)) 323 ret = true; 324 325 return ret; 326 } 327 328 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 329 { 330 bool ret = false; 331 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 332 333 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 334 ret = true; 335 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) { 336 ret = true; 337 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 338 ret = true; 339 } 340 341 return ret; 342 } 343 344 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 345 { 346 unsigned size; 347 void *ptr; 348 int i, idx; 349 350 cancel_delayed_work_sync(&adev->vcn.idle_work); 351 352 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 353 if (adev->vcn.harvest_config & (1 << i)) 354 continue; 355 if (adev->vcn.inst[i].vcpu_bo == NULL) 356 return 0; 357 358 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 359 ptr = adev->vcn.inst[i].cpu_addr; 360 361 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 362 if (!adev->vcn.inst[i].saved_bo) 363 return -ENOMEM; 364 365 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 366 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 367 drm_dev_exit(idx); 368 } 369 } 370 return 0; 371 } 372 373 int amdgpu_vcn_resume(struct amdgpu_device *adev) 374 { 375 unsigned size; 376 void *ptr; 377 int i, idx; 378 379 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 380 if (adev->vcn.harvest_config & (1 << i)) 381 continue; 382 if (adev->vcn.inst[i].vcpu_bo == NULL) 383 return -EINVAL; 384 385 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 386 ptr = adev->vcn.inst[i].cpu_addr; 387 388 if (adev->vcn.inst[i].saved_bo != NULL) { 389 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 390 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 391 drm_dev_exit(idx); 392 } 393 kvfree(adev->vcn.inst[i].saved_bo); 394 adev->vcn.inst[i].saved_bo = NULL; 395 } else { 396 const struct common_firmware_header *hdr; 397 unsigned offset; 398 399 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 400 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 401 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 402 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 403 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 404 le32_to_cpu(hdr->ucode_size_bytes)); 405 drm_dev_exit(idx); 406 } 407 size -= le32_to_cpu(hdr->ucode_size_bytes); 408 ptr += le32_to_cpu(hdr->ucode_size_bytes); 409 } 410 memset_io(ptr, 0, size); 411 } 412 } 413 return 0; 414 } 415 416 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 417 { 418 struct amdgpu_device *adev = 419 container_of(work, struct amdgpu_device, vcn.idle_work.work); 420 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 421 unsigned int i, j; 422 int r = 0; 423 424 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 425 if (adev->vcn.harvest_config & (1 << j)) 426 continue; 427 428 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 429 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 430 } 431 432 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 433 struct dpg_pause_state new_state; 434 435 if (fence[j] || 436 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 437 new_state.fw_based = VCN_DPG_STATE__PAUSE; 438 else 439 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 440 441 adev->vcn.pause_dpg_mode(adev, j, &new_state); 442 } 443 444 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 445 fences += fence[j]; 446 } 447 448 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 449 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 450 AMD_PG_STATE_GATE); 451 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 452 false); 453 if (r) 454 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 455 } else { 456 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 457 } 458 } 459 460 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 461 { 462 struct amdgpu_device *adev = ring->adev; 463 int r = 0; 464 465 atomic_inc(&adev->vcn.total_submission_cnt); 466 467 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 468 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 469 true); 470 if (r) 471 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 472 } 473 474 mutex_lock(&adev->vcn.vcn_pg_lock); 475 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 476 AMD_PG_STATE_UNGATE); 477 478 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 479 struct dpg_pause_state new_state; 480 481 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 482 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 483 new_state.fw_based = VCN_DPG_STATE__PAUSE; 484 } else { 485 unsigned int fences = 0; 486 unsigned int i; 487 488 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 489 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 490 491 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 492 new_state.fw_based = VCN_DPG_STATE__PAUSE; 493 else 494 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 495 } 496 497 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 498 } 499 mutex_unlock(&adev->vcn.vcn_pg_lock); 500 } 501 502 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 503 { 504 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 505 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 506 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 507 508 atomic_dec(&ring->adev->vcn.total_submission_cnt); 509 510 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 511 } 512 513 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 514 { 515 struct amdgpu_device *adev = ring->adev; 516 uint32_t tmp = 0; 517 unsigned i; 518 int r; 519 520 /* VCN in SRIOV does not support direct register read/write */ 521 if (amdgpu_sriov_vf(adev)) 522 return 0; 523 524 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 525 r = amdgpu_ring_alloc(ring, 3); 526 if (r) 527 return r; 528 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 529 amdgpu_ring_write(ring, 0xDEADBEEF); 530 amdgpu_ring_commit(ring); 531 for (i = 0; i < adev->usec_timeout; i++) { 532 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 533 if (tmp == 0xDEADBEEF) 534 break; 535 udelay(1); 536 } 537 538 if (i >= adev->usec_timeout) 539 r = -ETIMEDOUT; 540 541 return r; 542 } 543 544 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 545 { 546 struct amdgpu_device *adev = ring->adev; 547 uint32_t rptr; 548 unsigned int i; 549 int r; 550 551 if (amdgpu_sriov_vf(adev)) 552 return 0; 553 554 r = amdgpu_ring_alloc(ring, 16); 555 if (r) 556 return r; 557 558 rptr = amdgpu_ring_get_rptr(ring); 559 560 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 561 amdgpu_ring_commit(ring); 562 563 for (i = 0; i < adev->usec_timeout; i++) { 564 if (amdgpu_ring_get_rptr(ring) != rptr) 565 break; 566 udelay(1); 567 } 568 569 if (i >= adev->usec_timeout) 570 r = -ETIMEDOUT; 571 572 return r; 573 } 574 575 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 576 struct amdgpu_ib *ib_msg, 577 struct dma_fence **fence) 578 { 579 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 580 struct amdgpu_device *adev = ring->adev; 581 struct dma_fence *f = NULL; 582 struct amdgpu_job *job; 583 struct amdgpu_ib *ib; 584 int i, r; 585 586 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 587 64, AMDGPU_IB_POOL_DIRECT, 588 &job); 589 if (r) 590 goto err; 591 592 ib = &job->ibs[0]; 593 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 594 ib->ptr[1] = addr; 595 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 596 ib->ptr[3] = addr >> 32; 597 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 598 ib->ptr[5] = 0; 599 for (i = 6; i < 16; i += 2) { 600 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 601 ib->ptr[i+1] = 0; 602 } 603 ib->length_dw = 16; 604 605 r = amdgpu_job_submit_direct(job, ring, &f); 606 if (r) 607 goto err_free; 608 609 amdgpu_ib_free(adev, ib_msg, f); 610 611 if (fence) 612 *fence = dma_fence_get(f); 613 dma_fence_put(f); 614 615 return 0; 616 617 err_free: 618 amdgpu_job_free(job); 619 err: 620 amdgpu_ib_free(adev, ib_msg, f); 621 return r; 622 } 623 624 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 625 struct amdgpu_ib *ib) 626 { 627 struct amdgpu_device *adev = ring->adev; 628 uint32_t *msg; 629 int r, i; 630 631 memset(ib, 0, sizeof(*ib)); 632 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 633 AMDGPU_IB_POOL_DIRECT, 634 ib); 635 if (r) 636 return r; 637 638 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 639 msg[0] = cpu_to_le32(0x00000028); 640 msg[1] = cpu_to_le32(0x00000038); 641 msg[2] = cpu_to_le32(0x00000001); 642 msg[3] = cpu_to_le32(0x00000000); 643 msg[4] = cpu_to_le32(handle); 644 msg[5] = cpu_to_le32(0x00000000); 645 msg[6] = cpu_to_le32(0x00000001); 646 msg[7] = cpu_to_le32(0x00000028); 647 msg[8] = cpu_to_le32(0x00000010); 648 msg[9] = cpu_to_le32(0x00000000); 649 msg[10] = cpu_to_le32(0x00000007); 650 msg[11] = cpu_to_le32(0x00000000); 651 msg[12] = cpu_to_le32(0x00000780); 652 msg[13] = cpu_to_le32(0x00000440); 653 for (i = 14; i < 1024; ++i) 654 msg[i] = cpu_to_le32(0x0); 655 656 return 0; 657 } 658 659 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 660 struct amdgpu_ib *ib) 661 { 662 struct amdgpu_device *adev = ring->adev; 663 uint32_t *msg; 664 int r, i; 665 666 memset(ib, 0, sizeof(*ib)); 667 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 668 AMDGPU_IB_POOL_DIRECT, 669 ib); 670 if (r) 671 return r; 672 673 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 674 msg[0] = cpu_to_le32(0x00000028); 675 msg[1] = cpu_to_le32(0x00000018); 676 msg[2] = cpu_to_le32(0x00000000); 677 msg[3] = cpu_to_le32(0x00000002); 678 msg[4] = cpu_to_le32(handle); 679 msg[5] = cpu_to_le32(0x00000000); 680 for (i = 6; i < 1024; ++i) 681 msg[i] = cpu_to_le32(0x0); 682 683 return 0; 684 } 685 686 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 687 { 688 struct dma_fence *fence = NULL; 689 struct amdgpu_ib ib; 690 long r; 691 692 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 693 if (r) 694 goto error; 695 696 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 697 if (r) 698 goto error; 699 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 700 if (r) 701 goto error; 702 703 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 704 if (r) 705 goto error; 706 707 r = dma_fence_wait_timeout(fence, false, timeout); 708 if (r == 0) 709 r = -ETIMEDOUT; 710 else if (r > 0) 711 r = 0; 712 713 dma_fence_put(fence); 714 error: 715 return r; 716 } 717 718 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 719 uint32_t ib_pack_in_dw, bool enc) 720 { 721 uint32_t *ib_checksum; 722 723 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 724 ib->ptr[ib->length_dw++] = 0x30000002; 725 ib_checksum = &ib->ptr[ib->length_dw++]; 726 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 727 728 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 729 ib->ptr[ib->length_dw++] = 0x30000001; 730 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 731 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 732 733 return ib_checksum; 734 } 735 736 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 737 uint32_t ib_pack_in_dw) 738 { 739 uint32_t i; 740 uint32_t checksum = 0; 741 742 for (i = 0; i < ib_pack_in_dw; i++) 743 checksum += *(*ib_checksum + 2 + i); 744 745 **ib_checksum = checksum; 746 } 747 748 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 749 struct amdgpu_ib *ib_msg, 750 struct dma_fence **fence) 751 { 752 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 753 unsigned int ib_size_dw = 64; 754 struct amdgpu_device *adev = ring->adev; 755 struct dma_fence *f = NULL; 756 struct amdgpu_job *job; 757 struct amdgpu_ib *ib; 758 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 759 bool sq = amdgpu_vcn_using_unified_queue(ring); 760 uint32_t *ib_checksum; 761 uint32_t ib_pack_in_dw; 762 int i, r; 763 764 if (sq) 765 ib_size_dw += 8; 766 767 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 768 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 769 &job); 770 if (r) 771 goto err; 772 773 ib = &job->ibs[0]; 774 ib->length_dw = 0; 775 776 /* single queue headers */ 777 if (sq) { 778 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 779 + 4 + 2; /* engine info + decoding ib in dw */ 780 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 781 } 782 783 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 784 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 785 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 786 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 787 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 788 789 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 790 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 791 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 792 793 for (i = ib->length_dw; i < ib_size_dw; ++i) 794 ib->ptr[i] = 0x0; 795 796 if (sq) 797 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 798 799 r = amdgpu_job_submit_direct(job, ring, &f); 800 if (r) 801 goto err_free; 802 803 amdgpu_ib_free(adev, ib_msg, f); 804 805 if (fence) 806 *fence = dma_fence_get(f); 807 dma_fence_put(f); 808 809 return 0; 810 811 err_free: 812 amdgpu_job_free(job); 813 err: 814 amdgpu_ib_free(adev, ib_msg, f); 815 return r; 816 } 817 818 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 819 { 820 struct dma_fence *fence = NULL; 821 struct amdgpu_ib ib; 822 long r; 823 824 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 825 if (r) 826 goto error; 827 828 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 829 if (r) 830 goto error; 831 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 832 if (r) 833 goto error; 834 835 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 836 if (r) 837 goto error; 838 839 r = dma_fence_wait_timeout(fence, false, timeout); 840 if (r == 0) 841 r = -ETIMEDOUT; 842 else if (r > 0) 843 r = 0; 844 845 dma_fence_put(fence); 846 error: 847 return r; 848 } 849 850 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 851 { 852 struct amdgpu_device *adev = ring->adev; 853 uint32_t rptr; 854 unsigned i; 855 int r; 856 857 if (amdgpu_sriov_vf(adev)) 858 return 0; 859 860 r = amdgpu_ring_alloc(ring, 16); 861 if (r) 862 return r; 863 864 rptr = amdgpu_ring_get_rptr(ring); 865 866 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 867 amdgpu_ring_commit(ring); 868 869 for (i = 0; i < adev->usec_timeout; i++) { 870 if (amdgpu_ring_get_rptr(ring) != rptr) 871 break; 872 udelay(1); 873 } 874 875 if (i >= adev->usec_timeout) 876 r = -ETIMEDOUT; 877 878 return r; 879 } 880 881 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 882 struct amdgpu_ib *ib_msg, 883 struct dma_fence **fence) 884 { 885 unsigned int ib_size_dw = 16; 886 struct amdgpu_job *job; 887 struct amdgpu_ib *ib; 888 struct dma_fence *f = NULL; 889 uint32_t *ib_checksum = NULL; 890 uint64_t addr; 891 bool sq = amdgpu_vcn_using_unified_queue(ring); 892 int i, r; 893 894 if (sq) 895 ib_size_dw += 8; 896 897 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 898 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 899 &job); 900 if (r) 901 return r; 902 903 ib = &job->ibs[0]; 904 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 905 906 ib->length_dw = 0; 907 908 if (sq) 909 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 910 911 ib->ptr[ib->length_dw++] = 0x00000018; 912 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 913 ib->ptr[ib->length_dw++] = handle; 914 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 915 ib->ptr[ib->length_dw++] = addr; 916 ib->ptr[ib->length_dw++] = 0x0000000b; 917 918 ib->ptr[ib->length_dw++] = 0x00000014; 919 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 920 ib->ptr[ib->length_dw++] = 0x0000001c; 921 ib->ptr[ib->length_dw++] = 0x00000000; 922 ib->ptr[ib->length_dw++] = 0x00000000; 923 924 ib->ptr[ib->length_dw++] = 0x00000008; 925 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 926 927 for (i = ib->length_dw; i < ib_size_dw; ++i) 928 ib->ptr[i] = 0x0; 929 930 if (sq) 931 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 932 933 r = amdgpu_job_submit_direct(job, ring, &f); 934 if (r) 935 goto err; 936 937 if (fence) 938 *fence = dma_fence_get(f); 939 dma_fence_put(f); 940 941 return 0; 942 943 err: 944 amdgpu_job_free(job); 945 return r; 946 } 947 948 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 949 struct amdgpu_ib *ib_msg, 950 struct dma_fence **fence) 951 { 952 unsigned int ib_size_dw = 16; 953 struct amdgpu_job *job; 954 struct amdgpu_ib *ib; 955 struct dma_fence *f = NULL; 956 uint32_t *ib_checksum = NULL; 957 uint64_t addr; 958 bool sq = amdgpu_vcn_using_unified_queue(ring); 959 int i, r; 960 961 if (sq) 962 ib_size_dw += 8; 963 964 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 965 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 966 &job); 967 if (r) 968 return r; 969 970 ib = &job->ibs[0]; 971 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 972 973 ib->length_dw = 0; 974 975 if (sq) 976 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 977 978 ib->ptr[ib->length_dw++] = 0x00000018; 979 ib->ptr[ib->length_dw++] = 0x00000001; 980 ib->ptr[ib->length_dw++] = handle; 981 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 982 ib->ptr[ib->length_dw++] = addr; 983 ib->ptr[ib->length_dw++] = 0x0000000b; 984 985 ib->ptr[ib->length_dw++] = 0x00000014; 986 ib->ptr[ib->length_dw++] = 0x00000002; 987 ib->ptr[ib->length_dw++] = 0x0000001c; 988 ib->ptr[ib->length_dw++] = 0x00000000; 989 ib->ptr[ib->length_dw++] = 0x00000000; 990 991 ib->ptr[ib->length_dw++] = 0x00000008; 992 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 993 994 for (i = ib->length_dw; i < ib_size_dw; ++i) 995 ib->ptr[i] = 0x0; 996 997 if (sq) 998 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 999 1000 r = amdgpu_job_submit_direct(job, ring, &f); 1001 if (r) 1002 goto err; 1003 1004 if (fence) 1005 *fence = dma_fence_get(f); 1006 dma_fence_put(f); 1007 1008 return 0; 1009 1010 err: 1011 amdgpu_job_free(job); 1012 return r; 1013 } 1014 1015 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1016 { 1017 struct amdgpu_device *adev = ring->adev; 1018 struct dma_fence *fence = NULL; 1019 struct amdgpu_ib ib; 1020 long r; 1021 1022 memset(&ib, 0, sizeof(ib)); 1023 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 1024 AMDGPU_IB_POOL_DIRECT, 1025 &ib); 1026 if (r) 1027 return r; 1028 1029 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 1030 if (r) 1031 goto error; 1032 1033 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 1034 if (r) 1035 goto error; 1036 1037 r = dma_fence_wait_timeout(fence, false, timeout); 1038 if (r == 0) 1039 r = -ETIMEDOUT; 1040 else if (r > 0) 1041 r = 0; 1042 1043 error: 1044 amdgpu_ib_free(adev, &ib, fence); 1045 dma_fence_put(fence); 1046 1047 return r; 1048 } 1049 1050 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1051 { 1052 long r; 1053 1054 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1055 if (r) 1056 goto error; 1057 1058 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1059 1060 error: 1061 return r; 1062 } 1063 1064 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1065 { 1066 switch(ring) { 1067 case 0: 1068 return AMDGPU_RING_PRIO_0; 1069 case 1: 1070 return AMDGPU_RING_PRIO_1; 1071 case 2: 1072 return AMDGPU_RING_PRIO_2; 1073 default: 1074 return AMDGPU_RING_PRIO_0; 1075 } 1076 } 1077 1078 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 1079 { 1080 int i; 1081 unsigned int idx; 1082 1083 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1084 const struct common_firmware_header *hdr; 1085 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 1086 1087 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1088 if (adev->vcn.harvest_config & (1 << i)) 1089 continue; 1090 /* currently only support 2 FW instances */ 1091 if (i >= 2) { 1092 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1093 break; 1094 } 1095 idx = AMDGPU_UCODE_ID_VCN + i; 1096 adev->firmware.ucode[idx].ucode_id = idx; 1097 adev->firmware.ucode[idx].fw = adev->vcn.fw; 1098 adev->firmware.fw_size += 1099 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1100 } 1101 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 1102 } 1103 } 1104 1105 /* 1106 * debugfs for mapping vcn firmware log buffer. 1107 */ 1108 #if defined(CONFIG_DEBUG_FS) 1109 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1110 size_t size, loff_t *pos) 1111 { 1112 struct amdgpu_vcn_inst *vcn; 1113 void *log_buf; 1114 volatile struct amdgpu_vcn_fwlog *plog; 1115 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1116 unsigned int read_num[2] = {0}; 1117 1118 vcn = file_inode(f)->i_private; 1119 if (!vcn) 1120 return -ENODEV; 1121 1122 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1123 return -EFAULT; 1124 1125 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1126 1127 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1128 read_pos = plog->rptr; 1129 write_pos = plog->wptr; 1130 1131 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1132 return -EFAULT; 1133 1134 if (!size || (read_pos == write_pos)) 1135 return 0; 1136 1137 if (write_pos > read_pos) { 1138 available = write_pos - read_pos; 1139 read_num[0] = min(size, (size_t)available); 1140 } else { 1141 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1142 available = read_num[0] + write_pos - plog->header_size; 1143 if (size > available) 1144 read_num[1] = write_pos - plog->header_size; 1145 else if (size > read_num[0]) 1146 read_num[1] = size - read_num[0]; 1147 else 1148 read_num[0] = size; 1149 } 1150 1151 for (i = 0; i < 2; i++) { 1152 if (read_num[i]) { 1153 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1154 read_pos = plog->header_size; 1155 if (read_num[i] == copy_to_user((buf + read_bytes), 1156 (log_buf + read_pos), read_num[i])) 1157 return -EFAULT; 1158 1159 read_bytes += read_num[i]; 1160 read_pos += read_num[i]; 1161 } 1162 } 1163 1164 plog->rptr = read_pos; 1165 *pos += read_bytes; 1166 return read_bytes; 1167 } 1168 1169 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1170 .owner = THIS_MODULE, 1171 .read = amdgpu_debugfs_vcn_fwlog_read, 1172 .llseek = default_llseek 1173 }; 1174 #endif 1175 1176 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1177 struct amdgpu_vcn_inst *vcn) 1178 { 1179 #if defined(CONFIG_DEBUG_FS) 1180 struct drm_minor *minor = adev_to_drm(adev)->primary; 1181 struct dentry *root = minor->debugfs_root; 1182 char name[32]; 1183 1184 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1185 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn, 1186 &amdgpu_debugfs_vcnfwlog_fops, 1187 AMDGPU_VCNFW_LOG_SIZE); 1188 #endif 1189 } 1190 1191 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1192 { 1193 #if defined(CONFIG_DEBUG_FS) 1194 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1195 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1196 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1197 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1198 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1199 + vcn->fw_shared.log_offset; 1200 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1201 fw_log->is_enabled = 1; 1202 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1203 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1204 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1205 1206 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1207 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1208 log_buf->rptr = log_buf->header_size; 1209 log_buf->wptr = log_buf->header_size; 1210 log_buf->wrapped = 0; 1211 #endif 1212 } 1213 1214 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1215 struct amdgpu_irq_src *source, 1216 struct amdgpu_iv_entry *entry) 1217 { 1218 struct ras_common_if *ras_if = adev->vcn.ras_if; 1219 struct ras_dispatch_if ih_data = { 1220 .entry = entry, 1221 }; 1222 1223 if (!ras_if) 1224 return 0; 1225 1226 if (!amdgpu_sriov_vf(adev)) { 1227 ih_data.head = *ras_if; 1228 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1229 } else { 1230 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1231 adev->virt.ops->ras_poison_handler(adev); 1232 else 1233 dev_warn(adev->dev, 1234 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1235 } 1236 1237 return 0; 1238 } 1239 1240 void amdgpu_vcn_set_ras_funcs(struct amdgpu_device *adev) 1241 { 1242 if (!adev->vcn.ras) 1243 return; 1244 1245 amdgpu_ras_register_ras_block(adev, &adev->vcn.ras->ras_block); 1246 1247 strcpy(adev->vcn.ras->ras_block.ras_comm.name, "vcn"); 1248 adev->vcn.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1249 adev->vcn.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1250 adev->vcn.ras_if = &adev->vcn.ras->ras_block.ras_comm; 1251 1252 /* If don't define special ras_late_init function, use default ras_late_init */ 1253 if (!adev->vcn.ras->ras_block.ras_late_init) 1254 adev->vcn.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; 1255 } 1256