1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "soc15d.h" 38 39 /* Firmware Names */ 40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin" 60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 61 62 MODULE_FIRMWARE(FIRMWARE_RAVEN); 63 MODULE_FIRMWARE(FIRMWARE_PICASSO); 64 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 65 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 66 MODULE_FIRMWARE(FIRMWARE_RENOIR); 67 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 68 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 69 MODULE_FIRMWARE(FIRMWARE_NAVI10); 70 MODULE_FIRMWARE(FIRMWARE_NAVI14); 71 MODULE_FIRMWARE(FIRMWARE_NAVI12); 72 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 73 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 74 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 75 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 76 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 77 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 78 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 79 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 80 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 81 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3); 82 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 83 84 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 85 86 int amdgpu_vcn_early_init(struct amdgpu_device *adev) 87 { 88 char ucode_prefix[30]; 89 char fw_name[40]; 90 int r; 91 92 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 93 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 94 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name); 95 if (r) 96 amdgpu_ucode_release(&adev->vcn.fw); 97 98 return r; 99 } 100 101 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 102 { 103 unsigned long bo_size; 104 const struct common_firmware_header *hdr; 105 unsigned char fw_check; 106 unsigned int fw_shared_size, log_offset; 107 int i, r; 108 109 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 110 mutex_init(&adev->vcn.vcn_pg_lock); 111 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 112 atomic_set(&adev->vcn.total_submission_cnt, 0); 113 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 114 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 115 116 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 117 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 118 adev->vcn.indirect_sram = true; 119 120 /* 121 * Some Steam Deck's BIOS versions are incompatible with the 122 * indirect SRAM mode, leading to amdgpu being unable to get 123 * properly probed (and even potentially crashing the kernel). 124 * Hence, check for these versions here - notice this is 125 * restricted to Vangogh (Deck's APU). 126 */ 127 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 2)) { 128 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 129 130 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 131 !strncmp("F7A0114", bios_ver, 7))) { 132 adev->vcn.indirect_sram = false; 133 dev_info(adev->dev, 134 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 135 } 136 } 137 138 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 139 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 140 141 /* Bit 20-23, it is encode major and non-zero for new naming convention. 142 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 143 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 144 * is zero in old naming convention, this field is always zero so far. 145 * These four bits are used to tell which naming convention is present. 146 */ 147 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 148 if (fw_check) { 149 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 150 151 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 152 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 153 enc_major = fw_check; 154 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 155 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 156 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 157 enc_major, enc_minor, dec_ver, vep, fw_rev); 158 } else { 159 unsigned int version_major, version_minor, family_id; 160 161 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 162 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 163 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 164 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 165 version_major, version_minor, family_id); 166 } 167 168 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 169 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 170 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 171 172 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){ 173 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 174 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 175 } else { 176 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 177 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 178 } 179 180 bo_size += fw_shared_size; 181 182 if (amdgpu_vcnfw_log) 183 bo_size += AMDGPU_VCNFW_LOG_SIZE; 184 185 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 186 if (adev->vcn.harvest_config & (1 << i)) 187 continue; 188 189 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 190 AMDGPU_GEM_DOMAIN_VRAM | 191 AMDGPU_GEM_DOMAIN_GTT, 192 &adev->vcn.inst[i].vcpu_bo, 193 &adev->vcn.inst[i].gpu_addr, 194 &adev->vcn.inst[i].cpu_addr); 195 if (r) { 196 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 197 return r; 198 } 199 200 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 201 bo_size - fw_shared_size; 202 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 203 bo_size - fw_shared_size; 204 205 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 206 207 if (amdgpu_vcnfw_log) { 208 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 209 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 210 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 211 } 212 213 if (adev->vcn.indirect_sram) { 214 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 215 AMDGPU_GEM_DOMAIN_VRAM | 216 AMDGPU_GEM_DOMAIN_GTT, 217 &adev->vcn.inst[i].dpg_sram_bo, 218 &adev->vcn.inst[i].dpg_sram_gpu_addr, 219 &adev->vcn.inst[i].dpg_sram_cpu_addr); 220 if (r) { 221 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 222 return r; 223 } 224 } 225 } 226 227 return 0; 228 } 229 230 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 231 { 232 int i, j; 233 234 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 235 if (adev->vcn.harvest_config & (1 << j)) 236 continue; 237 238 if (adev->vcn.indirect_sram) { 239 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 240 &adev->vcn.inst[j].dpg_sram_gpu_addr, 241 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 242 } 243 kvfree(adev->vcn.inst[j].saved_bo); 244 245 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 246 &adev->vcn.inst[j].gpu_addr, 247 (void **)&adev->vcn.inst[j].cpu_addr); 248 249 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 250 251 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 252 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 253 } 254 255 amdgpu_ucode_release(&adev->vcn.fw); 256 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 257 mutex_destroy(&adev->vcn.vcn_pg_lock); 258 259 return 0; 260 } 261 262 /* from vcn4 and above, only unified queue is used */ 263 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) 264 { 265 struct amdgpu_device *adev = ring->adev; 266 bool ret = false; 267 268 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)) 269 ret = true; 270 271 return ret; 272 } 273 274 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 275 { 276 bool ret = false; 277 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 278 279 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 280 ret = true; 281 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) { 282 ret = true; 283 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 284 ret = true; 285 } 286 287 return ret; 288 } 289 290 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 291 { 292 unsigned size; 293 void *ptr; 294 int i, idx; 295 296 cancel_delayed_work_sync(&adev->vcn.idle_work); 297 298 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 299 if (adev->vcn.harvest_config & (1 << i)) 300 continue; 301 if (adev->vcn.inst[i].vcpu_bo == NULL) 302 return 0; 303 304 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 305 ptr = adev->vcn.inst[i].cpu_addr; 306 307 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 308 if (!adev->vcn.inst[i].saved_bo) 309 return -ENOMEM; 310 311 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 312 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 313 drm_dev_exit(idx); 314 } 315 } 316 return 0; 317 } 318 319 int amdgpu_vcn_resume(struct amdgpu_device *adev) 320 { 321 unsigned size; 322 void *ptr; 323 int i, idx; 324 325 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 326 if (adev->vcn.harvest_config & (1 << i)) 327 continue; 328 if (adev->vcn.inst[i].vcpu_bo == NULL) 329 return -EINVAL; 330 331 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 332 ptr = adev->vcn.inst[i].cpu_addr; 333 334 if (adev->vcn.inst[i].saved_bo != NULL) { 335 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 336 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 337 drm_dev_exit(idx); 338 } 339 kvfree(adev->vcn.inst[i].saved_bo); 340 adev->vcn.inst[i].saved_bo = NULL; 341 } else { 342 const struct common_firmware_header *hdr; 343 unsigned offset; 344 345 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 346 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 347 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 348 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 349 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 350 le32_to_cpu(hdr->ucode_size_bytes)); 351 drm_dev_exit(idx); 352 } 353 size -= le32_to_cpu(hdr->ucode_size_bytes); 354 ptr += le32_to_cpu(hdr->ucode_size_bytes); 355 } 356 memset_io(ptr, 0, size); 357 } 358 } 359 return 0; 360 } 361 362 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 363 { 364 struct amdgpu_device *adev = 365 container_of(work, struct amdgpu_device, vcn.idle_work.work); 366 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 367 unsigned int i, j; 368 int r = 0; 369 370 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 371 if (adev->vcn.harvest_config & (1 << j)) 372 continue; 373 374 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 375 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 376 } 377 378 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 379 struct dpg_pause_state new_state; 380 381 if (fence[j] || 382 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 383 new_state.fw_based = VCN_DPG_STATE__PAUSE; 384 else 385 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 386 387 adev->vcn.pause_dpg_mode(adev, j, &new_state); 388 } 389 390 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 391 fences += fence[j]; 392 } 393 394 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 395 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 396 AMD_PG_STATE_GATE); 397 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 398 false); 399 if (r) 400 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 401 } else { 402 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 403 } 404 } 405 406 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 407 { 408 struct amdgpu_device *adev = ring->adev; 409 int r = 0; 410 411 atomic_inc(&adev->vcn.total_submission_cnt); 412 413 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 414 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 415 true); 416 if (r) 417 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 418 } 419 420 mutex_lock(&adev->vcn.vcn_pg_lock); 421 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 422 AMD_PG_STATE_UNGATE); 423 424 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 425 struct dpg_pause_state new_state; 426 427 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 428 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 429 new_state.fw_based = VCN_DPG_STATE__PAUSE; 430 } else { 431 unsigned int fences = 0; 432 unsigned int i; 433 434 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 435 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 436 437 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 438 new_state.fw_based = VCN_DPG_STATE__PAUSE; 439 else 440 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 441 } 442 443 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 444 } 445 mutex_unlock(&adev->vcn.vcn_pg_lock); 446 } 447 448 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 449 { 450 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 451 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 452 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 453 454 atomic_dec(&ring->adev->vcn.total_submission_cnt); 455 456 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 457 } 458 459 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 460 { 461 struct amdgpu_device *adev = ring->adev; 462 uint32_t tmp = 0; 463 unsigned i; 464 int r; 465 466 /* VCN in SRIOV does not support direct register read/write */ 467 if (amdgpu_sriov_vf(adev)) 468 return 0; 469 470 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 471 r = amdgpu_ring_alloc(ring, 3); 472 if (r) 473 return r; 474 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 475 amdgpu_ring_write(ring, 0xDEADBEEF); 476 amdgpu_ring_commit(ring); 477 for (i = 0; i < adev->usec_timeout; i++) { 478 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 479 if (tmp == 0xDEADBEEF) 480 break; 481 udelay(1); 482 } 483 484 if (i >= adev->usec_timeout) 485 r = -ETIMEDOUT; 486 487 return r; 488 } 489 490 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 491 { 492 struct amdgpu_device *adev = ring->adev; 493 uint32_t rptr; 494 unsigned int i; 495 int r; 496 497 if (amdgpu_sriov_vf(adev)) 498 return 0; 499 500 r = amdgpu_ring_alloc(ring, 16); 501 if (r) 502 return r; 503 504 rptr = amdgpu_ring_get_rptr(ring); 505 506 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 507 amdgpu_ring_commit(ring); 508 509 for (i = 0; i < adev->usec_timeout; i++) { 510 if (amdgpu_ring_get_rptr(ring) != rptr) 511 break; 512 udelay(1); 513 } 514 515 if (i >= adev->usec_timeout) 516 r = -ETIMEDOUT; 517 518 return r; 519 } 520 521 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 522 struct amdgpu_ib *ib_msg, 523 struct dma_fence **fence) 524 { 525 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 526 struct amdgpu_device *adev = ring->adev; 527 struct dma_fence *f = NULL; 528 struct amdgpu_job *job; 529 struct amdgpu_ib *ib; 530 int i, r; 531 532 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 533 64, AMDGPU_IB_POOL_DIRECT, 534 &job); 535 if (r) 536 goto err; 537 538 ib = &job->ibs[0]; 539 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 540 ib->ptr[1] = addr; 541 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 542 ib->ptr[3] = addr >> 32; 543 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 544 ib->ptr[5] = 0; 545 for (i = 6; i < 16; i += 2) { 546 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 547 ib->ptr[i+1] = 0; 548 } 549 ib->length_dw = 16; 550 551 r = amdgpu_job_submit_direct(job, ring, &f); 552 if (r) 553 goto err_free; 554 555 amdgpu_ib_free(adev, ib_msg, f); 556 557 if (fence) 558 *fence = dma_fence_get(f); 559 dma_fence_put(f); 560 561 return 0; 562 563 err_free: 564 amdgpu_job_free(job); 565 err: 566 amdgpu_ib_free(adev, ib_msg, f); 567 return r; 568 } 569 570 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 571 struct amdgpu_ib *ib) 572 { 573 struct amdgpu_device *adev = ring->adev; 574 uint32_t *msg; 575 int r, i; 576 577 memset(ib, 0, sizeof(*ib)); 578 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 579 AMDGPU_IB_POOL_DIRECT, 580 ib); 581 if (r) 582 return r; 583 584 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 585 msg[0] = cpu_to_le32(0x00000028); 586 msg[1] = cpu_to_le32(0x00000038); 587 msg[2] = cpu_to_le32(0x00000001); 588 msg[3] = cpu_to_le32(0x00000000); 589 msg[4] = cpu_to_le32(handle); 590 msg[5] = cpu_to_le32(0x00000000); 591 msg[6] = cpu_to_le32(0x00000001); 592 msg[7] = cpu_to_le32(0x00000028); 593 msg[8] = cpu_to_le32(0x00000010); 594 msg[9] = cpu_to_le32(0x00000000); 595 msg[10] = cpu_to_le32(0x00000007); 596 msg[11] = cpu_to_le32(0x00000000); 597 msg[12] = cpu_to_le32(0x00000780); 598 msg[13] = cpu_to_le32(0x00000440); 599 for (i = 14; i < 1024; ++i) 600 msg[i] = cpu_to_le32(0x0); 601 602 return 0; 603 } 604 605 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 606 struct amdgpu_ib *ib) 607 { 608 struct amdgpu_device *adev = ring->adev; 609 uint32_t *msg; 610 int r, i; 611 612 memset(ib, 0, sizeof(*ib)); 613 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 614 AMDGPU_IB_POOL_DIRECT, 615 ib); 616 if (r) 617 return r; 618 619 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 620 msg[0] = cpu_to_le32(0x00000028); 621 msg[1] = cpu_to_le32(0x00000018); 622 msg[2] = cpu_to_le32(0x00000000); 623 msg[3] = cpu_to_le32(0x00000002); 624 msg[4] = cpu_to_le32(handle); 625 msg[5] = cpu_to_le32(0x00000000); 626 for (i = 6; i < 1024; ++i) 627 msg[i] = cpu_to_le32(0x0); 628 629 return 0; 630 } 631 632 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 633 { 634 struct dma_fence *fence = NULL; 635 struct amdgpu_ib ib; 636 long r; 637 638 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 639 if (r) 640 goto error; 641 642 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 643 if (r) 644 goto error; 645 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 646 if (r) 647 goto error; 648 649 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 650 if (r) 651 goto error; 652 653 r = dma_fence_wait_timeout(fence, false, timeout); 654 if (r == 0) 655 r = -ETIMEDOUT; 656 else if (r > 0) 657 r = 0; 658 659 dma_fence_put(fence); 660 error: 661 return r; 662 } 663 664 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 665 uint32_t ib_pack_in_dw, bool enc) 666 { 667 uint32_t *ib_checksum; 668 669 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 670 ib->ptr[ib->length_dw++] = 0x30000002; 671 ib_checksum = &ib->ptr[ib->length_dw++]; 672 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 673 674 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 675 ib->ptr[ib->length_dw++] = 0x30000001; 676 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 677 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 678 679 return ib_checksum; 680 } 681 682 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 683 uint32_t ib_pack_in_dw) 684 { 685 uint32_t i; 686 uint32_t checksum = 0; 687 688 for (i = 0; i < ib_pack_in_dw; i++) 689 checksum += *(*ib_checksum + 2 + i); 690 691 **ib_checksum = checksum; 692 } 693 694 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 695 struct amdgpu_ib *ib_msg, 696 struct dma_fence **fence) 697 { 698 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 699 unsigned int ib_size_dw = 64; 700 struct amdgpu_device *adev = ring->adev; 701 struct dma_fence *f = NULL; 702 struct amdgpu_job *job; 703 struct amdgpu_ib *ib; 704 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 705 bool sq = amdgpu_vcn_using_unified_queue(ring); 706 uint32_t *ib_checksum; 707 uint32_t ib_pack_in_dw; 708 int i, r; 709 710 if (sq) 711 ib_size_dw += 8; 712 713 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 714 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 715 &job); 716 if (r) 717 goto err; 718 719 ib = &job->ibs[0]; 720 ib->length_dw = 0; 721 722 /* single queue headers */ 723 if (sq) { 724 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 725 + 4 + 2; /* engine info + decoding ib in dw */ 726 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 727 } 728 729 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 730 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 731 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 732 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 733 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 734 735 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 736 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 737 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 738 739 for (i = ib->length_dw; i < ib_size_dw; ++i) 740 ib->ptr[i] = 0x0; 741 742 if (sq) 743 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 744 745 r = amdgpu_job_submit_direct(job, ring, &f); 746 if (r) 747 goto err_free; 748 749 amdgpu_ib_free(adev, ib_msg, f); 750 751 if (fence) 752 *fence = dma_fence_get(f); 753 dma_fence_put(f); 754 755 return 0; 756 757 err_free: 758 amdgpu_job_free(job); 759 err: 760 amdgpu_ib_free(adev, ib_msg, f); 761 return r; 762 } 763 764 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 765 { 766 struct dma_fence *fence = NULL; 767 struct amdgpu_ib ib; 768 long r; 769 770 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 771 if (r) 772 goto error; 773 774 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 775 if (r) 776 goto error; 777 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 778 if (r) 779 goto error; 780 781 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 782 if (r) 783 goto error; 784 785 r = dma_fence_wait_timeout(fence, false, timeout); 786 if (r == 0) 787 r = -ETIMEDOUT; 788 else if (r > 0) 789 r = 0; 790 791 dma_fence_put(fence); 792 error: 793 return r; 794 } 795 796 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 797 { 798 struct amdgpu_device *adev = ring->adev; 799 uint32_t rptr; 800 unsigned i; 801 int r; 802 803 if (amdgpu_sriov_vf(adev)) 804 return 0; 805 806 r = amdgpu_ring_alloc(ring, 16); 807 if (r) 808 return r; 809 810 rptr = amdgpu_ring_get_rptr(ring); 811 812 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 813 amdgpu_ring_commit(ring); 814 815 for (i = 0; i < adev->usec_timeout; i++) { 816 if (amdgpu_ring_get_rptr(ring) != rptr) 817 break; 818 udelay(1); 819 } 820 821 if (i >= adev->usec_timeout) 822 r = -ETIMEDOUT; 823 824 return r; 825 } 826 827 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 828 struct amdgpu_ib *ib_msg, 829 struct dma_fence **fence) 830 { 831 unsigned int ib_size_dw = 16; 832 struct amdgpu_job *job; 833 struct amdgpu_ib *ib; 834 struct dma_fence *f = NULL; 835 uint32_t *ib_checksum = NULL; 836 uint64_t addr; 837 bool sq = amdgpu_vcn_using_unified_queue(ring); 838 int i, r; 839 840 if (sq) 841 ib_size_dw += 8; 842 843 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 844 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 845 &job); 846 if (r) 847 return r; 848 849 ib = &job->ibs[0]; 850 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 851 852 ib->length_dw = 0; 853 854 if (sq) 855 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 856 857 ib->ptr[ib->length_dw++] = 0x00000018; 858 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 859 ib->ptr[ib->length_dw++] = handle; 860 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 861 ib->ptr[ib->length_dw++] = addr; 862 ib->ptr[ib->length_dw++] = 0x0000000b; 863 864 ib->ptr[ib->length_dw++] = 0x00000014; 865 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 866 ib->ptr[ib->length_dw++] = 0x0000001c; 867 ib->ptr[ib->length_dw++] = 0x00000000; 868 ib->ptr[ib->length_dw++] = 0x00000000; 869 870 ib->ptr[ib->length_dw++] = 0x00000008; 871 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 872 873 for (i = ib->length_dw; i < ib_size_dw; ++i) 874 ib->ptr[i] = 0x0; 875 876 if (sq) 877 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 878 879 r = amdgpu_job_submit_direct(job, ring, &f); 880 if (r) 881 goto err; 882 883 if (fence) 884 *fence = dma_fence_get(f); 885 dma_fence_put(f); 886 887 return 0; 888 889 err: 890 amdgpu_job_free(job); 891 return r; 892 } 893 894 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 895 struct amdgpu_ib *ib_msg, 896 struct dma_fence **fence) 897 { 898 unsigned int ib_size_dw = 16; 899 struct amdgpu_job *job; 900 struct amdgpu_ib *ib; 901 struct dma_fence *f = NULL; 902 uint32_t *ib_checksum = NULL; 903 uint64_t addr; 904 bool sq = amdgpu_vcn_using_unified_queue(ring); 905 int i, r; 906 907 if (sq) 908 ib_size_dw += 8; 909 910 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 911 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 912 &job); 913 if (r) 914 return r; 915 916 ib = &job->ibs[0]; 917 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 918 919 ib->length_dw = 0; 920 921 if (sq) 922 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 923 924 ib->ptr[ib->length_dw++] = 0x00000018; 925 ib->ptr[ib->length_dw++] = 0x00000001; 926 ib->ptr[ib->length_dw++] = handle; 927 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 928 ib->ptr[ib->length_dw++] = addr; 929 ib->ptr[ib->length_dw++] = 0x0000000b; 930 931 ib->ptr[ib->length_dw++] = 0x00000014; 932 ib->ptr[ib->length_dw++] = 0x00000002; 933 ib->ptr[ib->length_dw++] = 0x0000001c; 934 ib->ptr[ib->length_dw++] = 0x00000000; 935 ib->ptr[ib->length_dw++] = 0x00000000; 936 937 ib->ptr[ib->length_dw++] = 0x00000008; 938 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 939 940 for (i = ib->length_dw; i < ib_size_dw; ++i) 941 ib->ptr[i] = 0x0; 942 943 if (sq) 944 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 945 946 r = amdgpu_job_submit_direct(job, ring, &f); 947 if (r) 948 goto err; 949 950 if (fence) 951 *fence = dma_fence_get(f); 952 dma_fence_put(f); 953 954 return 0; 955 956 err: 957 amdgpu_job_free(job); 958 return r; 959 } 960 961 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 962 { 963 struct amdgpu_device *adev = ring->adev; 964 struct dma_fence *fence = NULL; 965 struct amdgpu_ib ib; 966 long r; 967 968 memset(&ib, 0, sizeof(ib)); 969 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 970 AMDGPU_IB_POOL_DIRECT, 971 &ib); 972 if (r) 973 return r; 974 975 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 976 if (r) 977 goto error; 978 979 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 980 if (r) 981 goto error; 982 983 r = dma_fence_wait_timeout(fence, false, timeout); 984 if (r == 0) 985 r = -ETIMEDOUT; 986 else if (r > 0) 987 r = 0; 988 989 error: 990 amdgpu_ib_free(adev, &ib, fence); 991 dma_fence_put(fence); 992 993 return r; 994 } 995 996 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 997 { 998 struct amdgpu_device *adev = ring->adev; 999 long r; 1000 1001 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(4, 0, 3)) { 1002 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1003 if (r) 1004 goto error; 1005 } 1006 1007 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1008 1009 error: 1010 return r; 1011 } 1012 1013 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1014 { 1015 switch(ring) { 1016 case 0: 1017 return AMDGPU_RING_PRIO_0; 1018 case 1: 1019 return AMDGPU_RING_PRIO_1; 1020 case 2: 1021 return AMDGPU_RING_PRIO_2; 1022 default: 1023 return AMDGPU_RING_PRIO_0; 1024 } 1025 } 1026 1027 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 1028 { 1029 int i; 1030 unsigned int idx; 1031 1032 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1033 const struct common_firmware_header *hdr; 1034 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 1035 1036 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1037 if (adev->vcn.harvest_config & (1 << i)) 1038 continue; 1039 /* currently only support 2 FW instances */ 1040 if (i >= 2) { 1041 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1042 break; 1043 } 1044 idx = AMDGPU_UCODE_ID_VCN + i; 1045 adev->firmware.ucode[idx].ucode_id = idx; 1046 adev->firmware.ucode[idx].fw = adev->vcn.fw; 1047 adev->firmware.fw_size += 1048 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1049 1050 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(4, 0, 3)) 1051 break; 1052 } 1053 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 1054 } 1055 } 1056 1057 /* 1058 * debugfs for mapping vcn firmware log buffer. 1059 */ 1060 #if defined(CONFIG_DEBUG_FS) 1061 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1062 size_t size, loff_t *pos) 1063 { 1064 struct amdgpu_vcn_inst *vcn; 1065 void *log_buf; 1066 volatile struct amdgpu_vcn_fwlog *plog; 1067 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1068 unsigned int read_num[2] = {0}; 1069 1070 vcn = file_inode(f)->i_private; 1071 if (!vcn) 1072 return -ENODEV; 1073 1074 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1075 return -EFAULT; 1076 1077 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1078 1079 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1080 read_pos = plog->rptr; 1081 write_pos = plog->wptr; 1082 1083 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1084 return -EFAULT; 1085 1086 if (!size || (read_pos == write_pos)) 1087 return 0; 1088 1089 if (write_pos > read_pos) { 1090 available = write_pos - read_pos; 1091 read_num[0] = min(size, (size_t)available); 1092 } else { 1093 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1094 available = read_num[0] + write_pos - plog->header_size; 1095 if (size > available) 1096 read_num[1] = write_pos - plog->header_size; 1097 else if (size > read_num[0]) 1098 read_num[1] = size - read_num[0]; 1099 else 1100 read_num[0] = size; 1101 } 1102 1103 for (i = 0; i < 2; i++) { 1104 if (read_num[i]) { 1105 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1106 read_pos = plog->header_size; 1107 if (read_num[i] == copy_to_user((buf + read_bytes), 1108 (log_buf + read_pos), read_num[i])) 1109 return -EFAULT; 1110 1111 read_bytes += read_num[i]; 1112 read_pos += read_num[i]; 1113 } 1114 } 1115 1116 plog->rptr = read_pos; 1117 *pos += read_bytes; 1118 return read_bytes; 1119 } 1120 1121 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1122 .owner = THIS_MODULE, 1123 .read = amdgpu_debugfs_vcn_fwlog_read, 1124 .llseek = default_llseek 1125 }; 1126 #endif 1127 1128 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1129 struct amdgpu_vcn_inst *vcn) 1130 { 1131 #if defined(CONFIG_DEBUG_FS) 1132 struct drm_minor *minor = adev_to_drm(adev)->primary; 1133 struct dentry *root = minor->debugfs_root; 1134 char name[32]; 1135 1136 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1137 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn, 1138 &amdgpu_debugfs_vcnfwlog_fops, 1139 AMDGPU_VCNFW_LOG_SIZE); 1140 #endif 1141 } 1142 1143 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1144 { 1145 #if defined(CONFIG_DEBUG_FS) 1146 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1147 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1148 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1149 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1150 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1151 + vcn->fw_shared.log_offset; 1152 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1153 fw_log->is_enabled = 1; 1154 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1155 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1156 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1157 1158 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1159 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1160 log_buf->rptr = log_buf->header_size; 1161 log_buf->wptr = log_buf->header_size; 1162 log_buf->wrapped = 0; 1163 #endif 1164 } 1165 1166 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1167 struct amdgpu_irq_src *source, 1168 struct amdgpu_iv_entry *entry) 1169 { 1170 struct ras_common_if *ras_if = adev->vcn.ras_if; 1171 struct ras_dispatch_if ih_data = { 1172 .entry = entry, 1173 }; 1174 1175 if (!ras_if) 1176 return 0; 1177 1178 if (!amdgpu_sriov_vf(adev)) { 1179 ih_data.head = *ras_if; 1180 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1181 } else { 1182 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1183 adev->virt.ops->ras_poison_handler(adev); 1184 else 1185 dev_warn(adev->dev, 1186 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1187 } 1188 1189 return 0; 1190 } 1191 1192 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1193 { 1194 int err; 1195 struct amdgpu_vcn_ras *ras; 1196 1197 if (!adev->vcn.ras) 1198 return 0; 1199 1200 ras = adev->vcn.ras; 1201 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1202 if (err) { 1203 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1204 return err; 1205 } 1206 1207 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1208 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1209 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1210 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1211 1212 if (!ras->ras_block.ras_late_init) 1213 ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; 1214 1215 return 0; 1216 } 1217