1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <drm/drm_drv.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_vcn.h" 35 #include "soc15d.h" 36 37 /* Firmware Names */ 38 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 39 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 40 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 41 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 42 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 43 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 44 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 45 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 46 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 48 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 49 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 50 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 51 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 52 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 53 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 54 55 MODULE_FIRMWARE(FIRMWARE_RAVEN); 56 MODULE_FIRMWARE(FIRMWARE_PICASSO); 57 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 59 MODULE_FIRMWARE(FIRMWARE_RENOIR); 60 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 61 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 62 MODULE_FIRMWARE(FIRMWARE_NAVI10); 63 MODULE_FIRMWARE(FIRMWARE_NAVI14); 64 MODULE_FIRMWARE(FIRMWARE_NAVI12); 65 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 66 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 67 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 68 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 69 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 70 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 71 72 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 73 74 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 75 { 76 unsigned long bo_size; 77 const char *fw_name; 78 const struct common_firmware_header *hdr; 79 unsigned char fw_check; 80 int i, r; 81 82 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 83 mutex_init(&adev->vcn.vcn_pg_lock); 84 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 85 atomic_set(&adev->vcn.total_submission_cnt, 0); 86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 87 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 88 89 switch (adev->asic_type) { 90 case CHIP_RAVEN: 91 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 92 fw_name = FIRMWARE_RAVEN2; 93 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 94 fw_name = FIRMWARE_PICASSO; 95 else 96 fw_name = FIRMWARE_RAVEN; 97 break; 98 case CHIP_ARCTURUS: 99 fw_name = FIRMWARE_ARCTURUS; 100 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 101 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 102 adev->vcn.indirect_sram = true; 103 break; 104 case CHIP_RENOIR: 105 if (adev->apu_flags & AMD_APU_IS_RENOIR) 106 fw_name = FIRMWARE_RENOIR; 107 else 108 fw_name = FIRMWARE_GREEN_SARDINE; 109 110 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 111 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 112 adev->vcn.indirect_sram = true; 113 break; 114 case CHIP_ALDEBARAN: 115 fw_name = FIRMWARE_ALDEBARAN; 116 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 117 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 118 adev->vcn.indirect_sram = true; 119 break; 120 case CHIP_NAVI10: 121 fw_name = FIRMWARE_NAVI10; 122 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 123 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 124 adev->vcn.indirect_sram = true; 125 break; 126 case CHIP_NAVI14: 127 fw_name = FIRMWARE_NAVI14; 128 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 129 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 130 adev->vcn.indirect_sram = true; 131 break; 132 case CHIP_NAVI12: 133 fw_name = FIRMWARE_NAVI12; 134 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 135 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 136 adev->vcn.indirect_sram = true; 137 break; 138 case CHIP_SIENNA_CICHLID: 139 fw_name = FIRMWARE_SIENNA_CICHLID; 140 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 141 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 142 adev->vcn.indirect_sram = true; 143 break; 144 case CHIP_NAVY_FLOUNDER: 145 fw_name = FIRMWARE_NAVY_FLOUNDER; 146 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 147 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 148 adev->vcn.indirect_sram = true; 149 break; 150 case CHIP_VANGOGH: 151 fw_name = FIRMWARE_VANGOGH; 152 break; 153 case CHIP_DIMGREY_CAVEFISH: 154 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 155 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 156 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 157 adev->vcn.indirect_sram = true; 158 break; 159 case CHIP_BEIGE_GOBY: 160 fw_name = FIRMWARE_BEIGE_GOBY; 161 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 162 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 163 adev->vcn.indirect_sram = true; 164 break; 165 case CHIP_YELLOW_CARP: 166 fw_name = FIRMWARE_YELLOW_CARP; 167 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 168 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 169 adev->vcn.indirect_sram = true; 170 break; 171 default: 172 return -EINVAL; 173 } 174 175 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 176 if (r) { 177 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 178 fw_name); 179 return r; 180 } 181 182 r = amdgpu_ucode_validate(adev->vcn.fw); 183 if (r) { 184 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 185 fw_name); 186 release_firmware(adev->vcn.fw); 187 adev->vcn.fw = NULL; 188 return r; 189 } 190 191 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 192 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 193 194 /* Bit 20-23, it is encode major and non-zero for new naming convention. 195 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 196 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 197 * is zero in old naming convention, this field is always zero so far. 198 * These four bits are used to tell which naming convention is present. 199 */ 200 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 201 if (fw_check) { 202 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 203 204 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 205 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 206 enc_major = fw_check; 207 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 208 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 209 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 210 enc_major, enc_minor, dec_ver, vep, fw_rev); 211 } else { 212 unsigned int version_major, version_minor, family_id; 213 214 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 215 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 216 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 217 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 218 version_major, version_minor, family_id); 219 } 220 221 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 222 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 223 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 224 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 225 226 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 227 if (adev->vcn.harvest_config & (1 << i)) 228 continue; 229 230 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 231 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 232 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 233 if (r) { 234 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 235 return r; 236 } 237 238 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr + 239 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 240 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr + 241 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 242 243 if (adev->vcn.indirect_sram) { 244 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 245 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 246 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 247 if (r) { 248 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 249 return r; 250 } 251 } 252 } 253 254 return 0; 255 } 256 257 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 258 { 259 int i, j; 260 261 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 262 if (adev->vcn.harvest_config & (1 << j)) 263 continue; 264 265 if (adev->vcn.indirect_sram) { 266 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 267 &adev->vcn.inst[j].dpg_sram_gpu_addr, 268 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 269 } 270 kvfree(adev->vcn.inst[j].saved_bo); 271 272 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 273 &adev->vcn.inst[j].gpu_addr, 274 (void **)&adev->vcn.inst[j].cpu_addr); 275 276 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 277 278 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 279 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 280 } 281 282 release_firmware(adev->vcn.fw); 283 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 284 mutex_destroy(&adev->vcn.vcn_pg_lock); 285 286 return 0; 287 } 288 289 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 290 { 291 bool ret = false; 292 293 int major; 294 int minor; 295 int revision; 296 297 /* if cannot find IP data, then this VCN does not exist */ 298 if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, &major, &minor, &revision) != 0) 299 return true; 300 301 if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 302 ret = true; 303 } else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) { 304 ret = true; 305 } else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 306 ret = true; 307 } 308 309 return ret; 310 } 311 312 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 313 { 314 unsigned size; 315 void *ptr; 316 int i, idx; 317 318 cancel_delayed_work_sync(&adev->vcn.idle_work); 319 320 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 321 if (adev->vcn.harvest_config & (1 << i)) 322 continue; 323 if (adev->vcn.inst[i].vcpu_bo == NULL) 324 return 0; 325 326 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 327 ptr = adev->vcn.inst[i].cpu_addr; 328 329 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 330 if (!adev->vcn.inst[i].saved_bo) 331 return -ENOMEM; 332 333 if (drm_dev_enter(&adev->ddev, &idx)) { 334 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 335 drm_dev_exit(idx); 336 } 337 } 338 return 0; 339 } 340 341 int amdgpu_vcn_resume(struct amdgpu_device *adev) 342 { 343 unsigned size; 344 void *ptr; 345 int i, idx; 346 347 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 348 if (adev->vcn.harvest_config & (1 << i)) 349 continue; 350 if (adev->vcn.inst[i].vcpu_bo == NULL) 351 return -EINVAL; 352 353 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 354 ptr = adev->vcn.inst[i].cpu_addr; 355 356 if (adev->vcn.inst[i].saved_bo != NULL) { 357 if (drm_dev_enter(&adev->ddev, &idx)) { 358 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 359 drm_dev_exit(idx); 360 } 361 kvfree(adev->vcn.inst[i].saved_bo); 362 adev->vcn.inst[i].saved_bo = NULL; 363 } else { 364 const struct common_firmware_header *hdr; 365 unsigned offset; 366 367 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 368 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 369 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 370 if (drm_dev_enter(&adev->ddev, &idx)) { 371 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 372 le32_to_cpu(hdr->ucode_size_bytes)); 373 drm_dev_exit(idx); 374 } 375 size -= le32_to_cpu(hdr->ucode_size_bytes); 376 ptr += le32_to_cpu(hdr->ucode_size_bytes); 377 } 378 memset_io(ptr, 0, size); 379 } 380 } 381 return 0; 382 } 383 384 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 385 { 386 struct amdgpu_device *adev = 387 container_of(work, struct amdgpu_device, vcn.idle_work.work); 388 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 389 unsigned int i, j; 390 int r = 0; 391 392 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 393 if (adev->vcn.harvest_config & (1 << j)) 394 continue; 395 396 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 397 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 398 } 399 400 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 401 struct dpg_pause_state new_state; 402 403 if (fence[j] || 404 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 405 new_state.fw_based = VCN_DPG_STATE__PAUSE; 406 else 407 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 408 409 adev->vcn.pause_dpg_mode(adev, j, &new_state); 410 } 411 412 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 413 fences += fence[j]; 414 } 415 416 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 417 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 418 AMD_PG_STATE_GATE); 419 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 420 false); 421 if (r) 422 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 423 } else { 424 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 425 } 426 } 427 428 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 429 { 430 struct amdgpu_device *adev = ring->adev; 431 int r = 0; 432 433 atomic_inc(&adev->vcn.total_submission_cnt); 434 435 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 436 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 437 true); 438 if (r) 439 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 440 } 441 442 mutex_lock(&adev->vcn.vcn_pg_lock); 443 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 444 AMD_PG_STATE_UNGATE); 445 446 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 447 struct dpg_pause_state new_state; 448 449 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 450 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 451 new_state.fw_based = VCN_DPG_STATE__PAUSE; 452 } else { 453 unsigned int fences = 0; 454 unsigned int i; 455 456 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 457 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 458 459 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 460 new_state.fw_based = VCN_DPG_STATE__PAUSE; 461 else 462 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 463 } 464 465 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 466 } 467 mutex_unlock(&adev->vcn.vcn_pg_lock); 468 } 469 470 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 471 { 472 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 473 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 474 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 475 476 atomic_dec(&ring->adev->vcn.total_submission_cnt); 477 478 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 479 } 480 481 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 482 { 483 struct amdgpu_device *adev = ring->adev; 484 uint32_t tmp = 0; 485 unsigned i; 486 int r; 487 488 /* VCN in SRIOV does not support direct register read/write */ 489 if (amdgpu_sriov_vf(adev)) 490 return 0; 491 492 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 493 r = amdgpu_ring_alloc(ring, 3); 494 if (r) 495 return r; 496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 497 amdgpu_ring_write(ring, 0xDEADBEEF); 498 amdgpu_ring_commit(ring); 499 for (i = 0; i < adev->usec_timeout; i++) { 500 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 501 if (tmp == 0xDEADBEEF) 502 break; 503 udelay(1); 504 } 505 506 if (i >= adev->usec_timeout) 507 r = -ETIMEDOUT; 508 509 return r; 510 } 511 512 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 513 { 514 struct amdgpu_device *adev = ring->adev; 515 uint32_t rptr; 516 unsigned int i; 517 int r; 518 519 if (amdgpu_sriov_vf(adev)) 520 return 0; 521 522 r = amdgpu_ring_alloc(ring, 16); 523 if (r) 524 return r; 525 526 rptr = amdgpu_ring_get_rptr(ring); 527 528 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 529 amdgpu_ring_commit(ring); 530 531 for (i = 0; i < adev->usec_timeout; i++) { 532 if (amdgpu_ring_get_rptr(ring) != rptr) 533 break; 534 udelay(1); 535 } 536 537 if (i >= adev->usec_timeout) 538 r = -ETIMEDOUT; 539 540 return r; 541 } 542 543 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 544 struct amdgpu_ib *ib_msg, 545 struct dma_fence **fence) 546 { 547 struct amdgpu_device *adev = ring->adev; 548 struct dma_fence *f = NULL; 549 struct amdgpu_job *job; 550 struct amdgpu_ib *ib; 551 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 552 int i, r; 553 554 r = amdgpu_job_alloc_with_ib(adev, 64, 555 AMDGPU_IB_POOL_DIRECT, &job); 556 if (r) 557 goto err; 558 559 ib = &job->ibs[0]; 560 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 561 ib->ptr[1] = addr; 562 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 563 ib->ptr[3] = addr >> 32; 564 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 565 ib->ptr[5] = 0; 566 for (i = 6; i < 16; i += 2) { 567 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 568 ib->ptr[i+1] = 0; 569 } 570 ib->length_dw = 16; 571 572 r = amdgpu_job_submit_direct(job, ring, &f); 573 if (r) 574 goto err_free; 575 576 amdgpu_ib_free(adev, ib_msg, f); 577 578 if (fence) 579 *fence = dma_fence_get(f); 580 dma_fence_put(f); 581 582 return 0; 583 584 err_free: 585 amdgpu_job_free(job); 586 err: 587 amdgpu_ib_free(adev, ib_msg, f); 588 return r; 589 } 590 591 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 592 struct amdgpu_ib *ib) 593 { 594 struct amdgpu_device *adev = ring->adev; 595 uint32_t *msg; 596 int r, i; 597 598 memset(ib, 0, sizeof(*ib)); 599 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 600 AMDGPU_IB_POOL_DIRECT, 601 ib); 602 if (r) 603 return r; 604 605 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 606 msg[0] = cpu_to_le32(0x00000028); 607 msg[1] = cpu_to_le32(0x00000038); 608 msg[2] = cpu_to_le32(0x00000001); 609 msg[3] = cpu_to_le32(0x00000000); 610 msg[4] = cpu_to_le32(handle); 611 msg[5] = cpu_to_le32(0x00000000); 612 msg[6] = cpu_to_le32(0x00000001); 613 msg[7] = cpu_to_le32(0x00000028); 614 msg[8] = cpu_to_le32(0x00000010); 615 msg[9] = cpu_to_le32(0x00000000); 616 msg[10] = cpu_to_le32(0x00000007); 617 msg[11] = cpu_to_le32(0x00000000); 618 msg[12] = cpu_to_le32(0x00000780); 619 msg[13] = cpu_to_le32(0x00000440); 620 for (i = 14; i < 1024; ++i) 621 msg[i] = cpu_to_le32(0x0); 622 623 return 0; 624 } 625 626 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 627 struct amdgpu_ib *ib) 628 { 629 struct amdgpu_device *adev = ring->adev; 630 uint32_t *msg; 631 int r, i; 632 633 memset(ib, 0, sizeof(*ib)); 634 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 635 AMDGPU_IB_POOL_DIRECT, 636 ib); 637 if (r) 638 return r; 639 640 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 641 msg[0] = cpu_to_le32(0x00000028); 642 msg[1] = cpu_to_le32(0x00000018); 643 msg[2] = cpu_to_le32(0x00000000); 644 msg[3] = cpu_to_le32(0x00000002); 645 msg[4] = cpu_to_le32(handle); 646 msg[5] = cpu_to_le32(0x00000000); 647 for (i = 6; i < 1024; ++i) 648 msg[i] = cpu_to_le32(0x0); 649 650 return 0; 651 } 652 653 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 654 { 655 struct dma_fence *fence = NULL; 656 struct amdgpu_ib ib; 657 long r; 658 659 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 660 if (r) 661 goto error; 662 663 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 664 if (r) 665 goto error; 666 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 667 if (r) 668 goto error; 669 670 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 671 if (r) 672 goto error; 673 674 r = dma_fence_wait_timeout(fence, false, timeout); 675 if (r == 0) 676 r = -ETIMEDOUT; 677 else if (r > 0) 678 r = 0; 679 680 dma_fence_put(fence); 681 error: 682 return r; 683 } 684 685 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 686 struct amdgpu_ib *ib_msg, 687 struct dma_fence **fence) 688 { 689 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 690 const unsigned int ib_size_dw = 64; 691 struct amdgpu_device *adev = ring->adev; 692 struct dma_fence *f = NULL; 693 struct amdgpu_job *job; 694 struct amdgpu_ib *ib; 695 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 696 int i, r; 697 698 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 699 AMDGPU_IB_POOL_DIRECT, &job); 700 if (r) 701 goto err; 702 703 ib = &job->ibs[0]; 704 ib->length_dw = 0; 705 706 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 707 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 708 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 709 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 710 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 711 712 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 713 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 714 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 715 716 for (i = ib->length_dw; i < ib_size_dw; ++i) 717 ib->ptr[i] = 0x0; 718 719 r = amdgpu_job_submit_direct(job, ring, &f); 720 if (r) 721 goto err_free; 722 723 amdgpu_ib_free(adev, ib_msg, f); 724 725 if (fence) 726 *fence = dma_fence_get(f); 727 dma_fence_put(f); 728 729 return 0; 730 731 err_free: 732 amdgpu_job_free(job); 733 err: 734 amdgpu_ib_free(adev, ib_msg, f); 735 return r; 736 } 737 738 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 739 { 740 struct dma_fence *fence = NULL; 741 struct amdgpu_ib ib; 742 long r; 743 744 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 745 if (r) 746 goto error; 747 748 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 749 if (r) 750 goto error; 751 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 752 if (r) 753 goto error; 754 755 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 756 if (r) 757 goto error; 758 759 r = dma_fence_wait_timeout(fence, false, timeout); 760 if (r == 0) 761 r = -ETIMEDOUT; 762 else if (r > 0) 763 r = 0; 764 765 dma_fence_put(fence); 766 error: 767 return r; 768 } 769 770 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 771 { 772 struct amdgpu_device *adev = ring->adev; 773 uint32_t rptr; 774 unsigned i; 775 int r; 776 777 if (amdgpu_sriov_vf(adev)) 778 return 0; 779 780 r = amdgpu_ring_alloc(ring, 16); 781 if (r) 782 return r; 783 784 rptr = amdgpu_ring_get_rptr(ring); 785 786 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 787 amdgpu_ring_commit(ring); 788 789 for (i = 0; i < adev->usec_timeout; i++) { 790 if (amdgpu_ring_get_rptr(ring) != rptr) 791 break; 792 udelay(1); 793 } 794 795 if (i >= adev->usec_timeout) 796 r = -ETIMEDOUT; 797 798 return r; 799 } 800 801 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 802 struct amdgpu_ib *ib_msg, 803 struct dma_fence **fence) 804 { 805 const unsigned ib_size_dw = 16; 806 struct amdgpu_job *job; 807 struct amdgpu_ib *ib; 808 struct dma_fence *f = NULL; 809 uint64_t addr; 810 int i, r; 811 812 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 813 AMDGPU_IB_POOL_DIRECT, &job); 814 if (r) 815 return r; 816 817 ib = &job->ibs[0]; 818 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 819 820 ib->length_dw = 0; 821 ib->ptr[ib->length_dw++] = 0x00000018; 822 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 823 ib->ptr[ib->length_dw++] = handle; 824 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 825 ib->ptr[ib->length_dw++] = addr; 826 ib->ptr[ib->length_dw++] = 0x0000000b; 827 828 ib->ptr[ib->length_dw++] = 0x00000014; 829 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 830 ib->ptr[ib->length_dw++] = 0x0000001c; 831 ib->ptr[ib->length_dw++] = 0x00000000; 832 ib->ptr[ib->length_dw++] = 0x00000000; 833 834 ib->ptr[ib->length_dw++] = 0x00000008; 835 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 836 837 for (i = ib->length_dw; i < ib_size_dw; ++i) 838 ib->ptr[i] = 0x0; 839 840 r = amdgpu_job_submit_direct(job, ring, &f); 841 if (r) 842 goto err; 843 844 if (fence) 845 *fence = dma_fence_get(f); 846 dma_fence_put(f); 847 848 return 0; 849 850 err: 851 amdgpu_job_free(job); 852 return r; 853 } 854 855 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 856 struct amdgpu_ib *ib_msg, 857 struct dma_fence **fence) 858 { 859 const unsigned ib_size_dw = 16; 860 struct amdgpu_job *job; 861 struct amdgpu_ib *ib; 862 struct dma_fence *f = NULL; 863 uint64_t addr; 864 int i, r; 865 866 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 867 AMDGPU_IB_POOL_DIRECT, &job); 868 if (r) 869 return r; 870 871 ib = &job->ibs[0]; 872 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 873 874 ib->length_dw = 0; 875 ib->ptr[ib->length_dw++] = 0x00000018; 876 ib->ptr[ib->length_dw++] = 0x00000001; 877 ib->ptr[ib->length_dw++] = handle; 878 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 879 ib->ptr[ib->length_dw++] = addr; 880 ib->ptr[ib->length_dw++] = 0x0000000b; 881 882 ib->ptr[ib->length_dw++] = 0x00000014; 883 ib->ptr[ib->length_dw++] = 0x00000002; 884 ib->ptr[ib->length_dw++] = 0x0000001c; 885 ib->ptr[ib->length_dw++] = 0x00000000; 886 ib->ptr[ib->length_dw++] = 0x00000000; 887 888 ib->ptr[ib->length_dw++] = 0x00000008; 889 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 890 891 for (i = ib->length_dw; i < ib_size_dw; ++i) 892 ib->ptr[i] = 0x0; 893 894 r = amdgpu_job_submit_direct(job, ring, &f); 895 if (r) 896 goto err; 897 898 if (fence) 899 *fence = dma_fence_get(f); 900 dma_fence_put(f); 901 902 return 0; 903 904 err: 905 amdgpu_job_free(job); 906 return r; 907 } 908 909 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 910 { 911 struct amdgpu_device *adev = ring->adev; 912 struct dma_fence *fence = NULL; 913 struct amdgpu_ib ib; 914 long r; 915 916 memset(&ib, 0, sizeof(ib)); 917 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 918 AMDGPU_IB_POOL_DIRECT, 919 &ib); 920 if (r) 921 return r; 922 923 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 924 if (r) 925 goto error; 926 927 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 928 if (r) 929 goto error; 930 931 r = dma_fence_wait_timeout(fence, false, timeout); 932 if (r == 0) 933 r = -ETIMEDOUT; 934 else if (r > 0) 935 r = 0; 936 937 error: 938 amdgpu_ib_free(adev, &ib, fence); 939 dma_fence_put(fence); 940 941 return r; 942 } 943 944 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 945 { 946 switch(ring) { 947 case 0: 948 return AMDGPU_RING_PRIO_0; 949 case 1: 950 return AMDGPU_RING_PRIO_1; 951 case 2: 952 return AMDGPU_RING_PRIO_2; 953 default: 954 return AMDGPU_RING_PRIO_0; 955 } 956 } 957