1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/dmi.h> 30 #include <linux/pci.h> 31 #include <linux/debugfs.h> 32 #include <drm/drm_drv.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_pm.h" 36 #include "amdgpu_vcn.h" 37 #include "soc15d.h" 38 39 /* Firmware Names */ 40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" 59 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 60 61 MODULE_FIRMWARE(FIRMWARE_RAVEN); 62 MODULE_FIRMWARE(FIRMWARE_PICASSO); 63 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 64 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 65 MODULE_FIRMWARE(FIRMWARE_RENOIR); 66 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 67 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 68 MODULE_FIRMWARE(FIRMWARE_NAVI10); 69 MODULE_FIRMWARE(FIRMWARE_NAVI14); 70 MODULE_FIRMWARE(FIRMWARE_NAVI12); 71 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 72 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 73 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 74 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 75 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 76 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 77 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 78 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 79 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); 80 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 81 82 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 83 84 int amdgpu_vcn_early_init(struct amdgpu_device *adev) 85 { 86 char ucode_prefix[30]; 87 char fw_name[40]; 88 int r; 89 90 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); 91 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 92 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name); 93 if (r) 94 amdgpu_ucode_release(&adev->vcn.fw); 95 96 return r; 97 } 98 99 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 100 { 101 unsigned long bo_size; 102 const struct common_firmware_header *hdr; 103 unsigned char fw_check; 104 unsigned int fw_shared_size, log_offset; 105 int i, r; 106 107 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 108 mutex_init(&adev->vcn.vcn_pg_lock); 109 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 110 atomic_set(&adev->vcn.total_submission_cnt, 0); 111 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 112 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 113 114 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 115 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 116 adev->vcn.indirect_sram = true; 117 118 /* 119 * Some Steam Deck's BIOS versions are incompatible with the 120 * indirect SRAM mode, leading to amdgpu being unable to get 121 * properly probed (and even potentially crashing the kernel). 122 * Hence, check for these versions here - notice this is 123 * restricted to Vangogh (Deck's APU). 124 */ 125 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 2)) { 126 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 127 128 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) || 129 !strncmp("F7A0114", bios_ver, 7))) { 130 adev->vcn.indirect_sram = false; 131 dev_info(adev->dev, 132 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver); 133 } 134 } 135 136 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 137 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 138 139 /* Bit 20-23, it is encode major and non-zero for new naming convention. 140 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 141 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 142 * is zero in old naming convention, this field is always zero so far. 143 * These four bits are used to tell which naming convention is present. 144 */ 145 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 146 if (fw_check) { 147 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 148 149 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 150 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 151 enc_major = fw_check; 152 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 153 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 154 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 155 enc_major, enc_minor, dec_ver, vep, fw_rev); 156 } else { 157 unsigned int version_major, version_minor, family_id; 158 159 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 160 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 161 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 162 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 163 version_major, version_minor, family_id); 164 } 165 166 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 167 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 168 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 169 170 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){ 171 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 172 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 173 } else { 174 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 175 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 176 } 177 178 bo_size += fw_shared_size; 179 180 if (amdgpu_vcnfw_log) 181 bo_size += AMDGPU_VCNFW_LOG_SIZE; 182 183 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 184 if (adev->vcn.harvest_config & (1 << i)) 185 continue; 186 187 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 188 AMDGPU_GEM_DOMAIN_VRAM | 189 AMDGPU_GEM_DOMAIN_GTT, 190 &adev->vcn.inst[i].vcpu_bo, 191 &adev->vcn.inst[i].gpu_addr, 192 &adev->vcn.inst[i].cpu_addr); 193 if (r) { 194 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 195 return r; 196 } 197 198 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 199 bo_size - fw_shared_size; 200 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 201 bo_size - fw_shared_size; 202 203 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 204 205 if (amdgpu_vcnfw_log) { 206 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 207 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 208 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 209 } 210 211 if (adev->vcn.indirect_sram) { 212 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 213 AMDGPU_GEM_DOMAIN_VRAM | 214 AMDGPU_GEM_DOMAIN_GTT, 215 &adev->vcn.inst[i].dpg_sram_bo, 216 &adev->vcn.inst[i].dpg_sram_gpu_addr, 217 &adev->vcn.inst[i].dpg_sram_cpu_addr); 218 if (r) { 219 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 220 return r; 221 } 222 } 223 } 224 225 return 0; 226 } 227 228 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 229 { 230 int i, j; 231 232 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 233 if (adev->vcn.harvest_config & (1 << j)) 234 continue; 235 236 if (adev->vcn.indirect_sram) { 237 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 238 &adev->vcn.inst[j].dpg_sram_gpu_addr, 239 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 240 } 241 kvfree(adev->vcn.inst[j].saved_bo); 242 243 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 244 &adev->vcn.inst[j].gpu_addr, 245 (void **)&adev->vcn.inst[j].cpu_addr); 246 247 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 248 249 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 250 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 251 } 252 253 amdgpu_ucode_release(&adev->vcn.fw); 254 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 255 mutex_destroy(&adev->vcn.vcn_pg_lock); 256 257 return 0; 258 } 259 260 /* from vcn4 and above, only unified queue is used */ 261 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) 262 { 263 struct amdgpu_device *adev = ring->adev; 264 bool ret = false; 265 266 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)) 267 ret = true; 268 269 return ret; 270 } 271 272 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 273 { 274 bool ret = false; 275 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 276 277 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 278 ret = true; 279 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) { 280 ret = true; 281 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 282 ret = true; 283 } 284 285 return ret; 286 } 287 288 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 289 { 290 unsigned size; 291 void *ptr; 292 int i, idx; 293 294 cancel_delayed_work_sync(&adev->vcn.idle_work); 295 296 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 297 if (adev->vcn.harvest_config & (1 << i)) 298 continue; 299 if (adev->vcn.inst[i].vcpu_bo == NULL) 300 return 0; 301 302 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 303 ptr = adev->vcn.inst[i].cpu_addr; 304 305 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 306 if (!adev->vcn.inst[i].saved_bo) 307 return -ENOMEM; 308 309 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 310 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 311 drm_dev_exit(idx); 312 } 313 } 314 return 0; 315 } 316 317 int amdgpu_vcn_resume(struct amdgpu_device *adev) 318 { 319 unsigned size; 320 void *ptr; 321 int i, idx; 322 323 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 324 if (adev->vcn.harvest_config & (1 << i)) 325 continue; 326 if (adev->vcn.inst[i].vcpu_bo == NULL) 327 return -EINVAL; 328 329 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 330 ptr = adev->vcn.inst[i].cpu_addr; 331 332 if (adev->vcn.inst[i].saved_bo != NULL) { 333 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 334 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 335 drm_dev_exit(idx); 336 } 337 kvfree(adev->vcn.inst[i].saved_bo); 338 adev->vcn.inst[i].saved_bo = NULL; 339 } else { 340 const struct common_firmware_header *hdr; 341 unsigned offset; 342 343 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 344 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 345 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 346 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 347 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 348 le32_to_cpu(hdr->ucode_size_bytes)); 349 drm_dev_exit(idx); 350 } 351 size -= le32_to_cpu(hdr->ucode_size_bytes); 352 ptr += le32_to_cpu(hdr->ucode_size_bytes); 353 } 354 memset_io(ptr, 0, size); 355 } 356 } 357 return 0; 358 } 359 360 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 361 { 362 struct amdgpu_device *adev = 363 container_of(work, struct amdgpu_device, vcn.idle_work.work); 364 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 365 unsigned int i, j; 366 int r = 0; 367 368 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 369 if (adev->vcn.harvest_config & (1 << j)) 370 continue; 371 372 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 373 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 374 } 375 376 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 377 struct dpg_pause_state new_state; 378 379 if (fence[j] || 380 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 381 new_state.fw_based = VCN_DPG_STATE__PAUSE; 382 else 383 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 384 385 adev->vcn.pause_dpg_mode(adev, j, &new_state); 386 } 387 388 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 389 fences += fence[j]; 390 } 391 392 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 393 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 394 AMD_PG_STATE_GATE); 395 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 396 false); 397 if (r) 398 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 399 } else { 400 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 401 } 402 } 403 404 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 405 { 406 struct amdgpu_device *adev = ring->adev; 407 int r = 0; 408 409 atomic_inc(&adev->vcn.total_submission_cnt); 410 411 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 412 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 413 true); 414 if (r) 415 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 416 } 417 418 mutex_lock(&adev->vcn.vcn_pg_lock); 419 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 420 AMD_PG_STATE_UNGATE); 421 422 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 423 struct dpg_pause_state new_state; 424 425 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 426 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 427 new_state.fw_based = VCN_DPG_STATE__PAUSE; 428 } else { 429 unsigned int fences = 0; 430 unsigned int i; 431 432 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 433 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 434 435 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 436 new_state.fw_based = VCN_DPG_STATE__PAUSE; 437 else 438 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 439 } 440 441 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 442 } 443 mutex_unlock(&adev->vcn.vcn_pg_lock); 444 } 445 446 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 447 { 448 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 449 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 450 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 451 452 atomic_dec(&ring->adev->vcn.total_submission_cnt); 453 454 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 455 } 456 457 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 458 { 459 struct amdgpu_device *adev = ring->adev; 460 uint32_t tmp = 0; 461 unsigned i; 462 int r; 463 464 /* VCN in SRIOV does not support direct register read/write */ 465 if (amdgpu_sriov_vf(adev)) 466 return 0; 467 468 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 469 r = amdgpu_ring_alloc(ring, 3); 470 if (r) 471 return r; 472 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 473 amdgpu_ring_write(ring, 0xDEADBEEF); 474 amdgpu_ring_commit(ring); 475 for (i = 0; i < adev->usec_timeout; i++) { 476 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 477 if (tmp == 0xDEADBEEF) 478 break; 479 udelay(1); 480 } 481 482 if (i >= adev->usec_timeout) 483 r = -ETIMEDOUT; 484 485 return r; 486 } 487 488 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 489 { 490 struct amdgpu_device *adev = ring->adev; 491 uint32_t rptr; 492 unsigned int i; 493 int r; 494 495 if (amdgpu_sriov_vf(adev)) 496 return 0; 497 498 r = amdgpu_ring_alloc(ring, 16); 499 if (r) 500 return r; 501 502 rptr = amdgpu_ring_get_rptr(ring); 503 504 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 505 amdgpu_ring_commit(ring); 506 507 for (i = 0; i < adev->usec_timeout; i++) { 508 if (amdgpu_ring_get_rptr(ring) != rptr) 509 break; 510 udelay(1); 511 } 512 513 if (i >= adev->usec_timeout) 514 r = -ETIMEDOUT; 515 516 return r; 517 } 518 519 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 520 struct amdgpu_ib *ib_msg, 521 struct dma_fence **fence) 522 { 523 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 524 struct amdgpu_device *adev = ring->adev; 525 struct dma_fence *f = NULL; 526 struct amdgpu_job *job; 527 struct amdgpu_ib *ib; 528 int i, r; 529 530 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 531 64, AMDGPU_IB_POOL_DIRECT, 532 &job); 533 if (r) 534 goto err; 535 536 ib = &job->ibs[0]; 537 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 538 ib->ptr[1] = addr; 539 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 540 ib->ptr[3] = addr >> 32; 541 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 542 ib->ptr[5] = 0; 543 for (i = 6; i < 16; i += 2) { 544 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 545 ib->ptr[i+1] = 0; 546 } 547 ib->length_dw = 16; 548 549 r = amdgpu_job_submit_direct(job, ring, &f); 550 if (r) 551 goto err_free; 552 553 amdgpu_ib_free(adev, ib_msg, f); 554 555 if (fence) 556 *fence = dma_fence_get(f); 557 dma_fence_put(f); 558 559 return 0; 560 561 err_free: 562 amdgpu_job_free(job); 563 err: 564 amdgpu_ib_free(adev, ib_msg, f); 565 return r; 566 } 567 568 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 569 struct amdgpu_ib *ib) 570 { 571 struct amdgpu_device *adev = ring->adev; 572 uint32_t *msg; 573 int r, i; 574 575 memset(ib, 0, sizeof(*ib)); 576 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 577 AMDGPU_IB_POOL_DIRECT, 578 ib); 579 if (r) 580 return r; 581 582 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 583 msg[0] = cpu_to_le32(0x00000028); 584 msg[1] = cpu_to_le32(0x00000038); 585 msg[2] = cpu_to_le32(0x00000001); 586 msg[3] = cpu_to_le32(0x00000000); 587 msg[4] = cpu_to_le32(handle); 588 msg[5] = cpu_to_le32(0x00000000); 589 msg[6] = cpu_to_le32(0x00000001); 590 msg[7] = cpu_to_le32(0x00000028); 591 msg[8] = cpu_to_le32(0x00000010); 592 msg[9] = cpu_to_le32(0x00000000); 593 msg[10] = cpu_to_le32(0x00000007); 594 msg[11] = cpu_to_le32(0x00000000); 595 msg[12] = cpu_to_le32(0x00000780); 596 msg[13] = cpu_to_le32(0x00000440); 597 for (i = 14; i < 1024; ++i) 598 msg[i] = cpu_to_le32(0x0); 599 600 return 0; 601 } 602 603 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 604 struct amdgpu_ib *ib) 605 { 606 struct amdgpu_device *adev = ring->adev; 607 uint32_t *msg; 608 int r, i; 609 610 memset(ib, 0, sizeof(*ib)); 611 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 612 AMDGPU_IB_POOL_DIRECT, 613 ib); 614 if (r) 615 return r; 616 617 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 618 msg[0] = cpu_to_le32(0x00000028); 619 msg[1] = cpu_to_le32(0x00000018); 620 msg[2] = cpu_to_le32(0x00000000); 621 msg[3] = cpu_to_le32(0x00000002); 622 msg[4] = cpu_to_le32(handle); 623 msg[5] = cpu_to_le32(0x00000000); 624 for (i = 6; i < 1024; ++i) 625 msg[i] = cpu_to_le32(0x0); 626 627 return 0; 628 } 629 630 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 631 { 632 struct dma_fence *fence = NULL; 633 struct amdgpu_ib ib; 634 long r; 635 636 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 637 if (r) 638 goto error; 639 640 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 641 if (r) 642 goto error; 643 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 644 if (r) 645 goto error; 646 647 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 648 if (r) 649 goto error; 650 651 r = dma_fence_wait_timeout(fence, false, timeout); 652 if (r == 0) 653 r = -ETIMEDOUT; 654 else if (r > 0) 655 r = 0; 656 657 dma_fence_put(fence); 658 error: 659 return r; 660 } 661 662 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 663 uint32_t ib_pack_in_dw, bool enc) 664 { 665 uint32_t *ib_checksum; 666 667 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 668 ib->ptr[ib->length_dw++] = 0x30000002; 669 ib_checksum = &ib->ptr[ib->length_dw++]; 670 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 671 672 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 673 ib->ptr[ib->length_dw++] = 0x30000001; 674 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 675 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 676 677 return ib_checksum; 678 } 679 680 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 681 uint32_t ib_pack_in_dw) 682 { 683 uint32_t i; 684 uint32_t checksum = 0; 685 686 for (i = 0; i < ib_pack_in_dw; i++) 687 checksum += *(*ib_checksum + 2 + i); 688 689 **ib_checksum = checksum; 690 } 691 692 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 693 struct amdgpu_ib *ib_msg, 694 struct dma_fence **fence) 695 { 696 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 697 unsigned int ib_size_dw = 64; 698 struct amdgpu_device *adev = ring->adev; 699 struct dma_fence *f = NULL; 700 struct amdgpu_job *job; 701 struct amdgpu_ib *ib; 702 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 703 bool sq = amdgpu_vcn_using_unified_queue(ring); 704 uint32_t *ib_checksum; 705 uint32_t ib_pack_in_dw; 706 int i, r; 707 708 if (sq) 709 ib_size_dw += 8; 710 711 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 712 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 713 &job); 714 if (r) 715 goto err; 716 717 ib = &job->ibs[0]; 718 ib->length_dw = 0; 719 720 /* single queue headers */ 721 if (sq) { 722 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 723 + 4 + 2; /* engine info + decoding ib in dw */ 724 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 725 } 726 727 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 728 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 729 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 730 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 731 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 732 733 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 734 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 735 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 736 737 for (i = ib->length_dw; i < ib_size_dw; ++i) 738 ib->ptr[i] = 0x0; 739 740 if (sq) 741 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 742 743 r = amdgpu_job_submit_direct(job, ring, &f); 744 if (r) 745 goto err_free; 746 747 amdgpu_ib_free(adev, ib_msg, f); 748 749 if (fence) 750 *fence = dma_fence_get(f); 751 dma_fence_put(f); 752 753 return 0; 754 755 err_free: 756 amdgpu_job_free(job); 757 err: 758 amdgpu_ib_free(adev, ib_msg, f); 759 return r; 760 } 761 762 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 763 { 764 struct dma_fence *fence = NULL; 765 struct amdgpu_ib ib; 766 long r; 767 768 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 769 if (r) 770 goto error; 771 772 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 773 if (r) 774 goto error; 775 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 776 if (r) 777 goto error; 778 779 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 780 if (r) 781 goto error; 782 783 r = dma_fence_wait_timeout(fence, false, timeout); 784 if (r == 0) 785 r = -ETIMEDOUT; 786 else if (r > 0) 787 r = 0; 788 789 dma_fence_put(fence); 790 error: 791 return r; 792 } 793 794 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 795 { 796 struct amdgpu_device *adev = ring->adev; 797 uint32_t rptr; 798 unsigned i; 799 int r; 800 801 if (amdgpu_sriov_vf(adev)) 802 return 0; 803 804 r = amdgpu_ring_alloc(ring, 16); 805 if (r) 806 return r; 807 808 rptr = amdgpu_ring_get_rptr(ring); 809 810 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 811 amdgpu_ring_commit(ring); 812 813 for (i = 0; i < adev->usec_timeout; i++) { 814 if (amdgpu_ring_get_rptr(ring) != rptr) 815 break; 816 udelay(1); 817 } 818 819 if (i >= adev->usec_timeout) 820 r = -ETIMEDOUT; 821 822 return r; 823 } 824 825 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 826 struct amdgpu_ib *ib_msg, 827 struct dma_fence **fence) 828 { 829 unsigned int ib_size_dw = 16; 830 struct amdgpu_job *job; 831 struct amdgpu_ib *ib; 832 struct dma_fence *f = NULL; 833 uint32_t *ib_checksum = NULL; 834 uint64_t addr; 835 bool sq = amdgpu_vcn_using_unified_queue(ring); 836 int i, r; 837 838 if (sq) 839 ib_size_dw += 8; 840 841 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 842 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 843 &job); 844 if (r) 845 return r; 846 847 ib = &job->ibs[0]; 848 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 849 850 ib->length_dw = 0; 851 852 if (sq) 853 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 854 855 ib->ptr[ib->length_dw++] = 0x00000018; 856 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 857 ib->ptr[ib->length_dw++] = handle; 858 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 859 ib->ptr[ib->length_dw++] = addr; 860 ib->ptr[ib->length_dw++] = 0x0000000b; 861 862 ib->ptr[ib->length_dw++] = 0x00000014; 863 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 864 ib->ptr[ib->length_dw++] = 0x0000001c; 865 ib->ptr[ib->length_dw++] = 0x00000000; 866 ib->ptr[ib->length_dw++] = 0x00000000; 867 868 ib->ptr[ib->length_dw++] = 0x00000008; 869 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 870 871 for (i = ib->length_dw; i < ib_size_dw; ++i) 872 ib->ptr[i] = 0x0; 873 874 if (sq) 875 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 876 877 r = amdgpu_job_submit_direct(job, ring, &f); 878 if (r) 879 goto err; 880 881 if (fence) 882 *fence = dma_fence_get(f); 883 dma_fence_put(f); 884 885 return 0; 886 887 err: 888 amdgpu_job_free(job); 889 return r; 890 } 891 892 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 893 struct amdgpu_ib *ib_msg, 894 struct dma_fence **fence) 895 { 896 unsigned int ib_size_dw = 16; 897 struct amdgpu_job *job; 898 struct amdgpu_ib *ib; 899 struct dma_fence *f = NULL; 900 uint32_t *ib_checksum = NULL; 901 uint64_t addr; 902 bool sq = amdgpu_vcn_using_unified_queue(ring); 903 int i, r; 904 905 if (sq) 906 ib_size_dw += 8; 907 908 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 909 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT, 910 &job); 911 if (r) 912 return r; 913 914 ib = &job->ibs[0]; 915 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 916 917 ib->length_dw = 0; 918 919 if (sq) 920 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 921 922 ib->ptr[ib->length_dw++] = 0x00000018; 923 ib->ptr[ib->length_dw++] = 0x00000001; 924 ib->ptr[ib->length_dw++] = handle; 925 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 926 ib->ptr[ib->length_dw++] = addr; 927 ib->ptr[ib->length_dw++] = 0x0000000b; 928 929 ib->ptr[ib->length_dw++] = 0x00000014; 930 ib->ptr[ib->length_dw++] = 0x00000002; 931 ib->ptr[ib->length_dw++] = 0x0000001c; 932 ib->ptr[ib->length_dw++] = 0x00000000; 933 ib->ptr[ib->length_dw++] = 0x00000000; 934 935 ib->ptr[ib->length_dw++] = 0x00000008; 936 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 937 938 for (i = ib->length_dw; i < ib_size_dw; ++i) 939 ib->ptr[i] = 0x0; 940 941 if (sq) 942 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 943 944 r = amdgpu_job_submit_direct(job, ring, &f); 945 if (r) 946 goto err; 947 948 if (fence) 949 *fence = dma_fence_get(f); 950 dma_fence_put(f); 951 952 return 0; 953 954 err: 955 amdgpu_job_free(job); 956 return r; 957 } 958 959 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 960 { 961 struct amdgpu_device *adev = ring->adev; 962 struct dma_fence *fence = NULL; 963 struct amdgpu_ib ib; 964 long r; 965 966 memset(&ib, 0, sizeof(ib)); 967 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 968 AMDGPU_IB_POOL_DIRECT, 969 &ib); 970 if (r) 971 return r; 972 973 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 974 if (r) 975 goto error; 976 977 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 978 if (r) 979 goto error; 980 981 r = dma_fence_wait_timeout(fence, false, timeout); 982 if (r == 0) 983 r = -ETIMEDOUT; 984 else if (r > 0) 985 r = 0; 986 987 error: 988 amdgpu_ib_free(adev, &ib, fence); 989 dma_fence_put(fence); 990 991 return r; 992 } 993 994 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 995 { 996 long r; 997 998 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 999 if (r) 1000 goto error; 1001 1002 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1003 1004 error: 1005 return r; 1006 } 1007 1008 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1009 { 1010 switch(ring) { 1011 case 0: 1012 return AMDGPU_RING_PRIO_0; 1013 case 1: 1014 return AMDGPU_RING_PRIO_1; 1015 case 2: 1016 return AMDGPU_RING_PRIO_2; 1017 default: 1018 return AMDGPU_RING_PRIO_0; 1019 } 1020 } 1021 1022 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 1023 { 1024 int i; 1025 unsigned int idx; 1026 1027 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1028 const struct common_firmware_header *hdr; 1029 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 1030 1031 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1032 if (adev->vcn.harvest_config & (1 << i)) 1033 continue; 1034 /* currently only support 2 FW instances */ 1035 if (i >= 2) { 1036 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1037 break; 1038 } 1039 idx = AMDGPU_UCODE_ID_VCN + i; 1040 adev->firmware.ucode[idx].ucode_id = idx; 1041 adev->firmware.ucode[idx].fw = adev->vcn.fw; 1042 adev->firmware.fw_size += 1043 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1044 } 1045 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 1046 } 1047 } 1048 1049 /* 1050 * debugfs for mapping vcn firmware log buffer. 1051 */ 1052 #if defined(CONFIG_DEBUG_FS) 1053 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1054 size_t size, loff_t *pos) 1055 { 1056 struct amdgpu_vcn_inst *vcn; 1057 void *log_buf; 1058 volatile struct amdgpu_vcn_fwlog *plog; 1059 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1060 unsigned int read_num[2] = {0}; 1061 1062 vcn = file_inode(f)->i_private; 1063 if (!vcn) 1064 return -ENODEV; 1065 1066 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1067 return -EFAULT; 1068 1069 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1070 1071 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1072 read_pos = plog->rptr; 1073 write_pos = plog->wptr; 1074 1075 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1076 return -EFAULT; 1077 1078 if (!size || (read_pos == write_pos)) 1079 return 0; 1080 1081 if (write_pos > read_pos) { 1082 available = write_pos - read_pos; 1083 read_num[0] = min(size, (size_t)available); 1084 } else { 1085 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1086 available = read_num[0] + write_pos - plog->header_size; 1087 if (size > available) 1088 read_num[1] = write_pos - plog->header_size; 1089 else if (size > read_num[0]) 1090 read_num[1] = size - read_num[0]; 1091 else 1092 read_num[0] = size; 1093 } 1094 1095 for (i = 0; i < 2; i++) { 1096 if (read_num[i]) { 1097 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1098 read_pos = plog->header_size; 1099 if (read_num[i] == copy_to_user((buf + read_bytes), 1100 (log_buf + read_pos), read_num[i])) 1101 return -EFAULT; 1102 1103 read_bytes += read_num[i]; 1104 read_pos += read_num[i]; 1105 } 1106 } 1107 1108 plog->rptr = read_pos; 1109 *pos += read_bytes; 1110 return read_bytes; 1111 } 1112 1113 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1114 .owner = THIS_MODULE, 1115 .read = amdgpu_debugfs_vcn_fwlog_read, 1116 .llseek = default_llseek 1117 }; 1118 #endif 1119 1120 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1121 struct amdgpu_vcn_inst *vcn) 1122 { 1123 #if defined(CONFIG_DEBUG_FS) 1124 struct drm_minor *minor = adev_to_drm(adev)->primary; 1125 struct dentry *root = minor->debugfs_root; 1126 char name[32]; 1127 1128 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1129 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn, 1130 &amdgpu_debugfs_vcnfwlog_fops, 1131 AMDGPU_VCNFW_LOG_SIZE); 1132 #endif 1133 } 1134 1135 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1136 { 1137 #if defined(CONFIG_DEBUG_FS) 1138 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1139 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1140 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1141 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1142 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1143 + vcn->fw_shared.log_offset; 1144 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1145 fw_log->is_enabled = 1; 1146 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1147 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1148 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1149 1150 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1151 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1152 log_buf->rptr = log_buf->header_size; 1153 log_buf->wptr = log_buf->header_size; 1154 log_buf->wrapped = 0; 1155 #endif 1156 } 1157 1158 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1159 struct amdgpu_irq_src *source, 1160 struct amdgpu_iv_entry *entry) 1161 { 1162 struct ras_common_if *ras_if = adev->vcn.ras_if; 1163 struct ras_dispatch_if ih_data = { 1164 .entry = entry, 1165 }; 1166 1167 if (!ras_if) 1168 return 0; 1169 1170 if (!amdgpu_sriov_vf(adev)) { 1171 ih_data.head = *ras_if; 1172 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1173 } else { 1174 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) 1175 adev->virt.ops->ras_poison_handler(adev); 1176 else 1177 dev_warn(adev->dev, 1178 "No ras_poison_handler interface in SRIOV for VCN!\n"); 1179 } 1180 1181 return 0; 1182 } 1183 1184 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1185 { 1186 int r, i; 1187 1188 r = amdgpu_ras_block_late_init(adev, ras_block); 1189 if (r) 1190 return r; 1191 1192 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 1193 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1194 if (adev->vcn.harvest_config & (1 << i)) 1195 continue; 1196 1197 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 1198 if (r) 1199 goto late_fini; 1200 } 1201 } 1202 return 0; 1203 1204 late_fini: 1205 amdgpu_ras_block_late_fini(adev, ras_block); 1206 return r; 1207 } 1208 1209 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev) 1210 { 1211 int err; 1212 struct amdgpu_vcn_ras *ras; 1213 1214 if (!adev->vcn.ras) 1215 return 0; 1216 1217 ras = adev->vcn.ras; 1218 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1219 if (err) { 1220 dev_err(adev->dev, "Failed to register vcn ras block!\n"); 1221 return err; 1222 } 1223 1224 strcpy(ras->ras_block.ras_comm.name, "vcn"); 1225 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 1226 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 1227 adev->vcn.ras_if = &ras->ras_block.ras_comm; 1228 1229 if (!ras->ras_block.ras_late_init) 1230 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; 1231 1232 return 0; 1233 } 1234