1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/debugfs.h> 31 #include <drm/drm_drv.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_pm.h" 35 #include "amdgpu_vcn.h" 36 #include "soc15d.h" 37 38 /* Firmware Names */ 39 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 40 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 41 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 42 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 43 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 44 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 45 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 46 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 47 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 48 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 49 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 50 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 51 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 52 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 53 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 54 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 55 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" 56 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" 57 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" 58 59 MODULE_FIRMWARE(FIRMWARE_RAVEN); 60 MODULE_FIRMWARE(FIRMWARE_PICASSO); 61 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 62 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 63 MODULE_FIRMWARE(FIRMWARE_RENOIR); 64 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 65 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 66 MODULE_FIRMWARE(FIRMWARE_NAVI10); 67 MODULE_FIRMWARE(FIRMWARE_NAVI14); 68 MODULE_FIRMWARE(FIRMWARE_NAVI12); 69 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 70 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 71 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 72 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 73 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 74 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 75 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 76 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); 77 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); 78 79 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 80 81 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 82 { 83 unsigned long bo_size; 84 const char *fw_name; 85 const struct common_firmware_header *hdr; 86 unsigned char fw_check; 87 unsigned int fw_shared_size, log_offset; 88 int i, r; 89 90 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 91 mutex_init(&adev->vcn.vcn_pg_lock); 92 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 93 atomic_set(&adev->vcn.total_submission_cnt, 0); 94 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 95 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 96 97 switch (adev->ip_versions[UVD_HWIP][0]) { 98 case IP_VERSION(1, 0, 0): 99 case IP_VERSION(1, 0, 1): 100 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 101 fw_name = FIRMWARE_RAVEN2; 102 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 103 fw_name = FIRMWARE_PICASSO; 104 else 105 fw_name = FIRMWARE_RAVEN; 106 break; 107 case IP_VERSION(2, 5, 0): 108 fw_name = FIRMWARE_ARCTURUS; 109 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 110 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 111 adev->vcn.indirect_sram = true; 112 break; 113 case IP_VERSION(2, 2, 0): 114 if (adev->apu_flags & AMD_APU_IS_RENOIR) 115 fw_name = FIRMWARE_RENOIR; 116 else 117 fw_name = FIRMWARE_GREEN_SARDINE; 118 119 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 120 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 121 adev->vcn.indirect_sram = true; 122 break; 123 case IP_VERSION(2, 6, 0): 124 fw_name = FIRMWARE_ALDEBARAN; 125 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 126 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 127 adev->vcn.indirect_sram = true; 128 break; 129 case IP_VERSION(2, 0, 0): 130 fw_name = FIRMWARE_NAVI10; 131 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 132 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 133 adev->vcn.indirect_sram = true; 134 break; 135 case IP_VERSION(2, 0, 2): 136 if (adev->asic_type == CHIP_NAVI12) 137 fw_name = FIRMWARE_NAVI12; 138 else 139 fw_name = FIRMWARE_NAVI14; 140 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 141 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 142 adev->vcn.indirect_sram = true; 143 break; 144 case IP_VERSION(3, 0, 0): 145 case IP_VERSION(3, 0, 64): 146 case IP_VERSION(3, 0, 192): 147 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 148 fw_name = FIRMWARE_SIENNA_CICHLID; 149 else 150 fw_name = FIRMWARE_NAVY_FLOUNDER; 151 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 152 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 153 adev->vcn.indirect_sram = true; 154 break; 155 case IP_VERSION(3, 0, 2): 156 fw_name = FIRMWARE_VANGOGH; 157 break; 158 case IP_VERSION(3, 0, 16): 159 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 160 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 161 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 162 adev->vcn.indirect_sram = true; 163 break; 164 case IP_VERSION(3, 0, 33): 165 fw_name = FIRMWARE_BEIGE_GOBY; 166 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 167 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 168 adev->vcn.indirect_sram = true; 169 break; 170 case IP_VERSION(3, 1, 1): 171 fw_name = FIRMWARE_YELLOW_CARP; 172 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 173 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 174 adev->vcn.indirect_sram = true; 175 break; 176 case IP_VERSION(3, 1, 2): 177 fw_name = FIRMWARE_VCN_3_1_2; 178 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 179 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 180 adev->vcn.indirect_sram = true; 181 break; 182 case IP_VERSION(4, 0, 0): 183 fw_name = FIRMWARE_VCN4_0_0; 184 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 185 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 186 adev->vcn.indirect_sram = true; 187 break; 188 case IP_VERSION(4, 0, 4): 189 fw_name = FIRMWARE_VCN4_0_4; 190 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 191 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 192 adev->vcn.indirect_sram = true; 193 break; 194 default: 195 return -EINVAL; 196 } 197 198 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 199 if (r) { 200 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 201 fw_name); 202 return r; 203 } 204 205 r = amdgpu_ucode_validate(adev->vcn.fw); 206 if (r) { 207 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 208 fw_name); 209 release_firmware(adev->vcn.fw); 210 adev->vcn.fw = NULL; 211 return r; 212 } 213 214 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 215 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 216 217 /* Bit 20-23, it is encode major and non-zero for new naming convention. 218 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 219 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 220 * is zero in old naming convention, this field is always zero so far. 221 * These four bits are used to tell which naming convention is present. 222 */ 223 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 224 if (fw_check) { 225 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 226 227 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 228 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 229 enc_major = fw_check; 230 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 231 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 232 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 233 enc_major, enc_minor, dec_ver, vep, fw_rev); 234 } else { 235 unsigned int version_major, version_minor, family_id; 236 237 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 238 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 239 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 240 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 241 version_major, version_minor, family_id); 242 } 243 244 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 245 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 246 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 247 248 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){ 249 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); 250 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log); 251 } else { 252 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 253 log_offset = offsetof(struct amdgpu_fw_shared, fw_log); 254 } 255 256 bo_size += fw_shared_size; 257 258 if (amdgpu_vcnfw_log) 259 bo_size += AMDGPU_VCNFW_LOG_SIZE; 260 261 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 262 if (adev->vcn.harvest_config & (1 << i)) 263 continue; 264 265 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 266 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 267 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 268 if (r) { 269 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 270 return r; 271 } 272 273 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + 274 bo_size - fw_shared_size; 275 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + 276 bo_size - fw_shared_size; 277 278 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; 279 280 if (amdgpu_vcnfw_log) { 281 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 282 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; 283 adev->vcn.inst[i].fw_shared.log_offset = log_offset; 284 } 285 286 if (adev->vcn.indirect_sram) { 287 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 288 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 289 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 290 if (r) { 291 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 292 return r; 293 } 294 } 295 } 296 297 return 0; 298 } 299 300 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 301 { 302 int i, j; 303 304 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 305 if (adev->vcn.harvest_config & (1 << j)) 306 continue; 307 308 if (adev->vcn.indirect_sram) { 309 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 310 &adev->vcn.inst[j].dpg_sram_gpu_addr, 311 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 312 } 313 kvfree(adev->vcn.inst[j].saved_bo); 314 315 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 316 &adev->vcn.inst[j].gpu_addr, 317 (void **)&adev->vcn.inst[j].cpu_addr); 318 319 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 320 321 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 322 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 323 } 324 325 release_firmware(adev->vcn.fw); 326 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 327 mutex_destroy(&adev->vcn.vcn_pg_lock); 328 329 return 0; 330 } 331 332 /* from vcn4 and above, only unified queue is used */ 333 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring) 334 { 335 struct amdgpu_device *adev = ring->adev; 336 bool ret = false; 337 338 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)) 339 ret = true; 340 341 return ret; 342 } 343 344 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 345 { 346 bool ret = false; 347 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 348 349 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 350 ret = true; 351 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) { 352 ret = true; 353 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 354 ret = true; 355 } 356 357 return ret; 358 } 359 360 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 361 { 362 unsigned size; 363 void *ptr; 364 int i, idx; 365 366 cancel_delayed_work_sync(&adev->vcn.idle_work); 367 368 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 369 if (adev->vcn.harvest_config & (1 << i)) 370 continue; 371 if (adev->vcn.inst[i].vcpu_bo == NULL) 372 return 0; 373 374 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 375 ptr = adev->vcn.inst[i].cpu_addr; 376 377 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 378 if (!adev->vcn.inst[i].saved_bo) 379 return -ENOMEM; 380 381 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 382 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 383 drm_dev_exit(idx); 384 } 385 } 386 return 0; 387 } 388 389 int amdgpu_vcn_resume(struct amdgpu_device *adev) 390 { 391 unsigned size; 392 void *ptr; 393 int i, idx; 394 395 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 396 if (adev->vcn.harvest_config & (1 << i)) 397 continue; 398 if (adev->vcn.inst[i].vcpu_bo == NULL) 399 return -EINVAL; 400 401 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 402 ptr = adev->vcn.inst[i].cpu_addr; 403 404 if (adev->vcn.inst[i].saved_bo != NULL) { 405 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 406 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 407 drm_dev_exit(idx); 408 } 409 kvfree(adev->vcn.inst[i].saved_bo); 410 adev->vcn.inst[i].saved_bo = NULL; 411 } else { 412 const struct common_firmware_header *hdr; 413 unsigned offset; 414 415 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 416 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 417 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 418 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 419 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 420 le32_to_cpu(hdr->ucode_size_bytes)); 421 drm_dev_exit(idx); 422 } 423 size -= le32_to_cpu(hdr->ucode_size_bytes); 424 ptr += le32_to_cpu(hdr->ucode_size_bytes); 425 } 426 memset_io(ptr, 0, size); 427 } 428 } 429 return 0; 430 } 431 432 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 433 { 434 struct amdgpu_device *adev = 435 container_of(work, struct amdgpu_device, vcn.idle_work.work); 436 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 437 unsigned int i, j; 438 int r = 0; 439 440 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 441 if (adev->vcn.harvest_config & (1 << j)) 442 continue; 443 444 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 445 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 446 } 447 448 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 449 struct dpg_pause_state new_state; 450 451 if (fence[j] || 452 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 453 new_state.fw_based = VCN_DPG_STATE__PAUSE; 454 else 455 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 456 457 adev->vcn.pause_dpg_mode(adev, j, &new_state); 458 } 459 460 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 461 fences += fence[j]; 462 } 463 464 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 465 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 466 AMD_PG_STATE_GATE); 467 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 468 false); 469 if (r) 470 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 471 } else { 472 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 473 } 474 } 475 476 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 477 { 478 struct amdgpu_device *adev = ring->adev; 479 int r = 0; 480 481 atomic_inc(&adev->vcn.total_submission_cnt); 482 483 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 484 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 485 true); 486 if (r) 487 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 488 } 489 490 mutex_lock(&adev->vcn.vcn_pg_lock); 491 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 492 AMD_PG_STATE_UNGATE); 493 494 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 495 struct dpg_pause_state new_state; 496 497 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 498 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 499 new_state.fw_based = VCN_DPG_STATE__PAUSE; 500 } else { 501 unsigned int fences = 0; 502 unsigned int i; 503 504 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 505 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 506 507 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 508 new_state.fw_based = VCN_DPG_STATE__PAUSE; 509 else 510 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 511 } 512 513 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 514 } 515 mutex_unlock(&adev->vcn.vcn_pg_lock); 516 } 517 518 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 519 { 520 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 521 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 522 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 523 524 atomic_dec(&ring->adev->vcn.total_submission_cnt); 525 526 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 527 } 528 529 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 530 { 531 struct amdgpu_device *adev = ring->adev; 532 uint32_t tmp = 0; 533 unsigned i; 534 int r; 535 536 /* VCN in SRIOV does not support direct register read/write */ 537 if (amdgpu_sriov_vf(adev)) 538 return 0; 539 540 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 541 r = amdgpu_ring_alloc(ring, 3); 542 if (r) 543 return r; 544 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 545 amdgpu_ring_write(ring, 0xDEADBEEF); 546 amdgpu_ring_commit(ring); 547 for (i = 0; i < adev->usec_timeout; i++) { 548 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 549 if (tmp == 0xDEADBEEF) 550 break; 551 udelay(1); 552 } 553 554 if (i >= adev->usec_timeout) 555 r = -ETIMEDOUT; 556 557 return r; 558 } 559 560 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 561 { 562 struct amdgpu_device *adev = ring->adev; 563 uint32_t rptr; 564 unsigned int i; 565 int r; 566 567 if (amdgpu_sriov_vf(adev)) 568 return 0; 569 570 r = amdgpu_ring_alloc(ring, 16); 571 if (r) 572 return r; 573 574 rptr = amdgpu_ring_get_rptr(ring); 575 576 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 577 amdgpu_ring_commit(ring); 578 579 for (i = 0; i < adev->usec_timeout; i++) { 580 if (amdgpu_ring_get_rptr(ring) != rptr) 581 break; 582 udelay(1); 583 } 584 585 if (i >= adev->usec_timeout) 586 r = -ETIMEDOUT; 587 588 return r; 589 } 590 591 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 592 struct amdgpu_ib *ib_msg, 593 struct dma_fence **fence) 594 { 595 struct amdgpu_device *adev = ring->adev; 596 struct dma_fence *f = NULL; 597 struct amdgpu_job *job; 598 struct amdgpu_ib *ib; 599 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 600 int i, r; 601 602 r = amdgpu_job_alloc_with_ib(adev, 64, 603 AMDGPU_IB_POOL_DIRECT, &job); 604 if (r) 605 goto err; 606 607 ib = &job->ibs[0]; 608 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 609 ib->ptr[1] = addr; 610 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 611 ib->ptr[3] = addr >> 32; 612 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 613 ib->ptr[5] = 0; 614 for (i = 6; i < 16; i += 2) { 615 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 616 ib->ptr[i+1] = 0; 617 } 618 ib->length_dw = 16; 619 620 r = amdgpu_job_submit_direct(job, ring, &f); 621 if (r) 622 goto err_free; 623 624 amdgpu_ib_free(adev, ib_msg, f); 625 626 if (fence) 627 *fence = dma_fence_get(f); 628 dma_fence_put(f); 629 630 return 0; 631 632 err_free: 633 amdgpu_job_free(job); 634 err: 635 amdgpu_ib_free(adev, ib_msg, f); 636 return r; 637 } 638 639 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 640 struct amdgpu_ib *ib) 641 { 642 struct amdgpu_device *adev = ring->adev; 643 uint32_t *msg; 644 int r, i; 645 646 memset(ib, 0, sizeof(*ib)); 647 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 648 AMDGPU_IB_POOL_DIRECT, 649 ib); 650 if (r) 651 return r; 652 653 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 654 msg[0] = cpu_to_le32(0x00000028); 655 msg[1] = cpu_to_le32(0x00000038); 656 msg[2] = cpu_to_le32(0x00000001); 657 msg[3] = cpu_to_le32(0x00000000); 658 msg[4] = cpu_to_le32(handle); 659 msg[5] = cpu_to_le32(0x00000000); 660 msg[6] = cpu_to_le32(0x00000001); 661 msg[7] = cpu_to_le32(0x00000028); 662 msg[8] = cpu_to_le32(0x00000010); 663 msg[9] = cpu_to_le32(0x00000000); 664 msg[10] = cpu_to_le32(0x00000007); 665 msg[11] = cpu_to_le32(0x00000000); 666 msg[12] = cpu_to_le32(0x00000780); 667 msg[13] = cpu_to_le32(0x00000440); 668 for (i = 14; i < 1024; ++i) 669 msg[i] = cpu_to_le32(0x0); 670 671 return 0; 672 } 673 674 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 675 struct amdgpu_ib *ib) 676 { 677 struct amdgpu_device *adev = ring->adev; 678 uint32_t *msg; 679 int r, i; 680 681 memset(ib, 0, sizeof(*ib)); 682 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 683 AMDGPU_IB_POOL_DIRECT, 684 ib); 685 if (r) 686 return r; 687 688 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 689 msg[0] = cpu_to_le32(0x00000028); 690 msg[1] = cpu_to_le32(0x00000018); 691 msg[2] = cpu_to_le32(0x00000000); 692 msg[3] = cpu_to_le32(0x00000002); 693 msg[4] = cpu_to_le32(handle); 694 msg[5] = cpu_to_le32(0x00000000); 695 for (i = 6; i < 1024; ++i) 696 msg[i] = cpu_to_le32(0x0); 697 698 return 0; 699 } 700 701 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 702 { 703 struct dma_fence *fence = NULL; 704 struct amdgpu_ib ib; 705 long r; 706 707 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 708 if (r) 709 goto error; 710 711 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 712 if (r) 713 goto error; 714 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 715 if (r) 716 goto error; 717 718 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 719 if (r) 720 goto error; 721 722 r = dma_fence_wait_timeout(fence, false, timeout); 723 if (r == 0) 724 r = -ETIMEDOUT; 725 else if (r > 0) 726 r = 0; 727 728 dma_fence_put(fence); 729 error: 730 return r; 731 } 732 733 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, 734 uint32_t ib_pack_in_dw, bool enc) 735 { 736 uint32_t *ib_checksum; 737 738 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ 739 ib->ptr[ib->length_dw++] = 0x30000002; 740 ib_checksum = &ib->ptr[ib->length_dw++]; 741 ib->ptr[ib->length_dw++] = ib_pack_in_dw; 742 743 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ 744 ib->ptr[ib->length_dw++] = 0x30000001; 745 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; 746 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); 747 748 return ib_checksum; 749 } 750 751 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum, 752 uint32_t ib_pack_in_dw) 753 { 754 uint32_t i; 755 uint32_t checksum = 0; 756 757 for (i = 0; i < ib_pack_in_dw; i++) 758 checksum += *(*ib_checksum + 2 + i); 759 760 **ib_checksum = checksum; 761 } 762 763 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 764 struct amdgpu_ib *ib_msg, 765 struct dma_fence **fence) 766 { 767 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 768 unsigned int ib_size_dw = 64; 769 struct amdgpu_device *adev = ring->adev; 770 struct dma_fence *f = NULL; 771 struct amdgpu_job *job; 772 struct amdgpu_ib *ib; 773 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 774 bool sq = amdgpu_vcn_using_unified_queue(ring); 775 uint32_t *ib_checksum; 776 uint32_t ib_pack_in_dw; 777 int i, r; 778 779 if (sq) 780 ib_size_dw += 8; 781 782 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 783 AMDGPU_IB_POOL_DIRECT, &job); 784 if (r) 785 goto err; 786 787 ib = &job->ibs[0]; 788 ib->length_dw = 0; 789 790 /* single queue headers */ 791 if (sq) { 792 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t) 793 + 4 + 2; /* engine info + decoding ib in dw */ 794 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); 795 } 796 797 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 798 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 799 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 800 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 801 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 802 803 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 804 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 805 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 806 807 for (i = ib->length_dw; i < ib_size_dw; ++i) 808 ib->ptr[i] = 0x0; 809 810 if (sq) 811 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); 812 813 r = amdgpu_job_submit_direct(job, ring, &f); 814 if (r) 815 goto err_free; 816 817 amdgpu_ib_free(adev, ib_msg, f); 818 819 if (fence) 820 *fence = dma_fence_get(f); 821 dma_fence_put(f); 822 823 return 0; 824 825 err_free: 826 amdgpu_job_free(job); 827 err: 828 amdgpu_ib_free(adev, ib_msg, f); 829 return r; 830 } 831 832 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 833 { 834 struct dma_fence *fence = NULL; 835 struct amdgpu_ib ib; 836 long r; 837 838 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 839 if (r) 840 goto error; 841 842 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 843 if (r) 844 goto error; 845 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 846 if (r) 847 goto error; 848 849 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 850 if (r) 851 goto error; 852 853 r = dma_fence_wait_timeout(fence, false, timeout); 854 if (r == 0) 855 r = -ETIMEDOUT; 856 else if (r > 0) 857 r = 0; 858 859 dma_fence_put(fence); 860 error: 861 return r; 862 } 863 864 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 865 { 866 struct amdgpu_device *adev = ring->adev; 867 uint32_t rptr; 868 unsigned i; 869 int r; 870 871 if (amdgpu_sriov_vf(adev)) 872 return 0; 873 874 r = amdgpu_ring_alloc(ring, 16); 875 if (r) 876 return r; 877 878 rptr = amdgpu_ring_get_rptr(ring); 879 880 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 881 amdgpu_ring_commit(ring); 882 883 for (i = 0; i < adev->usec_timeout; i++) { 884 if (amdgpu_ring_get_rptr(ring) != rptr) 885 break; 886 udelay(1); 887 } 888 889 if (i >= adev->usec_timeout) 890 r = -ETIMEDOUT; 891 892 return r; 893 } 894 895 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 896 struct amdgpu_ib *ib_msg, 897 struct dma_fence **fence) 898 { 899 unsigned int ib_size_dw = 16; 900 struct amdgpu_job *job; 901 struct amdgpu_ib *ib; 902 struct dma_fence *f = NULL; 903 uint32_t *ib_checksum = NULL; 904 uint64_t addr; 905 bool sq = amdgpu_vcn_using_unified_queue(ring); 906 int i, r; 907 908 if (sq) 909 ib_size_dw += 8; 910 911 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 912 AMDGPU_IB_POOL_DIRECT, &job); 913 if (r) 914 return r; 915 916 ib = &job->ibs[0]; 917 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 918 919 ib->length_dw = 0; 920 921 if (sq) 922 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 923 924 ib->ptr[ib->length_dw++] = 0x00000018; 925 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 926 ib->ptr[ib->length_dw++] = handle; 927 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 928 ib->ptr[ib->length_dw++] = addr; 929 ib->ptr[ib->length_dw++] = 0x0000000b; 930 931 ib->ptr[ib->length_dw++] = 0x00000014; 932 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 933 ib->ptr[ib->length_dw++] = 0x0000001c; 934 ib->ptr[ib->length_dw++] = 0x00000000; 935 ib->ptr[ib->length_dw++] = 0x00000000; 936 937 ib->ptr[ib->length_dw++] = 0x00000008; 938 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 939 940 for (i = ib->length_dw; i < ib_size_dw; ++i) 941 ib->ptr[i] = 0x0; 942 943 if (sq) 944 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 945 946 r = amdgpu_job_submit_direct(job, ring, &f); 947 if (r) 948 goto err; 949 950 if (fence) 951 *fence = dma_fence_get(f); 952 dma_fence_put(f); 953 954 return 0; 955 956 err: 957 amdgpu_job_free(job); 958 return r; 959 } 960 961 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 962 struct amdgpu_ib *ib_msg, 963 struct dma_fence **fence) 964 { 965 unsigned int ib_size_dw = 16; 966 struct amdgpu_job *job; 967 struct amdgpu_ib *ib; 968 struct dma_fence *f = NULL; 969 uint32_t *ib_checksum = NULL; 970 uint64_t addr; 971 bool sq = amdgpu_vcn_using_unified_queue(ring); 972 int i, r; 973 974 if (sq) 975 ib_size_dw += 8; 976 977 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 978 AMDGPU_IB_POOL_DIRECT, &job); 979 if (r) 980 return r; 981 982 ib = &job->ibs[0]; 983 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 984 985 ib->length_dw = 0; 986 987 if (sq) 988 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); 989 990 ib->ptr[ib->length_dw++] = 0x00000018; 991 ib->ptr[ib->length_dw++] = 0x00000001; 992 ib->ptr[ib->length_dw++] = handle; 993 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 994 ib->ptr[ib->length_dw++] = addr; 995 ib->ptr[ib->length_dw++] = 0x0000000b; 996 997 ib->ptr[ib->length_dw++] = 0x00000014; 998 ib->ptr[ib->length_dw++] = 0x00000002; 999 ib->ptr[ib->length_dw++] = 0x0000001c; 1000 ib->ptr[ib->length_dw++] = 0x00000000; 1001 ib->ptr[ib->length_dw++] = 0x00000000; 1002 1003 ib->ptr[ib->length_dw++] = 0x00000008; 1004 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 1005 1006 for (i = ib->length_dw; i < ib_size_dw; ++i) 1007 ib->ptr[i] = 0x0; 1008 1009 if (sq) 1010 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); 1011 1012 r = amdgpu_job_submit_direct(job, ring, &f); 1013 if (r) 1014 goto err; 1015 1016 if (fence) 1017 *fence = dma_fence_get(f); 1018 dma_fence_put(f); 1019 1020 return 0; 1021 1022 err: 1023 amdgpu_job_free(job); 1024 return r; 1025 } 1026 1027 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1028 { 1029 struct amdgpu_device *adev = ring->adev; 1030 struct dma_fence *fence = NULL; 1031 struct amdgpu_ib ib; 1032 long r; 1033 1034 memset(&ib, 0, sizeof(ib)); 1035 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 1036 AMDGPU_IB_POOL_DIRECT, 1037 &ib); 1038 if (r) 1039 return r; 1040 1041 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 1042 if (r) 1043 goto error; 1044 1045 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 1046 if (r) 1047 goto error; 1048 1049 r = dma_fence_wait_timeout(fence, false, timeout); 1050 if (r == 0) 1051 r = -ETIMEDOUT; 1052 else if (r > 0) 1053 r = 0; 1054 1055 error: 1056 amdgpu_ib_free(adev, &ib, fence); 1057 dma_fence_put(fence); 1058 1059 return r; 1060 } 1061 1062 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1063 { 1064 long r; 1065 1066 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); 1067 if (r) 1068 goto error; 1069 1070 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout); 1071 1072 error: 1073 return r; 1074 } 1075 1076 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 1077 { 1078 switch(ring) { 1079 case 0: 1080 return AMDGPU_RING_PRIO_0; 1081 case 1: 1082 return AMDGPU_RING_PRIO_1; 1083 case 2: 1084 return AMDGPU_RING_PRIO_2; 1085 default: 1086 return AMDGPU_RING_PRIO_0; 1087 } 1088 } 1089 1090 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 1091 { 1092 int i; 1093 unsigned int idx; 1094 1095 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1096 const struct common_firmware_header *hdr; 1097 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 1098 1099 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1100 if (adev->vcn.harvest_config & (1 << i)) 1101 continue; 1102 /* currently only support 2 FW instances */ 1103 if (i >= 2) { 1104 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 1105 break; 1106 } 1107 idx = AMDGPU_UCODE_ID_VCN + i; 1108 adev->firmware.ucode[idx].ucode_id = idx; 1109 adev->firmware.ucode[idx].fw = adev->vcn.fw; 1110 adev->firmware.fw_size += 1111 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 1112 } 1113 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 1114 } 1115 } 1116 1117 /* 1118 * debugfs for mapping vcn firmware log buffer. 1119 */ 1120 #if defined(CONFIG_DEBUG_FS) 1121 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, 1122 size_t size, loff_t *pos) 1123 { 1124 struct amdgpu_vcn_inst *vcn; 1125 void *log_buf; 1126 volatile struct amdgpu_vcn_fwlog *plog; 1127 unsigned int read_pos, write_pos, available, i, read_bytes = 0; 1128 unsigned int read_num[2] = {0}; 1129 1130 vcn = file_inode(f)->i_private; 1131 if (!vcn) 1132 return -ENODEV; 1133 1134 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) 1135 return -EFAULT; 1136 1137 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1138 1139 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; 1140 read_pos = plog->rptr; 1141 write_pos = plog->wptr; 1142 1143 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE) 1144 return -EFAULT; 1145 1146 if (!size || (read_pos == write_pos)) 1147 return 0; 1148 1149 if (write_pos > read_pos) { 1150 available = write_pos - read_pos; 1151 read_num[0] = min(size, (size_t)available); 1152 } else { 1153 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos; 1154 available = read_num[0] + write_pos - plog->header_size; 1155 if (size > available) 1156 read_num[1] = write_pos - plog->header_size; 1157 else if (size > read_num[0]) 1158 read_num[1] = size - read_num[0]; 1159 else 1160 read_num[0] = size; 1161 } 1162 1163 for (i = 0; i < 2; i++) { 1164 if (read_num[i]) { 1165 if (read_pos == AMDGPU_VCNFW_LOG_SIZE) 1166 read_pos = plog->header_size; 1167 if (read_num[i] == copy_to_user((buf + read_bytes), 1168 (log_buf + read_pos), read_num[i])) 1169 return -EFAULT; 1170 1171 read_bytes += read_num[i]; 1172 read_pos += read_num[i]; 1173 } 1174 } 1175 1176 plog->rptr = read_pos; 1177 *pos += read_bytes; 1178 return read_bytes; 1179 } 1180 1181 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = { 1182 .owner = THIS_MODULE, 1183 .read = amdgpu_debugfs_vcn_fwlog_read, 1184 .llseek = default_llseek 1185 }; 1186 #endif 1187 1188 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, 1189 struct amdgpu_vcn_inst *vcn) 1190 { 1191 #if defined(CONFIG_DEBUG_FS) 1192 struct drm_minor *minor = adev_to_drm(adev)->primary; 1193 struct dentry *root = minor->debugfs_root; 1194 char name[32]; 1195 1196 sprintf(name, "amdgpu_vcn_%d_fwlog", i); 1197 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn, 1198 &amdgpu_debugfs_vcnfwlog_fops, 1199 AMDGPU_VCNFW_LOG_SIZE); 1200 #endif 1201 } 1202 1203 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) 1204 { 1205 #if defined(CONFIG_DEBUG_FS) 1206 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; 1207 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; 1208 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; 1209 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; 1210 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr 1211 + vcn->fw_shared.log_offset; 1212 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); 1213 fw_log->is_enabled = 1; 1214 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF); 1215 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32); 1216 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE); 1217 1218 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog); 1219 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE; 1220 log_buf->rptr = log_buf->header_size; 1221 log_buf->wptr = log_buf->header_size; 1222 log_buf->wrapped = 0; 1223 #endif 1224 } 1225 1226 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 1227 struct amdgpu_irq_src *source, 1228 struct amdgpu_iv_entry *entry) 1229 { 1230 struct ras_common_if *ras_if = adev->vcn.ras_if; 1231 struct ras_dispatch_if ih_data = { 1232 .entry = entry, 1233 }; 1234 1235 if (!ras_if) 1236 return 0; 1237 1238 ih_data.head = *ras_if; 1239 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 1240 1241 return 0; 1242 } 1243