1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <drm/drm_drv.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_vcn.h" 35 #include "soc15d.h" 36 37 /* Firmware Names */ 38 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 39 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 40 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 41 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 42 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 43 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 44 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 45 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 46 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 48 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 49 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 50 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 51 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 52 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 53 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 54 55 MODULE_FIRMWARE(FIRMWARE_RAVEN); 56 MODULE_FIRMWARE(FIRMWARE_PICASSO); 57 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 59 MODULE_FIRMWARE(FIRMWARE_RENOIR); 60 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 61 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 62 MODULE_FIRMWARE(FIRMWARE_NAVI10); 63 MODULE_FIRMWARE(FIRMWARE_NAVI14); 64 MODULE_FIRMWARE(FIRMWARE_NAVI12); 65 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 66 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 67 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 68 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 69 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 70 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 71 72 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 73 74 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 75 { 76 unsigned long bo_size; 77 const char *fw_name; 78 const struct common_firmware_header *hdr; 79 unsigned char fw_check; 80 int i, r; 81 82 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 83 mutex_init(&adev->vcn.vcn_pg_lock); 84 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 85 atomic_set(&adev->vcn.total_submission_cnt, 0); 86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 87 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 88 89 switch (adev->ip_versions[UVD_HWIP][0]) { 90 case IP_VERSION(1, 0, 0): 91 case IP_VERSION(1, 0, 1): 92 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 93 fw_name = FIRMWARE_RAVEN2; 94 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 95 fw_name = FIRMWARE_PICASSO; 96 else 97 fw_name = FIRMWARE_RAVEN; 98 break; 99 case IP_VERSION(2, 5, 0): 100 fw_name = FIRMWARE_ARCTURUS; 101 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 102 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 103 adev->vcn.indirect_sram = true; 104 break; 105 case IP_VERSION(2, 2, 0): 106 if (adev->apu_flags & AMD_APU_IS_RENOIR) 107 fw_name = FIRMWARE_RENOIR; 108 else 109 fw_name = FIRMWARE_GREEN_SARDINE; 110 111 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 112 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 113 adev->vcn.indirect_sram = true; 114 break; 115 case IP_VERSION(2, 6, 0): 116 fw_name = FIRMWARE_ALDEBARAN; 117 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 118 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 119 adev->vcn.indirect_sram = true; 120 break; 121 case IP_VERSION(2, 0, 0): 122 fw_name = FIRMWARE_NAVI10; 123 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 124 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 125 adev->vcn.indirect_sram = true; 126 break; 127 case IP_VERSION(2, 0, 2): 128 if (adev->asic_type == CHIP_NAVI12) 129 fw_name = FIRMWARE_NAVI12; 130 else 131 fw_name = FIRMWARE_NAVI14; 132 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 133 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 134 adev->vcn.indirect_sram = true; 135 break; 136 case IP_VERSION(3, 0, 0): 137 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 138 fw_name = FIRMWARE_SIENNA_CICHLID; 139 else 140 fw_name = FIRMWARE_NAVY_FLOUNDER; 141 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 142 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 143 adev->vcn.indirect_sram = true; 144 break; 145 case IP_VERSION(3, 0, 2): 146 fw_name = FIRMWARE_VANGOGH; 147 break; 148 case IP_VERSION(3, 0, 16): 149 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 150 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 151 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 152 adev->vcn.indirect_sram = true; 153 break; 154 case IP_VERSION(3, 0, 33): 155 fw_name = FIRMWARE_BEIGE_GOBY; 156 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 157 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 158 adev->vcn.indirect_sram = true; 159 break; 160 case IP_VERSION(3, 1, 1): 161 fw_name = FIRMWARE_YELLOW_CARP; 162 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 163 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 164 adev->vcn.indirect_sram = true; 165 break; 166 default: 167 return -EINVAL; 168 } 169 170 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 171 if (r) { 172 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 173 fw_name); 174 return r; 175 } 176 177 r = amdgpu_ucode_validate(adev->vcn.fw); 178 if (r) { 179 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 180 fw_name); 181 release_firmware(adev->vcn.fw); 182 adev->vcn.fw = NULL; 183 return r; 184 } 185 186 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 187 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 188 189 /* Bit 20-23, it is encode major and non-zero for new naming convention. 190 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 191 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 192 * is zero in old naming convention, this field is always zero so far. 193 * These four bits are used to tell which naming convention is present. 194 */ 195 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 196 if (fw_check) { 197 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 198 199 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 200 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 201 enc_major = fw_check; 202 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 203 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 204 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 205 enc_major, enc_minor, dec_ver, vep, fw_rev); 206 } else { 207 unsigned int version_major, version_minor, family_id; 208 209 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 210 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 211 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 212 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 213 version_major, version_minor, family_id); 214 } 215 216 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 218 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 219 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 220 221 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 222 if (adev->vcn.harvest_config & (1 << i)) 223 continue; 224 225 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 226 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 227 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 228 if (r) { 229 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 230 return r; 231 } 232 233 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr + 234 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 235 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr + 236 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 237 238 if (adev->vcn.indirect_sram) { 239 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 240 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 241 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 242 if (r) { 243 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 244 return r; 245 } 246 } 247 } 248 249 return 0; 250 } 251 252 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 253 { 254 int i, j; 255 256 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 257 if (adev->vcn.harvest_config & (1 << j)) 258 continue; 259 260 if (adev->vcn.indirect_sram) { 261 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 262 &adev->vcn.inst[j].dpg_sram_gpu_addr, 263 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 264 } 265 kvfree(adev->vcn.inst[j].saved_bo); 266 267 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 268 &adev->vcn.inst[j].gpu_addr, 269 (void **)&adev->vcn.inst[j].cpu_addr); 270 271 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 272 273 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 274 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 275 } 276 277 release_firmware(adev->vcn.fw); 278 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 279 mutex_destroy(&adev->vcn.vcn_pg_lock); 280 281 return 0; 282 } 283 284 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 285 { 286 bool ret = false; 287 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 288 289 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 290 ret = true; 291 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) { 292 ret = true; 293 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 294 ret = true; 295 } 296 297 return ret; 298 } 299 300 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 301 { 302 unsigned size; 303 void *ptr; 304 int i, idx; 305 306 cancel_delayed_work_sync(&adev->vcn.idle_work); 307 308 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 309 if (adev->vcn.harvest_config & (1 << i)) 310 continue; 311 if (adev->vcn.inst[i].vcpu_bo == NULL) 312 return 0; 313 314 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 315 ptr = adev->vcn.inst[i].cpu_addr; 316 317 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 318 if (!adev->vcn.inst[i].saved_bo) 319 return -ENOMEM; 320 321 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 322 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 323 drm_dev_exit(idx); 324 } 325 } 326 return 0; 327 } 328 329 int amdgpu_vcn_resume(struct amdgpu_device *adev) 330 { 331 unsigned size; 332 void *ptr; 333 int i, idx; 334 335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 336 if (adev->vcn.harvest_config & (1 << i)) 337 continue; 338 if (adev->vcn.inst[i].vcpu_bo == NULL) 339 return -EINVAL; 340 341 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 342 ptr = adev->vcn.inst[i].cpu_addr; 343 344 if (adev->vcn.inst[i].saved_bo != NULL) { 345 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 346 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 347 drm_dev_exit(idx); 348 } 349 kvfree(adev->vcn.inst[i].saved_bo); 350 adev->vcn.inst[i].saved_bo = NULL; 351 } else { 352 const struct common_firmware_header *hdr; 353 unsigned offset; 354 355 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 356 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 357 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 358 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 359 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 360 le32_to_cpu(hdr->ucode_size_bytes)); 361 drm_dev_exit(idx); 362 } 363 size -= le32_to_cpu(hdr->ucode_size_bytes); 364 ptr += le32_to_cpu(hdr->ucode_size_bytes); 365 } 366 memset_io(ptr, 0, size); 367 } 368 } 369 return 0; 370 } 371 372 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 373 { 374 struct amdgpu_device *adev = 375 container_of(work, struct amdgpu_device, vcn.idle_work.work); 376 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 377 unsigned int i, j; 378 int r = 0; 379 380 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 381 if (adev->vcn.harvest_config & (1 << j)) 382 continue; 383 384 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 385 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 386 } 387 388 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 389 struct dpg_pause_state new_state; 390 391 if (fence[j] || 392 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 393 new_state.fw_based = VCN_DPG_STATE__PAUSE; 394 else 395 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 396 397 adev->vcn.pause_dpg_mode(adev, j, &new_state); 398 } 399 400 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 401 fences += fence[j]; 402 } 403 404 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 405 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 406 AMD_PG_STATE_GATE); 407 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 408 false); 409 if (r) 410 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 411 } else { 412 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 413 } 414 } 415 416 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 417 { 418 struct amdgpu_device *adev = ring->adev; 419 int r = 0; 420 421 atomic_inc(&adev->vcn.total_submission_cnt); 422 423 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 424 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 425 true); 426 if (r) 427 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 428 } 429 430 mutex_lock(&adev->vcn.vcn_pg_lock); 431 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 432 AMD_PG_STATE_UNGATE); 433 434 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 435 struct dpg_pause_state new_state; 436 437 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 438 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 439 new_state.fw_based = VCN_DPG_STATE__PAUSE; 440 } else { 441 unsigned int fences = 0; 442 unsigned int i; 443 444 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 445 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 446 447 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 448 new_state.fw_based = VCN_DPG_STATE__PAUSE; 449 else 450 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 451 } 452 453 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 454 } 455 mutex_unlock(&adev->vcn.vcn_pg_lock); 456 } 457 458 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 459 { 460 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 461 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 462 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 463 464 atomic_dec(&ring->adev->vcn.total_submission_cnt); 465 466 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 467 } 468 469 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 470 { 471 struct amdgpu_device *adev = ring->adev; 472 uint32_t tmp = 0; 473 unsigned i; 474 int r; 475 476 /* VCN in SRIOV does not support direct register read/write */ 477 if (amdgpu_sriov_vf(adev)) 478 return 0; 479 480 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 481 r = amdgpu_ring_alloc(ring, 3); 482 if (r) 483 return r; 484 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 485 amdgpu_ring_write(ring, 0xDEADBEEF); 486 amdgpu_ring_commit(ring); 487 for (i = 0; i < adev->usec_timeout; i++) { 488 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 489 if (tmp == 0xDEADBEEF) 490 break; 491 udelay(1); 492 } 493 494 if (i >= adev->usec_timeout) 495 r = -ETIMEDOUT; 496 497 return r; 498 } 499 500 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 501 { 502 struct amdgpu_device *adev = ring->adev; 503 uint32_t rptr; 504 unsigned int i; 505 int r; 506 507 if (amdgpu_sriov_vf(adev)) 508 return 0; 509 510 r = amdgpu_ring_alloc(ring, 16); 511 if (r) 512 return r; 513 514 rptr = amdgpu_ring_get_rptr(ring); 515 516 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 517 amdgpu_ring_commit(ring); 518 519 for (i = 0; i < adev->usec_timeout; i++) { 520 if (amdgpu_ring_get_rptr(ring) != rptr) 521 break; 522 udelay(1); 523 } 524 525 if (i >= adev->usec_timeout) 526 r = -ETIMEDOUT; 527 528 return r; 529 } 530 531 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 532 struct amdgpu_ib *ib_msg, 533 struct dma_fence **fence) 534 { 535 struct amdgpu_device *adev = ring->adev; 536 struct dma_fence *f = NULL; 537 struct amdgpu_job *job; 538 struct amdgpu_ib *ib; 539 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 540 int i, r; 541 542 r = amdgpu_job_alloc_with_ib(adev, 64, 543 AMDGPU_IB_POOL_DIRECT, &job); 544 if (r) 545 goto err; 546 547 ib = &job->ibs[0]; 548 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 549 ib->ptr[1] = addr; 550 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 551 ib->ptr[3] = addr >> 32; 552 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 553 ib->ptr[5] = 0; 554 for (i = 6; i < 16; i += 2) { 555 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 556 ib->ptr[i+1] = 0; 557 } 558 ib->length_dw = 16; 559 560 r = amdgpu_job_submit_direct(job, ring, &f); 561 if (r) 562 goto err_free; 563 564 amdgpu_ib_free(adev, ib_msg, f); 565 566 if (fence) 567 *fence = dma_fence_get(f); 568 dma_fence_put(f); 569 570 return 0; 571 572 err_free: 573 amdgpu_job_free(job); 574 err: 575 amdgpu_ib_free(adev, ib_msg, f); 576 return r; 577 } 578 579 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 580 struct amdgpu_ib *ib) 581 { 582 struct amdgpu_device *adev = ring->adev; 583 uint32_t *msg; 584 int r, i; 585 586 memset(ib, 0, sizeof(*ib)); 587 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 588 AMDGPU_IB_POOL_DIRECT, 589 ib); 590 if (r) 591 return r; 592 593 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 594 msg[0] = cpu_to_le32(0x00000028); 595 msg[1] = cpu_to_le32(0x00000038); 596 msg[2] = cpu_to_le32(0x00000001); 597 msg[3] = cpu_to_le32(0x00000000); 598 msg[4] = cpu_to_le32(handle); 599 msg[5] = cpu_to_le32(0x00000000); 600 msg[6] = cpu_to_le32(0x00000001); 601 msg[7] = cpu_to_le32(0x00000028); 602 msg[8] = cpu_to_le32(0x00000010); 603 msg[9] = cpu_to_le32(0x00000000); 604 msg[10] = cpu_to_le32(0x00000007); 605 msg[11] = cpu_to_le32(0x00000000); 606 msg[12] = cpu_to_le32(0x00000780); 607 msg[13] = cpu_to_le32(0x00000440); 608 for (i = 14; i < 1024; ++i) 609 msg[i] = cpu_to_le32(0x0); 610 611 return 0; 612 } 613 614 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 615 struct amdgpu_ib *ib) 616 { 617 struct amdgpu_device *adev = ring->adev; 618 uint32_t *msg; 619 int r, i; 620 621 memset(ib, 0, sizeof(*ib)); 622 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 623 AMDGPU_IB_POOL_DIRECT, 624 ib); 625 if (r) 626 return r; 627 628 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 629 msg[0] = cpu_to_le32(0x00000028); 630 msg[1] = cpu_to_le32(0x00000018); 631 msg[2] = cpu_to_le32(0x00000000); 632 msg[3] = cpu_to_le32(0x00000002); 633 msg[4] = cpu_to_le32(handle); 634 msg[5] = cpu_to_le32(0x00000000); 635 for (i = 6; i < 1024; ++i) 636 msg[i] = cpu_to_le32(0x0); 637 638 return 0; 639 } 640 641 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 642 { 643 struct dma_fence *fence = NULL; 644 struct amdgpu_ib ib; 645 long r; 646 647 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 648 if (r) 649 goto error; 650 651 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 652 if (r) 653 goto error; 654 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 655 if (r) 656 goto error; 657 658 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 659 if (r) 660 goto error; 661 662 r = dma_fence_wait_timeout(fence, false, timeout); 663 if (r == 0) 664 r = -ETIMEDOUT; 665 else if (r > 0) 666 r = 0; 667 668 dma_fence_put(fence); 669 error: 670 return r; 671 } 672 673 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 674 struct amdgpu_ib *ib_msg, 675 struct dma_fence **fence) 676 { 677 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 678 const unsigned int ib_size_dw = 64; 679 struct amdgpu_device *adev = ring->adev; 680 struct dma_fence *f = NULL; 681 struct amdgpu_job *job; 682 struct amdgpu_ib *ib; 683 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 684 int i, r; 685 686 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 687 AMDGPU_IB_POOL_DIRECT, &job); 688 if (r) 689 goto err; 690 691 ib = &job->ibs[0]; 692 ib->length_dw = 0; 693 694 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 695 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 696 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 697 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 698 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 699 700 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 701 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 702 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 703 704 for (i = ib->length_dw; i < ib_size_dw; ++i) 705 ib->ptr[i] = 0x0; 706 707 r = amdgpu_job_submit_direct(job, ring, &f); 708 if (r) 709 goto err_free; 710 711 amdgpu_ib_free(adev, ib_msg, f); 712 713 if (fence) 714 *fence = dma_fence_get(f); 715 dma_fence_put(f); 716 717 return 0; 718 719 err_free: 720 amdgpu_job_free(job); 721 err: 722 amdgpu_ib_free(adev, ib_msg, f); 723 return r; 724 } 725 726 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 727 { 728 struct dma_fence *fence = NULL; 729 struct amdgpu_ib ib; 730 long r; 731 732 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 733 if (r) 734 goto error; 735 736 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 737 if (r) 738 goto error; 739 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 740 if (r) 741 goto error; 742 743 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 744 if (r) 745 goto error; 746 747 r = dma_fence_wait_timeout(fence, false, timeout); 748 if (r == 0) 749 r = -ETIMEDOUT; 750 else if (r > 0) 751 r = 0; 752 753 dma_fence_put(fence); 754 error: 755 return r; 756 } 757 758 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 759 { 760 struct amdgpu_device *adev = ring->adev; 761 uint32_t rptr; 762 unsigned i; 763 int r; 764 765 if (amdgpu_sriov_vf(adev)) 766 return 0; 767 768 r = amdgpu_ring_alloc(ring, 16); 769 if (r) 770 return r; 771 772 rptr = amdgpu_ring_get_rptr(ring); 773 774 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 775 amdgpu_ring_commit(ring); 776 777 for (i = 0; i < adev->usec_timeout; i++) { 778 if (amdgpu_ring_get_rptr(ring) != rptr) 779 break; 780 udelay(1); 781 } 782 783 if (i >= adev->usec_timeout) 784 r = -ETIMEDOUT; 785 786 return r; 787 } 788 789 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 790 struct amdgpu_ib *ib_msg, 791 struct dma_fence **fence) 792 { 793 const unsigned ib_size_dw = 16; 794 struct amdgpu_job *job; 795 struct amdgpu_ib *ib; 796 struct dma_fence *f = NULL; 797 uint64_t addr; 798 int i, r; 799 800 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 801 AMDGPU_IB_POOL_DIRECT, &job); 802 if (r) 803 return r; 804 805 ib = &job->ibs[0]; 806 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 807 808 ib->length_dw = 0; 809 ib->ptr[ib->length_dw++] = 0x00000018; 810 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 811 ib->ptr[ib->length_dw++] = handle; 812 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 813 ib->ptr[ib->length_dw++] = addr; 814 ib->ptr[ib->length_dw++] = 0x0000000b; 815 816 ib->ptr[ib->length_dw++] = 0x00000014; 817 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 818 ib->ptr[ib->length_dw++] = 0x0000001c; 819 ib->ptr[ib->length_dw++] = 0x00000000; 820 ib->ptr[ib->length_dw++] = 0x00000000; 821 822 ib->ptr[ib->length_dw++] = 0x00000008; 823 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 824 825 for (i = ib->length_dw; i < ib_size_dw; ++i) 826 ib->ptr[i] = 0x0; 827 828 r = amdgpu_job_submit_direct(job, ring, &f); 829 if (r) 830 goto err; 831 832 if (fence) 833 *fence = dma_fence_get(f); 834 dma_fence_put(f); 835 836 return 0; 837 838 err: 839 amdgpu_job_free(job); 840 return r; 841 } 842 843 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 844 struct amdgpu_ib *ib_msg, 845 struct dma_fence **fence) 846 { 847 const unsigned ib_size_dw = 16; 848 struct amdgpu_job *job; 849 struct amdgpu_ib *ib; 850 struct dma_fence *f = NULL; 851 uint64_t addr; 852 int i, r; 853 854 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 855 AMDGPU_IB_POOL_DIRECT, &job); 856 if (r) 857 return r; 858 859 ib = &job->ibs[0]; 860 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 861 862 ib->length_dw = 0; 863 ib->ptr[ib->length_dw++] = 0x00000018; 864 ib->ptr[ib->length_dw++] = 0x00000001; 865 ib->ptr[ib->length_dw++] = handle; 866 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 867 ib->ptr[ib->length_dw++] = addr; 868 ib->ptr[ib->length_dw++] = 0x0000000b; 869 870 ib->ptr[ib->length_dw++] = 0x00000014; 871 ib->ptr[ib->length_dw++] = 0x00000002; 872 ib->ptr[ib->length_dw++] = 0x0000001c; 873 ib->ptr[ib->length_dw++] = 0x00000000; 874 ib->ptr[ib->length_dw++] = 0x00000000; 875 876 ib->ptr[ib->length_dw++] = 0x00000008; 877 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 878 879 for (i = ib->length_dw; i < ib_size_dw; ++i) 880 ib->ptr[i] = 0x0; 881 882 r = amdgpu_job_submit_direct(job, ring, &f); 883 if (r) 884 goto err; 885 886 if (fence) 887 *fence = dma_fence_get(f); 888 dma_fence_put(f); 889 890 return 0; 891 892 err: 893 amdgpu_job_free(job); 894 return r; 895 } 896 897 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 898 { 899 struct amdgpu_device *adev = ring->adev; 900 struct dma_fence *fence = NULL; 901 struct amdgpu_ib ib; 902 long r; 903 904 memset(&ib, 0, sizeof(ib)); 905 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 906 AMDGPU_IB_POOL_DIRECT, 907 &ib); 908 if (r) 909 return r; 910 911 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 912 if (r) 913 goto error; 914 915 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 916 if (r) 917 goto error; 918 919 r = dma_fence_wait_timeout(fence, false, timeout); 920 if (r == 0) 921 r = -ETIMEDOUT; 922 else if (r > 0) 923 r = 0; 924 925 error: 926 amdgpu_ib_free(adev, &ib, fence); 927 dma_fence_put(fence); 928 929 return r; 930 } 931 932 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 933 { 934 switch(ring) { 935 case 0: 936 return AMDGPU_RING_PRIO_0; 937 case 1: 938 return AMDGPU_RING_PRIO_1; 939 case 2: 940 return AMDGPU_RING_PRIO_2; 941 default: 942 return AMDGPU_RING_PRIO_0; 943 } 944 } 945 946 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 947 { 948 int i; 949 unsigned int idx; 950 951 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 952 const struct common_firmware_header *hdr; 953 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 954 955 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 956 if (adev->vcn.harvest_config & (1 << i)) 957 continue; 958 /* currently only support 2 FW instances */ 959 if (i >= 2) { 960 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 961 break; 962 } 963 idx = AMDGPU_UCODE_ID_VCN + i; 964 adev->firmware.ucode[idx].ucode_id = idx; 965 adev->firmware.ucode[idx].fw = adev->vcn.fw; 966 adev->firmware.fw_size += 967 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 968 } 969 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 970 } 971 } 972