1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <drm/drm_drv.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_vcn.h" 35 #include "soc15d.h" 36 37 /* Firmware Names */ 38 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 39 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 40 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 41 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 42 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 43 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 44 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 45 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 46 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 48 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 49 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 50 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 51 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 52 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 53 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 54 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2_vcn.bin" 55 56 MODULE_FIRMWARE(FIRMWARE_RAVEN); 57 MODULE_FIRMWARE(FIRMWARE_PICASSO); 58 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 59 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 60 MODULE_FIRMWARE(FIRMWARE_RENOIR); 61 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 62 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 63 MODULE_FIRMWARE(FIRMWARE_NAVI10); 64 MODULE_FIRMWARE(FIRMWARE_NAVI14); 65 MODULE_FIRMWARE(FIRMWARE_NAVI12); 66 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 67 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 68 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 69 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 70 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 71 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 72 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); 73 74 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 75 76 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 77 { 78 unsigned long bo_size; 79 const char *fw_name; 80 const struct common_firmware_header *hdr; 81 unsigned char fw_check; 82 int i, r; 83 84 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 85 mutex_init(&adev->vcn.vcn_pg_lock); 86 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 87 atomic_set(&adev->vcn.total_submission_cnt, 0); 88 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 89 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 90 91 switch (adev->ip_versions[UVD_HWIP][0]) { 92 case IP_VERSION(1, 0, 0): 93 case IP_VERSION(1, 0, 1): 94 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 95 fw_name = FIRMWARE_RAVEN2; 96 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 97 fw_name = FIRMWARE_PICASSO; 98 else 99 fw_name = FIRMWARE_RAVEN; 100 break; 101 case IP_VERSION(2, 5, 0): 102 fw_name = FIRMWARE_ARCTURUS; 103 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 104 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 105 adev->vcn.indirect_sram = true; 106 break; 107 case IP_VERSION(2, 2, 0): 108 if (adev->apu_flags & AMD_APU_IS_RENOIR) 109 fw_name = FIRMWARE_RENOIR; 110 else 111 fw_name = FIRMWARE_GREEN_SARDINE; 112 113 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 114 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 115 adev->vcn.indirect_sram = true; 116 break; 117 case IP_VERSION(2, 6, 0): 118 fw_name = FIRMWARE_ALDEBARAN; 119 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 120 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 121 adev->vcn.indirect_sram = true; 122 break; 123 case IP_VERSION(2, 0, 0): 124 fw_name = FIRMWARE_NAVI10; 125 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 126 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 127 adev->vcn.indirect_sram = true; 128 break; 129 case IP_VERSION(2, 0, 2): 130 if (adev->asic_type == CHIP_NAVI12) 131 fw_name = FIRMWARE_NAVI12; 132 else 133 fw_name = FIRMWARE_NAVI14; 134 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 135 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 136 adev->vcn.indirect_sram = true; 137 break; 138 case IP_VERSION(3, 0, 0): 139 case IP_VERSION(3, 0, 64): 140 case IP_VERSION(3, 0, 192): 141 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 142 fw_name = FIRMWARE_SIENNA_CICHLID; 143 else 144 fw_name = FIRMWARE_NAVY_FLOUNDER; 145 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 146 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 147 adev->vcn.indirect_sram = true; 148 break; 149 case IP_VERSION(3, 0, 2): 150 fw_name = FIRMWARE_VANGOGH; 151 break; 152 case IP_VERSION(3, 0, 16): 153 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 154 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 155 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 156 adev->vcn.indirect_sram = true; 157 break; 158 case IP_VERSION(3, 0, 33): 159 fw_name = FIRMWARE_BEIGE_GOBY; 160 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 161 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 162 adev->vcn.indirect_sram = true; 163 break; 164 case IP_VERSION(3, 1, 1): 165 fw_name = FIRMWARE_YELLOW_CARP; 166 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 167 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 168 adev->vcn.indirect_sram = true; 169 break; 170 case IP_VERSION(3, 1, 2): 171 fw_name = FIRMWARE_VCN_3_1_2; 172 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 173 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 174 adev->vcn.indirect_sram = true; 175 break; 176 default: 177 return -EINVAL; 178 } 179 180 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 181 if (r) { 182 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 183 fw_name); 184 return r; 185 } 186 187 r = amdgpu_ucode_validate(adev->vcn.fw); 188 if (r) { 189 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 190 fw_name); 191 release_firmware(adev->vcn.fw); 192 adev->vcn.fw = NULL; 193 return r; 194 } 195 196 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 197 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 198 199 /* Bit 20-23, it is encode major and non-zero for new naming convention. 200 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 201 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 202 * is zero in old naming convention, this field is always zero so far. 203 * These four bits are used to tell which naming convention is present. 204 */ 205 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 206 if (fw_check) { 207 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 208 209 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 210 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 211 enc_major = fw_check; 212 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 213 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 214 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 215 enc_major, enc_minor, dec_ver, vep, fw_rev); 216 } else { 217 unsigned int version_major, version_minor, family_id; 218 219 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 220 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 221 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 222 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 223 version_major, version_minor, family_id); 224 } 225 226 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 227 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 228 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 229 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 230 231 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 232 if (adev->vcn.harvest_config & (1 << i)) 233 continue; 234 235 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 236 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 237 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 238 if (r) { 239 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 240 return r; 241 } 242 243 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr + 244 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 245 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr + 246 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 247 248 if (adev->vcn.indirect_sram) { 249 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 250 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 251 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 252 if (r) { 253 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 254 return r; 255 } 256 } 257 } 258 259 return 0; 260 } 261 262 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 263 { 264 int i, j; 265 266 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 267 if (adev->vcn.harvest_config & (1 << j)) 268 continue; 269 270 if (adev->vcn.indirect_sram) { 271 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 272 &adev->vcn.inst[j].dpg_sram_gpu_addr, 273 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 274 } 275 kvfree(adev->vcn.inst[j].saved_bo); 276 277 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 278 &adev->vcn.inst[j].gpu_addr, 279 (void **)&adev->vcn.inst[j].cpu_addr); 280 281 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 282 283 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 284 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 285 } 286 287 release_firmware(adev->vcn.fw); 288 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 289 mutex_destroy(&adev->vcn.vcn_pg_lock); 290 291 return 0; 292 } 293 294 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 295 { 296 bool ret = false; 297 int vcn_config = adev->vcn.vcn_config[vcn_instance]; 298 299 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 300 ret = true; 301 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) { 302 ret = true; 303 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 304 ret = true; 305 } 306 307 return ret; 308 } 309 310 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 311 { 312 unsigned size; 313 void *ptr; 314 int i, idx; 315 316 cancel_delayed_work_sync(&adev->vcn.idle_work); 317 318 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 319 if (adev->vcn.harvest_config & (1 << i)) 320 continue; 321 if (adev->vcn.inst[i].vcpu_bo == NULL) 322 return 0; 323 324 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 325 ptr = adev->vcn.inst[i].cpu_addr; 326 327 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 328 if (!adev->vcn.inst[i].saved_bo) 329 return -ENOMEM; 330 331 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 332 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 333 drm_dev_exit(idx); 334 } 335 } 336 return 0; 337 } 338 339 int amdgpu_vcn_resume(struct amdgpu_device *adev) 340 { 341 unsigned size; 342 void *ptr; 343 int i, idx; 344 345 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 346 if (adev->vcn.harvest_config & (1 << i)) 347 continue; 348 if (adev->vcn.inst[i].vcpu_bo == NULL) 349 return -EINVAL; 350 351 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 352 ptr = adev->vcn.inst[i].cpu_addr; 353 354 if (adev->vcn.inst[i].saved_bo != NULL) { 355 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 356 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 357 drm_dev_exit(idx); 358 } 359 kvfree(adev->vcn.inst[i].saved_bo); 360 adev->vcn.inst[i].saved_bo = NULL; 361 } else { 362 const struct common_firmware_header *hdr; 363 unsigned offset; 364 365 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 366 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 367 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 368 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 369 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 370 le32_to_cpu(hdr->ucode_size_bytes)); 371 drm_dev_exit(idx); 372 } 373 size -= le32_to_cpu(hdr->ucode_size_bytes); 374 ptr += le32_to_cpu(hdr->ucode_size_bytes); 375 } 376 memset_io(ptr, 0, size); 377 } 378 } 379 return 0; 380 } 381 382 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 383 { 384 struct amdgpu_device *adev = 385 container_of(work, struct amdgpu_device, vcn.idle_work.work); 386 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 387 unsigned int i, j; 388 int r = 0; 389 390 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 391 if (adev->vcn.harvest_config & (1 << j)) 392 continue; 393 394 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 395 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 396 } 397 398 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 399 struct dpg_pause_state new_state; 400 401 if (fence[j] || 402 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 403 new_state.fw_based = VCN_DPG_STATE__PAUSE; 404 else 405 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 406 407 adev->vcn.pause_dpg_mode(adev, j, &new_state); 408 } 409 410 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 411 fences += fence[j]; 412 } 413 414 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 415 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 416 AMD_PG_STATE_GATE); 417 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 418 false); 419 if (r) 420 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 421 } else { 422 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 423 } 424 } 425 426 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 427 { 428 struct amdgpu_device *adev = ring->adev; 429 int r = 0; 430 431 atomic_inc(&adev->vcn.total_submission_cnt); 432 433 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 434 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 435 true); 436 if (r) 437 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 438 } 439 440 mutex_lock(&adev->vcn.vcn_pg_lock); 441 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 442 AMD_PG_STATE_UNGATE); 443 444 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 445 struct dpg_pause_state new_state; 446 447 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 448 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 449 new_state.fw_based = VCN_DPG_STATE__PAUSE; 450 } else { 451 unsigned int fences = 0; 452 unsigned int i; 453 454 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 455 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 456 457 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 458 new_state.fw_based = VCN_DPG_STATE__PAUSE; 459 else 460 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 461 } 462 463 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 464 } 465 mutex_unlock(&adev->vcn.vcn_pg_lock); 466 } 467 468 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 469 { 470 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 471 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 472 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 473 474 atomic_dec(&ring->adev->vcn.total_submission_cnt); 475 476 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 477 } 478 479 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 480 { 481 struct amdgpu_device *adev = ring->adev; 482 uint32_t tmp = 0; 483 unsigned i; 484 int r; 485 486 /* VCN in SRIOV does not support direct register read/write */ 487 if (amdgpu_sriov_vf(adev)) 488 return 0; 489 490 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 491 r = amdgpu_ring_alloc(ring, 3); 492 if (r) 493 return r; 494 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 495 amdgpu_ring_write(ring, 0xDEADBEEF); 496 amdgpu_ring_commit(ring); 497 for (i = 0; i < adev->usec_timeout; i++) { 498 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 499 if (tmp == 0xDEADBEEF) 500 break; 501 udelay(1); 502 } 503 504 if (i >= adev->usec_timeout) 505 r = -ETIMEDOUT; 506 507 return r; 508 } 509 510 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 511 { 512 struct amdgpu_device *adev = ring->adev; 513 uint32_t rptr; 514 unsigned int i; 515 int r; 516 517 if (amdgpu_sriov_vf(adev)) 518 return 0; 519 520 r = amdgpu_ring_alloc(ring, 16); 521 if (r) 522 return r; 523 524 rptr = amdgpu_ring_get_rptr(ring); 525 526 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 527 amdgpu_ring_commit(ring); 528 529 for (i = 0; i < adev->usec_timeout; i++) { 530 if (amdgpu_ring_get_rptr(ring) != rptr) 531 break; 532 udelay(1); 533 } 534 535 if (i >= adev->usec_timeout) 536 r = -ETIMEDOUT; 537 538 return r; 539 } 540 541 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 542 struct amdgpu_ib *ib_msg, 543 struct dma_fence **fence) 544 { 545 struct amdgpu_device *adev = ring->adev; 546 struct dma_fence *f = NULL; 547 struct amdgpu_job *job; 548 struct amdgpu_ib *ib; 549 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 550 int i, r; 551 552 r = amdgpu_job_alloc_with_ib(adev, 64, 553 AMDGPU_IB_POOL_DIRECT, &job); 554 if (r) 555 goto err; 556 557 ib = &job->ibs[0]; 558 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 559 ib->ptr[1] = addr; 560 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 561 ib->ptr[3] = addr >> 32; 562 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 563 ib->ptr[5] = 0; 564 for (i = 6; i < 16; i += 2) { 565 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 566 ib->ptr[i+1] = 0; 567 } 568 ib->length_dw = 16; 569 570 r = amdgpu_job_submit_direct(job, ring, &f); 571 if (r) 572 goto err_free; 573 574 amdgpu_ib_free(adev, ib_msg, f); 575 576 if (fence) 577 *fence = dma_fence_get(f); 578 dma_fence_put(f); 579 580 return 0; 581 582 err_free: 583 amdgpu_job_free(job); 584 err: 585 amdgpu_ib_free(adev, ib_msg, f); 586 return r; 587 } 588 589 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 590 struct amdgpu_ib *ib) 591 { 592 struct amdgpu_device *adev = ring->adev; 593 uint32_t *msg; 594 int r, i; 595 596 memset(ib, 0, sizeof(*ib)); 597 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 598 AMDGPU_IB_POOL_DIRECT, 599 ib); 600 if (r) 601 return r; 602 603 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 604 msg[0] = cpu_to_le32(0x00000028); 605 msg[1] = cpu_to_le32(0x00000038); 606 msg[2] = cpu_to_le32(0x00000001); 607 msg[3] = cpu_to_le32(0x00000000); 608 msg[4] = cpu_to_le32(handle); 609 msg[5] = cpu_to_le32(0x00000000); 610 msg[6] = cpu_to_le32(0x00000001); 611 msg[7] = cpu_to_le32(0x00000028); 612 msg[8] = cpu_to_le32(0x00000010); 613 msg[9] = cpu_to_le32(0x00000000); 614 msg[10] = cpu_to_le32(0x00000007); 615 msg[11] = cpu_to_le32(0x00000000); 616 msg[12] = cpu_to_le32(0x00000780); 617 msg[13] = cpu_to_le32(0x00000440); 618 for (i = 14; i < 1024; ++i) 619 msg[i] = cpu_to_le32(0x0); 620 621 return 0; 622 } 623 624 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 625 struct amdgpu_ib *ib) 626 { 627 struct amdgpu_device *adev = ring->adev; 628 uint32_t *msg; 629 int r, i; 630 631 memset(ib, 0, sizeof(*ib)); 632 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 633 AMDGPU_IB_POOL_DIRECT, 634 ib); 635 if (r) 636 return r; 637 638 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 639 msg[0] = cpu_to_le32(0x00000028); 640 msg[1] = cpu_to_le32(0x00000018); 641 msg[2] = cpu_to_le32(0x00000000); 642 msg[3] = cpu_to_le32(0x00000002); 643 msg[4] = cpu_to_le32(handle); 644 msg[5] = cpu_to_le32(0x00000000); 645 for (i = 6; i < 1024; ++i) 646 msg[i] = cpu_to_le32(0x0); 647 648 return 0; 649 } 650 651 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 652 { 653 struct dma_fence *fence = NULL; 654 struct amdgpu_ib ib; 655 long r; 656 657 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 658 if (r) 659 goto error; 660 661 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 662 if (r) 663 goto error; 664 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 665 if (r) 666 goto error; 667 668 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 669 if (r) 670 goto error; 671 672 r = dma_fence_wait_timeout(fence, false, timeout); 673 if (r == 0) 674 r = -ETIMEDOUT; 675 else if (r > 0) 676 r = 0; 677 678 dma_fence_put(fence); 679 error: 680 return r; 681 } 682 683 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 684 struct amdgpu_ib *ib_msg, 685 struct dma_fence **fence) 686 { 687 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 688 const unsigned int ib_size_dw = 64; 689 struct amdgpu_device *adev = ring->adev; 690 struct dma_fence *f = NULL; 691 struct amdgpu_job *job; 692 struct amdgpu_ib *ib; 693 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 694 int i, r; 695 696 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 697 AMDGPU_IB_POOL_DIRECT, &job); 698 if (r) 699 goto err; 700 701 ib = &job->ibs[0]; 702 ib->length_dw = 0; 703 704 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 705 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 706 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 707 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 708 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 709 710 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 711 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 712 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 713 714 for (i = ib->length_dw; i < ib_size_dw; ++i) 715 ib->ptr[i] = 0x0; 716 717 r = amdgpu_job_submit_direct(job, ring, &f); 718 if (r) 719 goto err_free; 720 721 amdgpu_ib_free(adev, ib_msg, f); 722 723 if (fence) 724 *fence = dma_fence_get(f); 725 dma_fence_put(f); 726 727 return 0; 728 729 err_free: 730 amdgpu_job_free(job); 731 err: 732 amdgpu_ib_free(adev, ib_msg, f); 733 return r; 734 } 735 736 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 737 { 738 struct dma_fence *fence = NULL; 739 struct amdgpu_ib ib; 740 long r; 741 742 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 743 if (r) 744 goto error; 745 746 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 747 if (r) 748 goto error; 749 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 750 if (r) 751 goto error; 752 753 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 754 if (r) 755 goto error; 756 757 r = dma_fence_wait_timeout(fence, false, timeout); 758 if (r == 0) 759 r = -ETIMEDOUT; 760 else if (r > 0) 761 r = 0; 762 763 dma_fence_put(fence); 764 error: 765 return r; 766 } 767 768 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 769 { 770 struct amdgpu_device *adev = ring->adev; 771 uint32_t rptr; 772 unsigned i; 773 int r; 774 775 if (amdgpu_sriov_vf(adev)) 776 return 0; 777 778 r = amdgpu_ring_alloc(ring, 16); 779 if (r) 780 return r; 781 782 rptr = amdgpu_ring_get_rptr(ring); 783 784 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 785 amdgpu_ring_commit(ring); 786 787 for (i = 0; i < adev->usec_timeout; i++) { 788 if (amdgpu_ring_get_rptr(ring) != rptr) 789 break; 790 udelay(1); 791 } 792 793 if (i >= adev->usec_timeout) 794 r = -ETIMEDOUT; 795 796 return r; 797 } 798 799 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 800 struct amdgpu_ib *ib_msg, 801 struct dma_fence **fence) 802 { 803 const unsigned ib_size_dw = 16; 804 struct amdgpu_job *job; 805 struct amdgpu_ib *ib; 806 struct dma_fence *f = NULL; 807 uint64_t addr; 808 int i, r; 809 810 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 811 AMDGPU_IB_POOL_DIRECT, &job); 812 if (r) 813 return r; 814 815 ib = &job->ibs[0]; 816 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 817 818 ib->length_dw = 0; 819 ib->ptr[ib->length_dw++] = 0x00000018; 820 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 821 ib->ptr[ib->length_dw++] = handle; 822 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 823 ib->ptr[ib->length_dw++] = addr; 824 ib->ptr[ib->length_dw++] = 0x0000000b; 825 826 ib->ptr[ib->length_dw++] = 0x00000014; 827 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 828 ib->ptr[ib->length_dw++] = 0x0000001c; 829 ib->ptr[ib->length_dw++] = 0x00000000; 830 ib->ptr[ib->length_dw++] = 0x00000000; 831 832 ib->ptr[ib->length_dw++] = 0x00000008; 833 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 834 835 for (i = ib->length_dw; i < ib_size_dw; ++i) 836 ib->ptr[i] = 0x0; 837 838 r = amdgpu_job_submit_direct(job, ring, &f); 839 if (r) 840 goto err; 841 842 if (fence) 843 *fence = dma_fence_get(f); 844 dma_fence_put(f); 845 846 return 0; 847 848 err: 849 amdgpu_job_free(job); 850 return r; 851 } 852 853 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 854 struct amdgpu_ib *ib_msg, 855 struct dma_fence **fence) 856 { 857 const unsigned ib_size_dw = 16; 858 struct amdgpu_job *job; 859 struct amdgpu_ib *ib; 860 struct dma_fence *f = NULL; 861 uint64_t addr; 862 int i, r; 863 864 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 865 AMDGPU_IB_POOL_DIRECT, &job); 866 if (r) 867 return r; 868 869 ib = &job->ibs[0]; 870 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 871 872 ib->length_dw = 0; 873 ib->ptr[ib->length_dw++] = 0x00000018; 874 ib->ptr[ib->length_dw++] = 0x00000001; 875 ib->ptr[ib->length_dw++] = handle; 876 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 877 ib->ptr[ib->length_dw++] = addr; 878 ib->ptr[ib->length_dw++] = 0x0000000b; 879 880 ib->ptr[ib->length_dw++] = 0x00000014; 881 ib->ptr[ib->length_dw++] = 0x00000002; 882 ib->ptr[ib->length_dw++] = 0x0000001c; 883 ib->ptr[ib->length_dw++] = 0x00000000; 884 ib->ptr[ib->length_dw++] = 0x00000000; 885 886 ib->ptr[ib->length_dw++] = 0x00000008; 887 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 888 889 for (i = ib->length_dw; i < ib_size_dw; ++i) 890 ib->ptr[i] = 0x0; 891 892 r = amdgpu_job_submit_direct(job, ring, &f); 893 if (r) 894 goto err; 895 896 if (fence) 897 *fence = dma_fence_get(f); 898 dma_fence_put(f); 899 900 return 0; 901 902 err: 903 amdgpu_job_free(job); 904 return r; 905 } 906 907 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 908 { 909 struct amdgpu_device *adev = ring->adev; 910 struct dma_fence *fence = NULL; 911 struct amdgpu_ib ib; 912 long r; 913 914 memset(&ib, 0, sizeof(ib)); 915 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 916 AMDGPU_IB_POOL_DIRECT, 917 &ib); 918 if (r) 919 return r; 920 921 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 922 if (r) 923 goto error; 924 925 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 926 if (r) 927 goto error; 928 929 r = dma_fence_wait_timeout(fence, false, timeout); 930 if (r == 0) 931 r = -ETIMEDOUT; 932 else if (r > 0) 933 r = 0; 934 935 error: 936 amdgpu_ib_free(adev, &ib, fence); 937 dma_fence_put(fence); 938 939 return r; 940 } 941 942 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 943 { 944 switch(ring) { 945 case 0: 946 return AMDGPU_RING_PRIO_0; 947 case 1: 948 return AMDGPU_RING_PRIO_1; 949 case 2: 950 return AMDGPU_RING_PRIO_2; 951 default: 952 return AMDGPU_RING_PRIO_0; 953 } 954 } 955 956 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 957 { 958 int i; 959 unsigned int idx; 960 961 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 962 const struct common_firmware_header *hdr; 963 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 964 965 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 966 if (adev->vcn.harvest_config & (1 << i)) 967 continue; 968 /* currently only support 2 FW instances */ 969 if (i >= 2) { 970 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 971 break; 972 } 973 idx = AMDGPU_UCODE_ID_VCN + i; 974 adev->firmware.ucode[idx].ucode_id = idx; 975 adev->firmware.ucode[idx].fw = adev->vcn.fw; 976 adev->firmware.fw_size += 977 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 978 } 979 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 980 } 981 } 982