1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/firmware.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <drm/drm_drv.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_vcn.h" 35 #include "soc15d.h" 36 37 /* Firmware Names */ 38 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" 39 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" 40 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" 41 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" 42 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" 43 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" 44 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" 45 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" 46 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" 47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" 48 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" 49 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" 50 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" 51 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" 52 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" 53 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" 54 55 MODULE_FIRMWARE(FIRMWARE_RAVEN); 56 MODULE_FIRMWARE(FIRMWARE_PICASSO); 57 MODULE_FIRMWARE(FIRMWARE_RAVEN2); 58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS); 59 MODULE_FIRMWARE(FIRMWARE_RENOIR); 60 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); 61 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); 62 MODULE_FIRMWARE(FIRMWARE_NAVI10); 63 MODULE_FIRMWARE(FIRMWARE_NAVI14); 64 MODULE_FIRMWARE(FIRMWARE_NAVI12); 65 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); 66 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); 67 MODULE_FIRMWARE(FIRMWARE_VANGOGH); 68 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); 69 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); 70 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); 71 72 static void amdgpu_vcn_idle_work_handler(struct work_struct *work); 73 74 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 75 { 76 unsigned long bo_size; 77 const char *fw_name; 78 const struct common_firmware_header *hdr; 79 unsigned char fw_check; 80 int i, r; 81 82 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); 83 mutex_init(&adev->vcn.vcn_pg_lock); 84 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); 85 atomic_set(&adev->vcn.total_submission_cnt, 0); 86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 87 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); 88 89 switch (adev->ip_versions[UVD_HWIP][0]) { 90 case IP_VERSION(1, 0, 0): 91 case IP_VERSION(1, 0, 1): 92 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 93 fw_name = FIRMWARE_RAVEN2; 94 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 95 fw_name = FIRMWARE_PICASSO; 96 else 97 fw_name = FIRMWARE_RAVEN; 98 break; 99 case IP_VERSION(2, 5, 0): 100 fw_name = FIRMWARE_ARCTURUS; 101 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 102 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 103 adev->vcn.indirect_sram = true; 104 break; 105 case IP_VERSION(2, 2, 0): 106 if (adev->apu_flags & AMD_APU_IS_RENOIR) 107 fw_name = FIRMWARE_RENOIR; 108 else 109 fw_name = FIRMWARE_GREEN_SARDINE; 110 111 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 112 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 113 adev->vcn.indirect_sram = true; 114 break; 115 case IP_VERSION(2, 6, 0): 116 fw_name = FIRMWARE_ALDEBARAN; 117 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 118 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 119 adev->vcn.indirect_sram = true; 120 break; 121 case IP_VERSION(2, 0, 0): 122 fw_name = FIRMWARE_NAVI10; 123 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 124 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 125 adev->vcn.indirect_sram = true; 126 break; 127 case IP_VERSION(2, 0, 2): 128 if (adev->asic_type == CHIP_NAVI12) 129 fw_name = FIRMWARE_NAVI12; 130 else 131 fw_name = FIRMWARE_NAVI14; 132 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 133 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 134 adev->vcn.indirect_sram = true; 135 break; 136 case IP_VERSION(3, 0, 0): 137 case IP_VERSION(3, 0, 64): 138 case IP_VERSION(3, 0, 192): 139 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 140 fw_name = FIRMWARE_SIENNA_CICHLID; 141 else 142 fw_name = FIRMWARE_NAVY_FLOUNDER; 143 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 144 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 145 adev->vcn.indirect_sram = true; 146 break; 147 case IP_VERSION(3, 0, 2): 148 fw_name = FIRMWARE_VANGOGH; 149 break; 150 case IP_VERSION(3, 0, 16): 151 fw_name = FIRMWARE_DIMGREY_CAVEFISH; 152 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 153 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 154 adev->vcn.indirect_sram = true; 155 break; 156 case IP_VERSION(3, 0, 33): 157 fw_name = FIRMWARE_BEIGE_GOBY; 158 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 159 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 160 adev->vcn.indirect_sram = true; 161 break; 162 case IP_VERSION(3, 1, 1): 163 fw_name = FIRMWARE_YELLOW_CARP; 164 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 165 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 166 adev->vcn.indirect_sram = true; 167 break; 168 default: 169 return -EINVAL; 170 } 171 172 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); 173 if (r) { 174 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", 175 fw_name); 176 return r; 177 } 178 179 r = amdgpu_ucode_validate(adev->vcn.fw); 180 if (r) { 181 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", 182 fw_name); 183 release_firmware(adev->vcn.fw); 184 adev->vcn.fw = NULL; 185 return r; 186 } 187 188 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 189 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); 190 191 /* Bit 20-23, it is encode major and non-zero for new naming convention. 192 * This field is part of version minor and DRM_DISABLED_FLAG in old naming 193 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG 194 * is zero in old naming convention, this field is always zero so far. 195 * These four bits are used to tell which naming convention is present. 196 */ 197 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; 198 if (fw_check) { 199 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev; 200 201 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; 202 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; 203 enc_major = fw_check; 204 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; 205 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; 206 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", 207 enc_major, enc_minor, dec_ver, vep, fw_rev); 208 } else { 209 unsigned int version_major, version_minor, family_id; 210 211 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 212 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 213 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 214 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n", 215 version_major, version_minor, family_id); 216 } 217 218 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 219 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 220 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 221 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 222 223 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 224 if (adev->vcn.harvest_config & (1 << i)) 225 continue; 226 227 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 228 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo, 229 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr); 230 if (r) { 231 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); 232 return r; 233 } 234 235 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr + 236 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 237 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr + 238 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); 239 240 if (adev->vcn.indirect_sram) { 241 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE, 242 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo, 243 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr); 244 if (r) { 245 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r); 246 return r; 247 } 248 } 249 } 250 251 return 0; 252 } 253 254 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 255 { 256 int i, j; 257 258 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 259 if (adev->vcn.harvest_config & (1 << j)) 260 continue; 261 262 if (adev->vcn.indirect_sram) { 263 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, 264 &adev->vcn.inst[j].dpg_sram_gpu_addr, 265 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); 266 } 267 kvfree(adev->vcn.inst[j].saved_bo); 268 269 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, 270 &adev->vcn.inst[j].gpu_addr, 271 (void **)&adev->vcn.inst[j].cpu_addr); 272 273 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); 274 275 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 276 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); 277 } 278 279 release_firmware(adev->vcn.fw); 280 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); 281 mutex_destroy(&adev->vcn.vcn_pg_lock); 282 283 return 0; 284 } 285 286 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) 287 { 288 bool ret = false; 289 290 int major; 291 int minor; 292 int revision; 293 294 /* if cannot find IP data, then this VCN does not exist */ 295 if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, &major, &minor, &revision) != 0) 296 return true; 297 298 if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) { 299 ret = true; 300 } else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) { 301 ret = true; 302 } else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) { 303 ret = true; 304 } 305 306 return ret; 307 } 308 309 int amdgpu_vcn_suspend(struct amdgpu_device *adev) 310 { 311 unsigned size; 312 void *ptr; 313 int i, idx; 314 315 cancel_delayed_work_sync(&adev->vcn.idle_work); 316 317 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 318 if (adev->vcn.harvest_config & (1 << i)) 319 continue; 320 if (adev->vcn.inst[i].vcpu_bo == NULL) 321 return 0; 322 323 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 324 ptr = adev->vcn.inst[i].cpu_addr; 325 326 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); 327 if (!adev->vcn.inst[i].saved_bo) 328 return -ENOMEM; 329 330 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 331 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); 332 drm_dev_exit(idx); 333 } 334 } 335 return 0; 336 } 337 338 int amdgpu_vcn_resume(struct amdgpu_device *adev) 339 { 340 unsigned size; 341 void *ptr; 342 int i, idx; 343 344 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 345 if (adev->vcn.harvest_config & (1 << i)) 346 continue; 347 if (adev->vcn.inst[i].vcpu_bo == NULL) 348 return -EINVAL; 349 350 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); 351 ptr = adev->vcn.inst[i].cpu_addr; 352 353 if (adev->vcn.inst[i].saved_bo != NULL) { 354 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 355 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); 356 drm_dev_exit(idx); 357 } 358 kvfree(adev->vcn.inst[i].saved_bo); 359 adev->vcn.inst[i].saved_bo = NULL; 360 } else { 361 const struct common_firmware_header *hdr; 362 unsigned offset; 363 364 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 365 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 366 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 367 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 368 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, 369 le32_to_cpu(hdr->ucode_size_bytes)); 370 drm_dev_exit(idx); 371 } 372 size -= le32_to_cpu(hdr->ucode_size_bytes); 373 ptr += le32_to_cpu(hdr->ucode_size_bytes); 374 } 375 memset_io(ptr, 0, size); 376 } 377 } 378 return 0; 379 } 380 381 static void amdgpu_vcn_idle_work_handler(struct work_struct *work) 382 { 383 struct amdgpu_device *adev = 384 container_of(work, struct amdgpu_device, vcn.idle_work.work); 385 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 386 unsigned int i, j; 387 int r = 0; 388 389 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 390 if (adev->vcn.harvest_config & (1 << j)) 391 continue; 392 393 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 394 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); 395 } 396 397 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 398 struct dpg_pause_state new_state; 399 400 if (fence[j] || 401 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) 402 new_state.fw_based = VCN_DPG_STATE__PAUSE; 403 else 404 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 405 406 adev->vcn.pause_dpg_mode(adev, j, &new_state); 407 } 408 409 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); 410 fences += fence[j]; 411 } 412 413 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { 414 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 415 AMD_PG_STATE_GATE); 416 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 417 false); 418 if (r) 419 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 420 } else { 421 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 422 } 423 } 424 425 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) 426 { 427 struct amdgpu_device *adev = ring->adev; 428 int r = 0; 429 430 atomic_inc(&adev->vcn.total_submission_cnt); 431 432 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { 433 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 434 true); 435 if (r) 436 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 437 } 438 439 mutex_lock(&adev->vcn.vcn_pg_lock); 440 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 441 AMD_PG_STATE_UNGATE); 442 443 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 444 struct dpg_pause_state new_state; 445 446 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 447 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 448 new_state.fw_based = VCN_DPG_STATE__PAUSE; 449 } else { 450 unsigned int fences = 0; 451 unsigned int i; 452 453 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 454 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); 455 456 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) 457 new_state.fw_based = VCN_DPG_STATE__PAUSE; 458 else 459 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 460 } 461 462 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); 463 } 464 mutex_unlock(&adev->vcn.vcn_pg_lock); 465 } 466 467 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) 468 { 469 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 470 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 471 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 472 473 atomic_dec(&ring->adev->vcn.total_submission_cnt); 474 475 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 476 } 477 478 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) 479 { 480 struct amdgpu_device *adev = ring->adev; 481 uint32_t tmp = 0; 482 unsigned i; 483 int r; 484 485 /* VCN in SRIOV does not support direct register read/write */ 486 if (amdgpu_sriov_vf(adev)) 487 return 0; 488 489 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 490 r = amdgpu_ring_alloc(ring, 3); 491 if (r) 492 return r; 493 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 494 amdgpu_ring_write(ring, 0xDEADBEEF); 495 amdgpu_ring_commit(ring); 496 for (i = 0; i < adev->usec_timeout; i++) { 497 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 498 if (tmp == 0xDEADBEEF) 499 break; 500 udelay(1); 501 } 502 503 if (i >= adev->usec_timeout) 504 r = -ETIMEDOUT; 505 506 return r; 507 } 508 509 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) 510 { 511 struct amdgpu_device *adev = ring->adev; 512 uint32_t rptr; 513 unsigned int i; 514 int r; 515 516 if (amdgpu_sriov_vf(adev)) 517 return 0; 518 519 r = amdgpu_ring_alloc(ring, 16); 520 if (r) 521 return r; 522 523 rptr = amdgpu_ring_get_rptr(ring); 524 525 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 526 amdgpu_ring_commit(ring); 527 528 for (i = 0; i < adev->usec_timeout; i++) { 529 if (amdgpu_ring_get_rptr(ring) != rptr) 530 break; 531 udelay(1); 532 } 533 534 if (i >= adev->usec_timeout) 535 r = -ETIMEDOUT; 536 537 return r; 538 } 539 540 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, 541 struct amdgpu_ib *ib_msg, 542 struct dma_fence **fence) 543 { 544 struct amdgpu_device *adev = ring->adev; 545 struct dma_fence *f = NULL; 546 struct amdgpu_job *job; 547 struct amdgpu_ib *ib; 548 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 549 int i, r; 550 551 r = amdgpu_job_alloc_with_ib(adev, 64, 552 AMDGPU_IB_POOL_DIRECT, &job); 553 if (r) 554 goto err; 555 556 ib = &job->ibs[0]; 557 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); 558 ib->ptr[1] = addr; 559 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); 560 ib->ptr[3] = addr >> 32; 561 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); 562 ib->ptr[5] = 0; 563 for (i = 6; i < 16; i += 2) { 564 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); 565 ib->ptr[i+1] = 0; 566 } 567 ib->length_dw = 16; 568 569 r = amdgpu_job_submit_direct(job, ring, &f); 570 if (r) 571 goto err_free; 572 573 amdgpu_ib_free(adev, ib_msg, f); 574 575 if (fence) 576 *fence = dma_fence_get(f); 577 dma_fence_put(f); 578 579 return 0; 580 581 err_free: 582 amdgpu_job_free(job); 583 err: 584 amdgpu_ib_free(adev, ib_msg, f); 585 return r; 586 } 587 588 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 589 struct amdgpu_ib *ib) 590 { 591 struct amdgpu_device *adev = ring->adev; 592 uint32_t *msg; 593 int r, i; 594 595 memset(ib, 0, sizeof(*ib)); 596 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 597 AMDGPU_IB_POOL_DIRECT, 598 ib); 599 if (r) 600 return r; 601 602 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 603 msg[0] = cpu_to_le32(0x00000028); 604 msg[1] = cpu_to_le32(0x00000038); 605 msg[2] = cpu_to_le32(0x00000001); 606 msg[3] = cpu_to_le32(0x00000000); 607 msg[4] = cpu_to_le32(handle); 608 msg[5] = cpu_to_le32(0x00000000); 609 msg[6] = cpu_to_le32(0x00000001); 610 msg[7] = cpu_to_le32(0x00000028); 611 msg[8] = cpu_to_le32(0x00000010); 612 msg[9] = cpu_to_le32(0x00000000); 613 msg[10] = cpu_to_le32(0x00000007); 614 msg[11] = cpu_to_le32(0x00000000); 615 msg[12] = cpu_to_le32(0x00000780); 616 msg[13] = cpu_to_le32(0x00000440); 617 for (i = 14; i < 1024; ++i) 618 msg[i] = cpu_to_le32(0x0); 619 620 return 0; 621 } 622 623 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 624 struct amdgpu_ib *ib) 625 { 626 struct amdgpu_device *adev = ring->adev; 627 uint32_t *msg; 628 int r, i; 629 630 memset(ib, 0, sizeof(*ib)); 631 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2, 632 AMDGPU_IB_POOL_DIRECT, 633 ib); 634 if (r) 635 return r; 636 637 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); 638 msg[0] = cpu_to_le32(0x00000028); 639 msg[1] = cpu_to_le32(0x00000018); 640 msg[2] = cpu_to_le32(0x00000000); 641 msg[3] = cpu_to_le32(0x00000002); 642 msg[4] = cpu_to_le32(handle); 643 msg[5] = cpu_to_le32(0x00000000); 644 for (i = 6; i < 1024; ++i) 645 msg[i] = cpu_to_le32(0x0); 646 647 return 0; 648 } 649 650 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) 651 { 652 struct dma_fence *fence = NULL; 653 struct amdgpu_ib ib; 654 long r; 655 656 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 657 if (r) 658 goto error; 659 660 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); 661 if (r) 662 goto error; 663 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 664 if (r) 665 goto error; 666 667 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); 668 if (r) 669 goto error; 670 671 r = dma_fence_wait_timeout(fence, false, timeout); 672 if (r == 0) 673 r = -ETIMEDOUT; 674 else if (r > 0) 675 r = 0; 676 677 dma_fence_put(fence); 678 error: 679 return r; 680 } 681 682 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 683 struct amdgpu_ib *ib_msg, 684 struct dma_fence **fence) 685 { 686 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 687 const unsigned int ib_size_dw = 64; 688 struct amdgpu_device *adev = ring->adev; 689 struct dma_fence *f = NULL; 690 struct amdgpu_job *job; 691 struct amdgpu_ib *ib; 692 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 693 int i, r; 694 695 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, 696 AMDGPU_IB_POOL_DIRECT, &job); 697 if (r) 698 goto err; 699 700 ib = &job->ibs[0]; 701 ib->length_dw = 0; 702 703 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; 704 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); 705 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); 706 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; 707 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); 708 709 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); 710 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); 711 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); 712 713 for (i = ib->length_dw; i < ib_size_dw; ++i) 714 ib->ptr[i] = 0x0; 715 716 r = amdgpu_job_submit_direct(job, ring, &f); 717 if (r) 718 goto err_free; 719 720 amdgpu_ib_free(adev, ib_msg, f); 721 722 if (fence) 723 *fence = dma_fence_get(f); 724 dma_fence_put(f); 725 726 return 0; 727 728 err_free: 729 amdgpu_job_free(job); 730 err: 731 amdgpu_ib_free(adev, ib_msg, f); 732 return r; 733 } 734 735 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) 736 { 737 struct dma_fence *fence = NULL; 738 struct amdgpu_ib ib; 739 long r; 740 741 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); 742 if (r) 743 goto error; 744 745 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); 746 if (r) 747 goto error; 748 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); 749 if (r) 750 goto error; 751 752 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); 753 if (r) 754 goto error; 755 756 r = dma_fence_wait_timeout(fence, false, timeout); 757 if (r == 0) 758 r = -ETIMEDOUT; 759 else if (r > 0) 760 r = 0; 761 762 dma_fence_put(fence); 763 error: 764 return r; 765 } 766 767 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) 768 { 769 struct amdgpu_device *adev = ring->adev; 770 uint32_t rptr; 771 unsigned i; 772 int r; 773 774 if (amdgpu_sriov_vf(adev)) 775 return 0; 776 777 r = amdgpu_ring_alloc(ring, 16); 778 if (r) 779 return r; 780 781 rptr = amdgpu_ring_get_rptr(ring); 782 783 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 784 amdgpu_ring_commit(ring); 785 786 for (i = 0; i < adev->usec_timeout; i++) { 787 if (amdgpu_ring_get_rptr(ring) != rptr) 788 break; 789 udelay(1); 790 } 791 792 if (i >= adev->usec_timeout) 793 r = -ETIMEDOUT; 794 795 return r; 796 } 797 798 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 799 struct amdgpu_ib *ib_msg, 800 struct dma_fence **fence) 801 { 802 const unsigned ib_size_dw = 16; 803 struct amdgpu_job *job; 804 struct amdgpu_ib *ib; 805 struct dma_fence *f = NULL; 806 uint64_t addr; 807 int i, r; 808 809 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 810 AMDGPU_IB_POOL_DIRECT, &job); 811 if (r) 812 return r; 813 814 ib = &job->ibs[0]; 815 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 816 817 ib->length_dw = 0; 818 ib->ptr[ib->length_dw++] = 0x00000018; 819 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 820 ib->ptr[ib->length_dw++] = handle; 821 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 822 ib->ptr[ib->length_dw++] = addr; 823 ib->ptr[ib->length_dw++] = 0x0000000b; 824 825 ib->ptr[ib->length_dw++] = 0x00000014; 826 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 827 ib->ptr[ib->length_dw++] = 0x0000001c; 828 ib->ptr[ib->length_dw++] = 0x00000000; 829 ib->ptr[ib->length_dw++] = 0x00000000; 830 831 ib->ptr[ib->length_dw++] = 0x00000008; 832 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 833 834 for (i = ib->length_dw; i < ib_size_dw; ++i) 835 ib->ptr[i] = 0x0; 836 837 r = amdgpu_job_submit_direct(job, ring, &f); 838 if (r) 839 goto err; 840 841 if (fence) 842 *fence = dma_fence_get(f); 843 dma_fence_put(f); 844 845 return 0; 846 847 err: 848 amdgpu_job_free(job); 849 return r; 850 } 851 852 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 853 struct amdgpu_ib *ib_msg, 854 struct dma_fence **fence) 855 { 856 const unsigned ib_size_dw = 16; 857 struct amdgpu_job *job; 858 struct amdgpu_ib *ib; 859 struct dma_fence *f = NULL; 860 uint64_t addr; 861 int i, r; 862 863 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 864 AMDGPU_IB_POOL_DIRECT, &job); 865 if (r) 866 return r; 867 868 ib = &job->ibs[0]; 869 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); 870 871 ib->length_dw = 0; 872 ib->ptr[ib->length_dw++] = 0x00000018; 873 ib->ptr[ib->length_dw++] = 0x00000001; 874 ib->ptr[ib->length_dw++] = handle; 875 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 876 ib->ptr[ib->length_dw++] = addr; 877 ib->ptr[ib->length_dw++] = 0x0000000b; 878 879 ib->ptr[ib->length_dw++] = 0x00000014; 880 ib->ptr[ib->length_dw++] = 0x00000002; 881 ib->ptr[ib->length_dw++] = 0x0000001c; 882 ib->ptr[ib->length_dw++] = 0x00000000; 883 ib->ptr[ib->length_dw++] = 0x00000000; 884 885 ib->ptr[ib->length_dw++] = 0x00000008; 886 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 887 888 for (i = ib->length_dw; i < ib_size_dw; ++i) 889 ib->ptr[i] = 0x0; 890 891 r = amdgpu_job_submit_direct(job, ring, &f); 892 if (r) 893 goto err; 894 895 if (fence) 896 *fence = dma_fence_get(f); 897 dma_fence_put(f); 898 899 return 0; 900 901 err: 902 amdgpu_job_free(job); 903 return r; 904 } 905 906 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 907 { 908 struct amdgpu_device *adev = ring->adev; 909 struct dma_fence *fence = NULL; 910 struct amdgpu_ib ib; 911 long r; 912 913 memset(&ib, 0, sizeof(ib)); 914 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE, 915 AMDGPU_IB_POOL_DIRECT, 916 &ib); 917 if (r) 918 return r; 919 920 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); 921 if (r) 922 goto error; 923 924 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); 925 if (r) 926 goto error; 927 928 r = dma_fence_wait_timeout(fence, false, timeout); 929 if (r == 0) 930 r = -ETIMEDOUT; 931 else if (r > 0) 932 r = 0; 933 934 error: 935 amdgpu_ib_free(adev, &ib, fence); 936 dma_fence_put(fence); 937 938 return r; 939 } 940 941 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring) 942 { 943 switch(ring) { 944 case 0: 945 return AMDGPU_RING_PRIO_0; 946 case 1: 947 return AMDGPU_RING_PRIO_1; 948 case 2: 949 return AMDGPU_RING_PRIO_2; 950 default: 951 return AMDGPU_RING_PRIO_0; 952 } 953 } 954 955 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 956 { 957 int i; 958 unsigned int idx; 959 960 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 961 const struct common_firmware_header *hdr; 962 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 963 964 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 965 if (adev->vcn.harvest_config & (1 << i)) 966 continue; 967 /* currently only support 2 FW instances */ 968 if (i >= 2) { 969 dev_info(adev->dev, "More then 2 VCN FW instances!\n"); 970 break; 971 } 972 idx = AMDGPU_UCODE_ID_VCN + i; 973 adev->firmware.ucode[idx].ucode_id = idx; 974 adev->firmware.ucode[idx].fw = adev->vcn.fw; 975 adev->firmware.fw_size += 976 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 977 } 978 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 979 } 980 } 981