1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 /* 1 second timeout */ 43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 44 45 /* Firmware versions for VI */ 46 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 47 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 48 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 49 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 50 51 /* Polaris10/11 firmware version */ 52 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 53 54 /* Firmware Names */ 55 #ifdef CONFIG_DRM_AMDGPU_CIK 56 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 57 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" 58 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" 59 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" 60 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" 61 #endif 62 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 63 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 64 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 65 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 66 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 67 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 68 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 69 70 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 71 72 #define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00) 73 #define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00) 74 #define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00) 75 #define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00) 76 #define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00) 77 78 /** 79 * amdgpu_uvd_cs_ctx - Command submission parser context 80 * 81 * Used for emulating virtual memory support on UVD 4.2. 82 */ 83 struct amdgpu_uvd_cs_ctx { 84 struct amdgpu_cs_parser *parser; 85 unsigned reg, count; 86 unsigned data0, data1; 87 unsigned idx; 88 unsigned ib_idx; 89 90 /* does the IB has a msg command */ 91 bool has_msg_cmd; 92 93 /* minimum buffer sizes */ 94 unsigned *buf_sizes; 95 }; 96 97 #ifdef CONFIG_DRM_AMDGPU_CIK 98 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 99 MODULE_FIRMWARE(FIRMWARE_KABINI); 100 MODULE_FIRMWARE(FIRMWARE_KAVERI); 101 MODULE_FIRMWARE(FIRMWARE_HAWAII); 102 MODULE_FIRMWARE(FIRMWARE_MULLINS); 103 #endif 104 MODULE_FIRMWARE(FIRMWARE_TONGA); 105 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 106 MODULE_FIRMWARE(FIRMWARE_FIJI); 107 MODULE_FIRMWARE(FIRMWARE_STONEY); 108 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 109 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 110 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 111 112 MODULE_FIRMWARE(FIRMWARE_VEGA10); 113 114 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 115 116 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 117 { 118 struct amdgpu_ring *ring; 119 struct amd_sched_rq *rq; 120 unsigned long bo_size; 121 const char *fw_name; 122 const struct common_firmware_header *hdr; 123 unsigned version_major, version_minor, family_id; 124 int i, r; 125 126 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 127 128 switch (adev->asic_type) { 129 #ifdef CONFIG_DRM_AMDGPU_CIK 130 case CHIP_BONAIRE: 131 fw_name = FIRMWARE_BONAIRE; 132 break; 133 case CHIP_KABINI: 134 fw_name = FIRMWARE_KABINI; 135 break; 136 case CHIP_KAVERI: 137 fw_name = FIRMWARE_KAVERI; 138 break; 139 case CHIP_HAWAII: 140 fw_name = FIRMWARE_HAWAII; 141 break; 142 case CHIP_MULLINS: 143 fw_name = FIRMWARE_MULLINS; 144 break; 145 #endif 146 case CHIP_TONGA: 147 fw_name = FIRMWARE_TONGA; 148 break; 149 case CHIP_FIJI: 150 fw_name = FIRMWARE_FIJI; 151 break; 152 case CHIP_CARRIZO: 153 fw_name = FIRMWARE_CARRIZO; 154 break; 155 case CHIP_STONEY: 156 fw_name = FIRMWARE_STONEY; 157 break; 158 case CHIP_POLARIS10: 159 fw_name = FIRMWARE_POLARIS10; 160 break; 161 case CHIP_POLARIS11: 162 fw_name = FIRMWARE_POLARIS11; 163 break; 164 case CHIP_VEGA10: 165 fw_name = FIRMWARE_VEGA10; 166 break; 167 case CHIP_POLARIS12: 168 fw_name = FIRMWARE_POLARIS12; 169 break; 170 default: 171 return -EINVAL; 172 } 173 174 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 175 if (r) { 176 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 177 fw_name); 178 return r; 179 } 180 181 r = amdgpu_ucode_validate(adev->uvd.fw); 182 if (r) { 183 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 184 fw_name); 185 release_firmware(adev->uvd.fw); 186 adev->uvd.fw = NULL; 187 return r; 188 } 189 190 /* Set the default UVD handles that the firmware can handle */ 191 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 192 193 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 194 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 195 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 196 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 197 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 198 version_major, version_minor, family_id); 199 200 /* 201 * Limit the number of UVD handles depending on microcode major 202 * and minor versions. The firmware version which has 40 UVD 203 * instances support is 1.80. So all subsequent versions should 204 * also have the same support. 205 */ 206 if ((version_major > 0x01) || 207 ((version_major == 0x01) && (version_minor >= 0x50))) 208 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 209 210 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 211 (family_id << 8)); 212 213 if ((adev->asic_type == CHIP_POLARIS10 || 214 adev->asic_type == CHIP_POLARIS11) && 215 (adev->uvd.fw_version < FW_1_66_16)) 216 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", 217 version_major, version_minor); 218 219 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 220 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 221 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 222 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 223 224 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 225 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo, 226 &adev->uvd.gpu_addr, &adev->uvd.cpu_addr); 227 if (r) { 228 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 229 return r; 230 } 231 232 ring = &adev->uvd.ring; 233 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; 234 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, 235 rq, amdgpu_sched_jobs, NULL); 236 if (r != 0) { 237 DRM_ERROR("Failed setting up UVD run queue.\n"); 238 return r; 239 } 240 241 for (i = 0; i < adev->uvd.max_handles; ++i) { 242 atomic_set(&adev->uvd.handles[i], 0); 243 adev->uvd.filp[i] = NULL; 244 } 245 246 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 247 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 248 adev->uvd.address_64_bit = true; 249 250 switch (adev->asic_type) { 251 case CHIP_TONGA: 252 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 253 break; 254 case CHIP_CARRIZO: 255 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 256 break; 257 case CHIP_FIJI: 258 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 259 break; 260 case CHIP_STONEY: 261 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 262 break; 263 default: 264 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 265 } 266 267 return 0; 268 } 269 270 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 271 { 272 int i; 273 kfree(adev->uvd.saved_bo); 274 275 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); 276 277 amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo, 278 &adev->uvd.gpu_addr, 279 (void **)&adev->uvd.cpu_addr); 280 281 amdgpu_ring_fini(&adev->uvd.ring); 282 283 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 284 amdgpu_ring_fini(&adev->uvd.ring_enc[i]); 285 286 release_firmware(adev->uvd.fw); 287 288 return 0; 289 } 290 291 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 292 { 293 unsigned size; 294 void *ptr; 295 int i; 296 297 if (adev->uvd.vcpu_bo == NULL) 298 return 0; 299 300 for (i = 0; i < adev->uvd.max_handles; ++i) 301 if (atomic_read(&adev->uvd.handles[i])) 302 break; 303 304 if (i == AMDGPU_MAX_UVD_HANDLES) 305 return 0; 306 307 cancel_delayed_work_sync(&adev->uvd.idle_work); 308 309 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 310 ptr = adev->uvd.cpu_addr; 311 312 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 313 if (!adev->uvd.saved_bo) 314 return -ENOMEM; 315 316 memcpy_fromio(adev->uvd.saved_bo, ptr, size); 317 318 return 0; 319 } 320 321 int amdgpu_uvd_resume(struct amdgpu_device *adev) 322 { 323 unsigned size; 324 void *ptr; 325 326 if (adev->uvd.vcpu_bo == NULL) 327 return -EINVAL; 328 329 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 330 ptr = adev->uvd.cpu_addr; 331 332 if (adev->uvd.saved_bo != NULL) { 333 memcpy_toio(ptr, adev->uvd.saved_bo, size); 334 kfree(adev->uvd.saved_bo); 335 adev->uvd.saved_bo = NULL; 336 } else { 337 const struct common_firmware_header *hdr; 338 unsigned offset; 339 340 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 341 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 342 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 343 memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset, 344 le32_to_cpu(hdr->ucode_size_bytes)); 345 size -= le32_to_cpu(hdr->ucode_size_bytes); 346 ptr += le32_to_cpu(hdr->ucode_size_bytes); 347 } 348 memset_io(ptr, 0, size); 349 } 350 351 return 0; 352 } 353 354 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 355 { 356 struct amdgpu_ring *ring = &adev->uvd.ring; 357 int i, r; 358 359 for (i = 0; i < adev->uvd.max_handles; ++i) { 360 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 361 if (handle != 0 && adev->uvd.filp[i] == filp) { 362 struct dma_fence *fence; 363 364 r = amdgpu_uvd_get_destroy_msg(ring, handle, 365 false, &fence); 366 if (r) { 367 DRM_ERROR("Error destroying UVD (%d)!\n", r); 368 continue; 369 } 370 371 dma_fence_wait(fence, false); 372 dma_fence_put(fence); 373 374 adev->uvd.filp[i] = NULL; 375 atomic_set(&adev->uvd.handles[i], 0); 376 } 377 } 378 } 379 380 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 381 { 382 int i; 383 for (i = 0; i < abo->placement.num_placement; ++i) { 384 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 385 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 386 } 387 } 388 389 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 390 { 391 uint32_t lo, hi; 392 uint64_t addr; 393 394 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 395 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 396 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 397 398 return addr; 399 } 400 401 /** 402 * amdgpu_uvd_cs_pass1 - first parsing round 403 * 404 * @ctx: UVD parser context 405 * 406 * Make sure UVD message and feedback buffers are in VRAM and 407 * nobody is violating an 256MB boundary. 408 */ 409 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 410 { 411 struct ttm_operation_ctx tctx = { false, false }; 412 struct amdgpu_bo_va_mapping *mapping; 413 struct amdgpu_bo *bo; 414 uint32_t cmd; 415 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 416 int r = 0; 417 418 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 419 if (r) { 420 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 421 return r; 422 } 423 424 if (!ctx->parser->adev->uvd.address_64_bit) { 425 /* check if it's a message or feedback command */ 426 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 427 if (cmd == 0x0 || cmd == 0x3) { 428 /* yes, force it into VRAM */ 429 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 430 amdgpu_ttm_placement_from_domain(bo, domain); 431 } 432 amdgpu_uvd_force_into_uvd_segment(bo); 433 434 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 435 } 436 437 return r; 438 } 439 440 /** 441 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 442 * 443 * @msg: pointer to message structure 444 * @buf_sizes: returned buffer sizes 445 * 446 * Peek into the decode message and calculate the necessary buffer sizes. 447 */ 448 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 449 unsigned buf_sizes[]) 450 { 451 unsigned stream_type = msg[4]; 452 unsigned width = msg[6]; 453 unsigned height = msg[7]; 454 unsigned dpb_size = msg[9]; 455 unsigned pitch = msg[28]; 456 unsigned level = msg[57]; 457 458 unsigned width_in_mb = width / 16; 459 unsigned height_in_mb = ALIGN(height / 16, 2); 460 unsigned fs_in_mb = width_in_mb * height_in_mb; 461 462 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 463 unsigned min_ctx_size = ~0; 464 465 image_size = width * height; 466 image_size += image_size / 2; 467 image_size = ALIGN(image_size, 1024); 468 469 switch (stream_type) { 470 case 0: /* H264 */ 471 switch(level) { 472 case 30: 473 num_dpb_buffer = 8100 / fs_in_mb; 474 break; 475 case 31: 476 num_dpb_buffer = 18000 / fs_in_mb; 477 break; 478 case 32: 479 num_dpb_buffer = 20480 / fs_in_mb; 480 break; 481 case 41: 482 num_dpb_buffer = 32768 / fs_in_mb; 483 break; 484 case 42: 485 num_dpb_buffer = 34816 / fs_in_mb; 486 break; 487 case 50: 488 num_dpb_buffer = 110400 / fs_in_mb; 489 break; 490 case 51: 491 num_dpb_buffer = 184320 / fs_in_mb; 492 break; 493 default: 494 num_dpb_buffer = 184320 / fs_in_mb; 495 break; 496 } 497 num_dpb_buffer++; 498 if (num_dpb_buffer > 17) 499 num_dpb_buffer = 17; 500 501 /* reference picture buffer */ 502 min_dpb_size = image_size * num_dpb_buffer; 503 504 /* macroblock context buffer */ 505 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 506 507 /* IT surface buffer */ 508 min_dpb_size += width_in_mb * height_in_mb * 32; 509 break; 510 511 case 1: /* VC1 */ 512 513 /* reference picture buffer */ 514 min_dpb_size = image_size * 3; 515 516 /* CONTEXT_BUFFER */ 517 min_dpb_size += width_in_mb * height_in_mb * 128; 518 519 /* IT surface buffer */ 520 min_dpb_size += width_in_mb * 64; 521 522 /* DB surface buffer */ 523 min_dpb_size += width_in_mb * 128; 524 525 /* BP */ 526 tmp = max(width_in_mb, height_in_mb); 527 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 528 break; 529 530 case 3: /* MPEG2 */ 531 532 /* reference picture buffer */ 533 min_dpb_size = image_size * 3; 534 break; 535 536 case 4: /* MPEG4 */ 537 538 /* reference picture buffer */ 539 min_dpb_size = image_size * 3; 540 541 /* CM */ 542 min_dpb_size += width_in_mb * height_in_mb * 64; 543 544 /* IT surface buffer */ 545 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 546 break; 547 548 case 7: /* H264 Perf */ 549 switch(level) { 550 case 30: 551 num_dpb_buffer = 8100 / fs_in_mb; 552 break; 553 case 31: 554 num_dpb_buffer = 18000 / fs_in_mb; 555 break; 556 case 32: 557 num_dpb_buffer = 20480 / fs_in_mb; 558 break; 559 case 41: 560 num_dpb_buffer = 32768 / fs_in_mb; 561 break; 562 case 42: 563 num_dpb_buffer = 34816 / fs_in_mb; 564 break; 565 case 50: 566 num_dpb_buffer = 110400 / fs_in_mb; 567 break; 568 case 51: 569 num_dpb_buffer = 184320 / fs_in_mb; 570 break; 571 default: 572 num_dpb_buffer = 184320 / fs_in_mb; 573 break; 574 } 575 num_dpb_buffer++; 576 if (num_dpb_buffer > 17) 577 num_dpb_buffer = 17; 578 579 /* reference picture buffer */ 580 min_dpb_size = image_size * num_dpb_buffer; 581 582 if (!adev->uvd.use_ctx_buf){ 583 /* macroblock context buffer */ 584 min_dpb_size += 585 width_in_mb * height_in_mb * num_dpb_buffer * 192; 586 587 /* IT surface buffer */ 588 min_dpb_size += width_in_mb * height_in_mb * 32; 589 } else { 590 /* macroblock context buffer */ 591 min_ctx_size = 592 width_in_mb * height_in_mb * num_dpb_buffer * 192; 593 } 594 break; 595 596 case 8: /* MJPEG */ 597 min_dpb_size = 0; 598 break; 599 600 case 16: /* H265 */ 601 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 602 image_size = ALIGN(image_size, 256); 603 604 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 605 min_dpb_size = image_size * num_dpb_buffer; 606 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 607 * 16 * num_dpb_buffer + 52 * 1024; 608 break; 609 610 default: 611 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 612 return -EINVAL; 613 } 614 615 if (width > pitch) { 616 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 617 return -EINVAL; 618 } 619 620 if (dpb_size < min_dpb_size) { 621 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 622 dpb_size, min_dpb_size); 623 return -EINVAL; 624 } 625 626 buf_sizes[0x1] = dpb_size; 627 buf_sizes[0x2] = image_size; 628 buf_sizes[0x4] = min_ctx_size; 629 return 0; 630 } 631 632 /** 633 * amdgpu_uvd_cs_msg - handle UVD message 634 * 635 * @ctx: UVD parser context 636 * @bo: buffer object containing the message 637 * @offset: offset into the buffer object 638 * 639 * Peek into the UVD message and extract the session id. 640 * Make sure that we don't open up to many sessions. 641 */ 642 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 643 struct amdgpu_bo *bo, unsigned offset) 644 { 645 struct amdgpu_device *adev = ctx->parser->adev; 646 int32_t *msg, msg_type, handle; 647 void *ptr; 648 long r; 649 int i; 650 651 if (offset & 0x3F) { 652 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 653 return -EINVAL; 654 } 655 656 r = amdgpu_bo_kmap(bo, &ptr); 657 if (r) { 658 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); 659 return r; 660 } 661 662 msg = ptr + offset; 663 664 msg_type = msg[1]; 665 handle = msg[2]; 666 667 if (handle == 0) { 668 DRM_ERROR("Invalid UVD handle!\n"); 669 return -EINVAL; 670 } 671 672 switch (msg_type) { 673 case 0: 674 /* it's a create msg, calc image size (width * height) */ 675 amdgpu_bo_kunmap(bo); 676 677 /* try to alloc a new handle */ 678 for (i = 0; i < adev->uvd.max_handles; ++i) { 679 if (atomic_read(&adev->uvd.handles[i]) == handle) { 680 DRM_ERROR("Handle 0x%x already in use!\n", handle); 681 return -EINVAL; 682 } 683 684 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 685 adev->uvd.filp[i] = ctx->parser->filp; 686 return 0; 687 } 688 } 689 690 DRM_ERROR("No more free UVD handles!\n"); 691 return -ENOSPC; 692 693 case 1: 694 /* it's a decode msg, calc buffer sizes */ 695 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 696 amdgpu_bo_kunmap(bo); 697 if (r) 698 return r; 699 700 /* validate the handle */ 701 for (i = 0; i < adev->uvd.max_handles; ++i) { 702 if (atomic_read(&adev->uvd.handles[i]) == handle) { 703 if (adev->uvd.filp[i] != ctx->parser->filp) { 704 DRM_ERROR("UVD handle collision detected!\n"); 705 return -EINVAL; 706 } 707 return 0; 708 } 709 } 710 711 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 712 return -ENOENT; 713 714 case 2: 715 /* it's a destroy msg, free the handle */ 716 for (i = 0; i < adev->uvd.max_handles; ++i) 717 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 718 amdgpu_bo_kunmap(bo); 719 return 0; 720 721 default: 722 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 723 return -EINVAL; 724 } 725 BUG(); 726 return -EINVAL; 727 } 728 729 /** 730 * amdgpu_uvd_cs_pass2 - second parsing round 731 * 732 * @ctx: UVD parser context 733 * 734 * Patch buffer addresses, make sure buffer sizes are correct. 735 */ 736 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 737 { 738 struct amdgpu_bo_va_mapping *mapping; 739 struct amdgpu_bo *bo; 740 uint32_t cmd; 741 uint64_t start, end; 742 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 743 int r; 744 745 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 746 if (r) { 747 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 748 return r; 749 } 750 751 start = amdgpu_bo_gpu_offset(bo); 752 753 end = (mapping->last + 1 - mapping->start); 754 end = end * AMDGPU_GPU_PAGE_SIZE + start; 755 756 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 757 start += addr; 758 759 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 760 lower_32_bits(start)); 761 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 762 upper_32_bits(start)); 763 764 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 765 if (cmd < 0x4) { 766 if ((end - start) < ctx->buf_sizes[cmd]) { 767 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 768 (unsigned)(end - start), 769 ctx->buf_sizes[cmd]); 770 return -EINVAL; 771 } 772 773 } else if (cmd == 0x206) { 774 if ((end - start) < ctx->buf_sizes[4]) { 775 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 776 (unsigned)(end - start), 777 ctx->buf_sizes[4]); 778 return -EINVAL; 779 } 780 } else if ((cmd != 0x100) && (cmd != 0x204)) { 781 DRM_ERROR("invalid UVD command %X!\n", cmd); 782 return -EINVAL; 783 } 784 785 if (!ctx->parser->adev->uvd.address_64_bit) { 786 if ((start >> 28) != ((end - 1) >> 28)) { 787 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 788 start, end); 789 return -EINVAL; 790 } 791 792 if ((cmd == 0 || cmd == 0x3) && 793 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { 794 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 795 start, end); 796 return -EINVAL; 797 } 798 } 799 800 if (cmd == 0) { 801 ctx->has_msg_cmd = true; 802 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 803 if (r) 804 return r; 805 } else if (!ctx->has_msg_cmd) { 806 DRM_ERROR("Message needed before other commands are send!\n"); 807 return -EINVAL; 808 } 809 810 return 0; 811 } 812 813 /** 814 * amdgpu_uvd_cs_reg - parse register writes 815 * 816 * @ctx: UVD parser context 817 * @cb: callback function 818 * 819 * Parse the register writes, call cb on each complete command. 820 */ 821 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 822 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 823 { 824 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 825 int i, r; 826 827 ctx->idx++; 828 for (i = 0; i <= ctx->count; ++i) { 829 unsigned reg = ctx->reg + i; 830 831 if (ctx->idx >= ib->length_dw) { 832 DRM_ERROR("Register command after end of CS!\n"); 833 return -EINVAL; 834 } 835 836 switch (reg) { 837 case mmUVD_GPCOM_VCPU_DATA0: 838 ctx->data0 = ctx->idx; 839 break; 840 case mmUVD_GPCOM_VCPU_DATA1: 841 ctx->data1 = ctx->idx; 842 break; 843 case mmUVD_GPCOM_VCPU_CMD: 844 r = cb(ctx); 845 if (r) 846 return r; 847 break; 848 case mmUVD_ENGINE_CNTL: 849 case mmUVD_NO_OP: 850 break; 851 default: 852 DRM_ERROR("Invalid reg 0x%X!\n", reg); 853 return -EINVAL; 854 } 855 ctx->idx++; 856 } 857 return 0; 858 } 859 860 /** 861 * amdgpu_uvd_cs_packets - parse UVD packets 862 * 863 * @ctx: UVD parser context 864 * @cb: callback function 865 * 866 * Parse the command stream packets. 867 */ 868 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 869 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 870 { 871 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 872 int r; 873 874 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 875 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 876 unsigned type = CP_PACKET_GET_TYPE(cmd); 877 switch (type) { 878 case PACKET_TYPE0: 879 ctx->reg = CP_PACKET0_GET_REG(cmd); 880 ctx->count = CP_PACKET_GET_COUNT(cmd); 881 r = amdgpu_uvd_cs_reg(ctx, cb); 882 if (r) 883 return r; 884 break; 885 case PACKET_TYPE2: 886 ++ctx->idx; 887 break; 888 default: 889 DRM_ERROR("Unknown packet type %d !\n", type); 890 return -EINVAL; 891 } 892 } 893 return 0; 894 } 895 896 /** 897 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 898 * 899 * @parser: Command submission parser context 900 * 901 * Parse the command stream, patch in addresses as necessary. 902 */ 903 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 904 { 905 struct amdgpu_uvd_cs_ctx ctx = {}; 906 unsigned buf_sizes[] = { 907 [0x00000000] = 2048, 908 [0x00000001] = 0xFFFFFFFF, 909 [0x00000002] = 0xFFFFFFFF, 910 [0x00000003] = 2048, 911 [0x00000004] = 0xFFFFFFFF, 912 }; 913 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 914 int r; 915 916 parser->job->vm = NULL; 917 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 918 919 if (ib->length_dw % 16) { 920 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 921 ib->length_dw); 922 return -EINVAL; 923 } 924 925 ctx.parser = parser; 926 ctx.buf_sizes = buf_sizes; 927 ctx.ib_idx = ib_idx; 928 929 /* first round only required on chips without UVD 64 bit address support */ 930 if (!parser->adev->uvd.address_64_bit) { 931 /* first round, make sure the buffers are actually in the UVD segment */ 932 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 933 if (r) 934 return r; 935 } 936 937 /* second round, patch buffer addresses into the command stream */ 938 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 939 if (r) 940 return r; 941 942 if (!ctx.has_msg_cmd) { 943 DRM_ERROR("UVD-IBs need a msg command!\n"); 944 return -EINVAL; 945 } 946 947 return 0; 948 } 949 950 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 951 bool direct, struct dma_fence **fence) 952 { 953 struct ttm_operation_ctx ctx = { true, false }; 954 struct ttm_validate_buffer tv; 955 struct ww_acquire_ctx ticket; 956 struct list_head head; 957 struct amdgpu_job *job; 958 struct amdgpu_ib *ib; 959 struct dma_fence *f = NULL; 960 struct amdgpu_device *adev = ring->adev; 961 uint64_t addr; 962 uint32_t data[4]; 963 int i, r; 964 965 memset(&tv, 0, sizeof(tv)); 966 tv.bo = &bo->tbo; 967 968 INIT_LIST_HEAD(&head); 969 list_add(&tv.head, &head); 970 971 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); 972 if (r) 973 return r; 974 975 if (!ring->adev->uvd.address_64_bit) { 976 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 977 amdgpu_uvd_force_into_uvd_segment(bo); 978 } 979 980 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 981 if (r) 982 goto err; 983 984 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 985 if (r) 986 goto err; 987 988 if (adev->asic_type >= CHIP_VEGA10) { 989 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0); 990 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0); 991 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0); 992 data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0); 993 } else { 994 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); 995 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); 996 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 997 data[3] = PACKET0(mmUVD_NO_OP, 0); 998 } 999 1000 ib = &job->ibs[0]; 1001 addr = amdgpu_bo_gpu_offset(bo); 1002 ib->ptr[0] = data[0]; 1003 ib->ptr[1] = addr; 1004 ib->ptr[2] = data[1]; 1005 ib->ptr[3] = addr >> 32; 1006 ib->ptr[4] = data[2]; 1007 ib->ptr[5] = 0; 1008 for (i = 6; i < 16; i += 2) { 1009 ib->ptr[i] = data[3]; 1010 ib->ptr[i+1] = 0; 1011 } 1012 ib->length_dw = 16; 1013 1014 if (direct) { 1015 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 1016 job->fence = dma_fence_get(f); 1017 if (r) 1018 goto err_free; 1019 1020 amdgpu_job_free(job); 1021 } else { 1022 r = amdgpu_job_submit(job, ring, &adev->uvd.entity, 1023 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1024 if (r) 1025 goto err_free; 1026 } 1027 1028 ttm_eu_fence_buffer_objects(&ticket, &head, f); 1029 1030 if (fence) 1031 *fence = dma_fence_get(f); 1032 amdgpu_bo_unref(&bo); 1033 dma_fence_put(f); 1034 1035 return 0; 1036 1037 err_free: 1038 amdgpu_job_free(job); 1039 1040 err: 1041 ttm_eu_backoff_reservation(&ticket, &head); 1042 return r; 1043 } 1044 1045 /* multiple fence commands without any stream commands in between can 1046 crash the vcpu so just try to emmit a dummy create/destroy msg to 1047 avoid this */ 1048 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1049 struct dma_fence **fence) 1050 { 1051 struct amdgpu_device *adev = ring->adev; 1052 struct amdgpu_bo *bo; 1053 uint32_t *msg; 1054 int r, i; 1055 1056 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 1057 AMDGPU_GEM_DOMAIN_VRAM, 1058 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1059 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1060 NULL, NULL, 0, &bo); 1061 if (r) 1062 return r; 1063 1064 r = amdgpu_bo_reserve(bo, false); 1065 if (r) { 1066 amdgpu_bo_unref(&bo); 1067 return r; 1068 } 1069 1070 r = amdgpu_bo_kmap(bo, (void **)&msg); 1071 if (r) { 1072 amdgpu_bo_unreserve(bo); 1073 amdgpu_bo_unref(&bo); 1074 return r; 1075 } 1076 1077 /* stitch together an UVD create msg */ 1078 msg[0] = cpu_to_le32(0x00000de4); 1079 msg[1] = cpu_to_le32(0x00000000); 1080 msg[2] = cpu_to_le32(handle); 1081 msg[3] = cpu_to_le32(0x00000000); 1082 msg[4] = cpu_to_le32(0x00000000); 1083 msg[5] = cpu_to_le32(0x00000000); 1084 msg[6] = cpu_to_le32(0x00000000); 1085 msg[7] = cpu_to_le32(0x00000780); 1086 msg[8] = cpu_to_le32(0x00000440); 1087 msg[9] = cpu_to_le32(0x00000000); 1088 msg[10] = cpu_to_le32(0x01b37000); 1089 for (i = 11; i < 1024; ++i) 1090 msg[i] = cpu_to_le32(0x0); 1091 1092 amdgpu_bo_kunmap(bo); 1093 amdgpu_bo_unreserve(bo); 1094 1095 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1096 } 1097 1098 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1099 bool direct, struct dma_fence **fence) 1100 { 1101 struct amdgpu_device *adev = ring->adev; 1102 struct amdgpu_bo *bo; 1103 uint32_t *msg; 1104 int r, i; 1105 1106 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 1107 AMDGPU_GEM_DOMAIN_VRAM, 1108 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1109 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1110 NULL, NULL, 0, &bo); 1111 if (r) 1112 return r; 1113 1114 r = amdgpu_bo_reserve(bo, false); 1115 if (r) { 1116 amdgpu_bo_unref(&bo); 1117 return r; 1118 } 1119 1120 r = amdgpu_bo_kmap(bo, (void **)&msg); 1121 if (r) { 1122 amdgpu_bo_unreserve(bo); 1123 amdgpu_bo_unref(&bo); 1124 return r; 1125 } 1126 1127 /* stitch together an UVD destroy msg */ 1128 msg[0] = cpu_to_le32(0x00000de4); 1129 msg[1] = cpu_to_le32(0x00000002); 1130 msg[2] = cpu_to_le32(handle); 1131 msg[3] = cpu_to_le32(0x00000000); 1132 for (i = 4; i < 1024; ++i) 1133 msg[i] = cpu_to_le32(0x0); 1134 1135 amdgpu_bo_kunmap(bo); 1136 amdgpu_bo_unreserve(bo); 1137 1138 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1139 } 1140 1141 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1142 { 1143 struct amdgpu_device *adev = 1144 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1145 unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring); 1146 1147 if (amdgpu_sriov_vf(adev)) 1148 return; 1149 1150 if (fences == 0) { 1151 if (adev->pm.dpm_enabled) { 1152 amdgpu_dpm_enable_uvd(adev, false); 1153 } else { 1154 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1155 /* shutdown the UVD block */ 1156 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1157 AMD_PG_STATE_GATE); 1158 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1159 AMD_CG_STATE_GATE); 1160 } 1161 } else { 1162 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1163 } 1164 } 1165 1166 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1167 { 1168 struct amdgpu_device *adev = ring->adev; 1169 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1170 1171 if (amdgpu_sriov_vf(adev)) 1172 return; 1173 1174 if (set_clocks) { 1175 if (adev->pm.dpm_enabled) { 1176 amdgpu_dpm_enable_uvd(adev, true); 1177 } else { 1178 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1179 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1180 AMD_CG_STATE_UNGATE); 1181 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1182 AMD_PG_STATE_UNGATE); 1183 } 1184 } 1185 } 1186 1187 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1188 { 1189 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1190 } 1191 1192 /** 1193 * amdgpu_uvd_ring_test_ib - test ib execution 1194 * 1195 * @ring: amdgpu_ring pointer 1196 * 1197 * Test if we can successfully execute an IB 1198 */ 1199 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1200 { 1201 struct dma_fence *fence; 1202 long r; 1203 1204 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1205 if (r) { 1206 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); 1207 goto error; 1208 } 1209 1210 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1211 if (r) { 1212 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); 1213 goto error; 1214 } 1215 1216 r = dma_fence_wait_timeout(fence, false, timeout); 1217 if (r == 0) { 1218 DRM_ERROR("amdgpu: IB test timed out.\n"); 1219 r = -ETIMEDOUT; 1220 } else if (r < 0) { 1221 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1222 } else { 1223 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 1224 r = 0; 1225 } 1226 1227 dma_fence_put(fence); 1228 1229 error: 1230 return r; 1231 } 1232 1233 /** 1234 * amdgpu_uvd_used_handles - returns used UVD handles 1235 * 1236 * @adev: amdgpu_device pointer 1237 * 1238 * Returns the number of UVD handles in use 1239 */ 1240 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1241 { 1242 unsigned i; 1243 uint32_t used_handles = 0; 1244 1245 for (i = 0; i < adev->uvd.max_handles; ++i) { 1246 /* 1247 * Handles can be freed in any order, and not 1248 * necessarily linear. So we need to count 1249 * all non-zero handles. 1250 */ 1251 if (atomic_read(&adev->uvd.handles[i])) 1252 used_handles++; 1253 } 1254 1255 return used_handles; 1256 } 1257