1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 /* 1 second timeout */ 43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 44 45 /* Firmware versions for VI */ 46 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 47 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 48 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 49 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 50 51 /* Polaris10/11 firmware version */ 52 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 53 54 /* Firmware Names */ 55 #ifdef CONFIG_DRM_AMDGPU_CIK 56 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 57 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" 58 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" 59 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" 60 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" 61 #endif 62 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 63 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 64 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 65 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 66 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 67 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 68 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 69 70 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 71 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 72 73 #define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00) 74 #define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00) 75 #define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00) 76 #define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00) 77 #define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00) 78 79 /** 80 * amdgpu_uvd_cs_ctx - Command submission parser context 81 * 82 * Used for emulating virtual memory support on UVD 4.2. 83 */ 84 struct amdgpu_uvd_cs_ctx { 85 struct amdgpu_cs_parser *parser; 86 unsigned reg, count; 87 unsigned data0, data1; 88 unsigned idx; 89 unsigned ib_idx; 90 91 /* does the IB has a msg command */ 92 bool has_msg_cmd; 93 94 /* minimum buffer sizes */ 95 unsigned *buf_sizes; 96 }; 97 98 #ifdef CONFIG_DRM_AMDGPU_CIK 99 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 100 MODULE_FIRMWARE(FIRMWARE_KABINI); 101 MODULE_FIRMWARE(FIRMWARE_KAVERI); 102 MODULE_FIRMWARE(FIRMWARE_HAWAII); 103 MODULE_FIRMWARE(FIRMWARE_MULLINS); 104 #endif 105 MODULE_FIRMWARE(FIRMWARE_TONGA); 106 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 107 MODULE_FIRMWARE(FIRMWARE_FIJI); 108 MODULE_FIRMWARE(FIRMWARE_STONEY); 109 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 110 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 111 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 112 113 MODULE_FIRMWARE(FIRMWARE_VEGA10); 114 MODULE_FIRMWARE(FIRMWARE_VEGA12); 115 116 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 117 118 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 119 { 120 struct amdgpu_ring *ring; 121 struct drm_sched_rq *rq; 122 unsigned long bo_size; 123 const char *fw_name; 124 const struct common_firmware_header *hdr; 125 unsigned version_major, version_minor, family_id; 126 int i, r; 127 128 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 129 130 switch (adev->asic_type) { 131 #ifdef CONFIG_DRM_AMDGPU_CIK 132 case CHIP_BONAIRE: 133 fw_name = FIRMWARE_BONAIRE; 134 break; 135 case CHIP_KABINI: 136 fw_name = FIRMWARE_KABINI; 137 break; 138 case CHIP_KAVERI: 139 fw_name = FIRMWARE_KAVERI; 140 break; 141 case CHIP_HAWAII: 142 fw_name = FIRMWARE_HAWAII; 143 break; 144 case CHIP_MULLINS: 145 fw_name = FIRMWARE_MULLINS; 146 break; 147 #endif 148 case CHIP_TONGA: 149 fw_name = FIRMWARE_TONGA; 150 break; 151 case CHIP_FIJI: 152 fw_name = FIRMWARE_FIJI; 153 break; 154 case CHIP_CARRIZO: 155 fw_name = FIRMWARE_CARRIZO; 156 break; 157 case CHIP_STONEY: 158 fw_name = FIRMWARE_STONEY; 159 break; 160 case CHIP_POLARIS10: 161 fw_name = FIRMWARE_POLARIS10; 162 break; 163 case CHIP_POLARIS11: 164 fw_name = FIRMWARE_POLARIS11; 165 break; 166 case CHIP_POLARIS12: 167 fw_name = FIRMWARE_POLARIS12; 168 break; 169 case CHIP_VEGA10: 170 fw_name = FIRMWARE_VEGA10; 171 break; 172 case CHIP_VEGA12: 173 fw_name = FIRMWARE_VEGA12; 174 break; 175 default: 176 return -EINVAL; 177 } 178 179 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 180 if (r) { 181 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 182 fw_name); 183 return r; 184 } 185 186 r = amdgpu_ucode_validate(adev->uvd.fw); 187 if (r) { 188 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 189 fw_name); 190 release_firmware(adev->uvd.fw); 191 adev->uvd.fw = NULL; 192 return r; 193 } 194 195 /* Set the default UVD handles that the firmware can handle */ 196 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 197 198 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 199 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 200 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 201 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 202 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 203 version_major, version_minor, family_id); 204 205 /* 206 * Limit the number of UVD handles depending on microcode major 207 * and minor versions. The firmware version which has 40 UVD 208 * instances support is 1.80. So all subsequent versions should 209 * also have the same support. 210 */ 211 if ((version_major > 0x01) || 212 ((version_major == 0x01) && (version_minor >= 0x50))) 213 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 214 215 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 216 (family_id << 8)); 217 218 if ((adev->asic_type == CHIP_POLARIS10 || 219 adev->asic_type == CHIP_POLARIS11) && 220 (adev->uvd.fw_version < FW_1_66_16)) 221 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", 222 version_major, version_minor); 223 224 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 225 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 226 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 227 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 228 229 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 230 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo, 231 &adev->uvd.gpu_addr, &adev->uvd.cpu_addr); 232 if (r) { 233 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 234 return r; 235 } 236 237 ring = &adev->uvd.ring; 238 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; 239 r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity, 240 rq, amdgpu_sched_jobs, NULL); 241 if (r != 0) { 242 DRM_ERROR("Failed setting up UVD run queue.\n"); 243 return r; 244 } 245 246 for (i = 0; i < adev->uvd.max_handles; ++i) { 247 atomic_set(&adev->uvd.handles[i], 0); 248 adev->uvd.filp[i] = NULL; 249 } 250 251 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 252 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 253 adev->uvd.address_64_bit = true; 254 255 switch (adev->asic_type) { 256 case CHIP_TONGA: 257 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 258 break; 259 case CHIP_CARRIZO: 260 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 261 break; 262 case CHIP_FIJI: 263 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 264 break; 265 case CHIP_STONEY: 266 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 267 break; 268 default: 269 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 270 } 271 272 return 0; 273 } 274 275 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 276 { 277 int i; 278 kfree(adev->uvd.saved_bo); 279 280 drm_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); 281 282 amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo, 283 &adev->uvd.gpu_addr, 284 (void **)&adev->uvd.cpu_addr); 285 286 amdgpu_ring_fini(&adev->uvd.ring); 287 288 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 289 amdgpu_ring_fini(&adev->uvd.ring_enc[i]); 290 291 release_firmware(adev->uvd.fw); 292 293 return 0; 294 } 295 296 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 297 { 298 unsigned size; 299 void *ptr; 300 int i; 301 302 if (adev->uvd.vcpu_bo == NULL) 303 return 0; 304 305 cancel_delayed_work_sync(&adev->uvd.idle_work); 306 307 /* only valid for physical mode */ 308 if (adev->asic_type < CHIP_POLARIS10) { 309 for (i = 0; i < adev->uvd.max_handles; ++i) 310 if (atomic_read(&adev->uvd.handles[i])) 311 break; 312 313 if (i == adev->uvd.max_handles) 314 return 0; 315 } 316 317 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 318 ptr = adev->uvd.cpu_addr; 319 320 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 321 if (!adev->uvd.saved_bo) 322 return -ENOMEM; 323 324 memcpy_fromio(adev->uvd.saved_bo, ptr, size); 325 326 return 0; 327 } 328 329 int amdgpu_uvd_resume(struct amdgpu_device *adev) 330 { 331 unsigned size; 332 void *ptr; 333 334 if (adev->uvd.vcpu_bo == NULL) 335 return -EINVAL; 336 337 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 338 ptr = adev->uvd.cpu_addr; 339 340 if (adev->uvd.saved_bo != NULL) { 341 memcpy_toio(ptr, adev->uvd.saved_bo, size); 342 kfree(adev->uvd.saved_bo); 343 adev->uvd.saved_bo = NULL; 344 } else { 345 const struct common_firmware_header *hdr; 346 unsigned offset; 347 348 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 349 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 350 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 351 memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset, 352 le32_to_cpu(hdr->ucode_size_bytes)); 353 size -= le32_to_cpu(hdr->ucode_size_bytes); 354 ptr += le32_to_cpu(hdr->ucode_size_bytes); 355 } 356 memset_io(ptr, 0, size); 357 /* to restore uvd fence seq */ 358 amdgpu_fence_driver_force_completion(&adev->uvd.ring); 359 } 360 361 return 0; 362 } 363 364 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 365 { 366 struct amdgpu_ring *ring = &adev->uvd.ring; 367 int i, r; 368 369 for (i = 0; i < adev->uvd.max_handles; ++i) { 370 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 371 if (handle != 0 && adev->uvd.filp[i] == filp) { 372 struct dma_fence *fence; 373 374 r = amdgpu_uvd_get_destroy_msg(ring, handle, 375 false, &fence); 376 if (r) { 377 DRM_ERROR("Error destroying UVD (%d)!\n", r); 378 continue; 379 } 380 381 dma_fence_wait(fence, false); 382 dma_fence_put(fence); 383 384 adev->uvd.filp[i] = NULL; 385 atomic_set(&adev->uvd.handles[i], 0); 386 } 387 } 388 } 389 390 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 391 { 392 int i; 393 for (i = 0; i < abo->placement.num_placement; ++i) { 394 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 395 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 396 } 397 } 398 399 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 400 { 401 uint32_t lo, hi; 402 uint64_t addr; 403 404 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 405 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 406 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 407 408 return addr; 409 } 410 411 /** 412 * amdgpu_uvd_cs_pass1 - first parsing round 413 * 414 * @ctx: UVD parser context 415 * 416 * Make sure UVD message and feedback buffers are in VRAM and 417 * nobody is violating an 256MB boundary. 418 */ 419 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 420 { 421 struct ttm_operation_ctx tctx = { false, false }; 422 struct amdgpu_bo_va_mapping *mapping; 423 struct amdgpu_bo *bo; 424 uint32_t cmd; 425 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 426 int r = 0; 427 428 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 429 if (r) { 430 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 431 return r; 432 } 433 434 if (!ctx->parser->adev->uvd.address_64_bit) { 435 /* check if it's a message or feedback command */ 436 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 437 if (cmd == 0x0 || cmd == 0x3) { 438 /* yes, force it into VRAM */ 439 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 440 amdgpu_ttm_placement_from_domain(bo, domain); 441 } 442 amdgpu_uvd_force_into_uvd_segment(bo); 443 444 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 445 } 446 447 return r; 448 } 449 450 /** 451 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 452 * 453 * @msg: pointer to message structure 454 * @buf_sizes: returned buffer sizes 455 * 456 * Peek into the decode message and calculate the necessary buffer sizes. 457 */ 458 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 459 unsigned buf_sizes[]) 460 { 461 unsigned stream_type = msg[4]; 462 unsigned width = msg[6]; 463 unsigned height = msg[7]; 464 unsigned dpb_size = msg[9]; 465 unsigned pitch = msg[28]; 466 unsigned level = msg[57]; 467 468 unsigned width_in_mb = width / 16; 469 unsigned height_in_mb = ALIGN(height / 16, 2); 470 unsigned fs_in_mb = width_in_mb * height_in_mb; 471 472 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 473 unsigned min_ctx_size = ~0; 474 475 image_size = width * height; 476 image_size += image_size / 2; 477 image_size = ALIGN(image_size, 1024); 478 479 switch (stream_type) { 480 case 0: /* H264 */ 481 switch(level) { 482 case 30: 483 num_dpb_buffer = 8100 / fs_in_mb; 484 break; 485 case 31: 486 num_dpb_buffer = 18000 / fs_in_mb; 487 break; 488 case 32: 489 num_dpb_buffer = 20480 / fs_in_mb; 490 break; 491 case 41: 492 num_dpb_buffer = 32768 / fs_in_mb; 493 break; 494 case 42: 495 num_dpb_buffer = 34816 / fs_in_mb; 496 break; 497 case 50: 498 num_dpb_buffer = 110400 / fs_in_mb; 499 break; 500 case 51: 501 num_dpb_buffer = 184320 / fs_in_mb; 502 break; 503 default: 504 num_dpb_buffer = 184320 / fs_in_mb; 505 break; 506 } 507 num_dpb_buffer++; 508 if (num_dpb_buffer > 17) 509 num_dpb_buffer = 17; 510 511 /* reference picture buffer */ 512 min_dpb_size = image_size * num_dpb_buffer; 513 514 /* macroblock context buffer */ 515 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 516 517 /* IT surface buffer */ 518 min_dpb_size += width_in_mb * height_in_mb * 32; 519 break; 520 521 case 1: /* VC1 */ 522 523 /* reference picture buffer */ 524 min_dpb_size = image_size * 3; 525 526 /* CONTEXT_BUFFER */ 527 min_dpb_size += width_in_mb * height_in_mb * 128; 528 529 /* IT surface buffer */ 530 min_dpb_size += width_in_mb * 64; 531 532 /* DB surface buffer */ 533 min_dpb_size += width_in_mb * 128; 534 535 /* BP */ 536 tmp = max(width_in_mb, height_in_mb); 537 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 538 break; 539 540 case 3: /* MPEG2 */ 541 542 /* reference picture buffer */ 543 min_dpb_size = image_size * 3; 544 break; 545 546 case 4: /* MPEG4 */ 547 548 /* reference picture buffer */ 549 min_dpb_size = image_size * 3; 550 551 /* CM */ 552 min_dpb_size += width_in_mb * height_in_mb * 64; 553 554 /* IT surface buffer */ 555 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 556 break; 557 558 case 7: /* H264 Perf */ 559 switch(level) { 560 case 30: 561 num_dpb_buffer = 8100 / fs_in_mb; 562 break; 563 case 31: 564 num_dpb_buffer = 18000 / fs_in_mb; 565 break; 566 case 32: 567 num_dpb_buffer = 20480 / fs_in_mb; 568 break; 569 case 41: 570 num_dpb_buffer = 32768 / fs_in_mb; 571 break; 572 case 42: 573 num_dpb_buffer = 34816 / fs_in_mb; 574 break; 575 case 50: 576 num_dpb_buffer = 110400 / fs_in_mb; 577 break; 578 case 51: 579 num_dpb_buffer = 184320 / fs_in_mb; 580 break; 581 default: 582 num_dpb_buffer = 184320 / fs_in_mb; 583 break; 584 } 585 num_dpb_buffer++; 586 if (num_dpb_buffer > 17) 587 num_dpb_buffer = 17; 588 589 /* reference picture buffer */ 590 min_dpb_size = image_size * num_dpb_buffer; 591 592 if (!adev->uvd.use_ctx_buf){ 593 /* macroblock context buffer */ 594 min_dpb_size += 595 width_in_mb * height_in_mb * num_dpb_buffer * 192; 596 597 /* IT surface buffer */ 598 min_dpb_size += width_in_mb * height_in_mb * 32; 599 } else { 600 /* macroblock context buffer */ 601 min_ctx_size = 602 width_in_mb * height_in_mb * num_dpb_buffer * 192; 603 } 604 break; 605 606 case 8: /* MJPEG */ 607 min_dpb_size = 0; 608 break; 609 610 case 16: /* H265 */ 611 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 612 image_size = ALIGN(image_size, 256); 613 614 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 615 min_dpb_size = image_size * num_dpb_buffer; 616 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 617 * 16 * num_dpb_buffer + 52 * 1024; 618 break; 619 620 default: 621 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 622 return -EINVAL; 623 } 624 625 if (width > pitch) { 626 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 627 return -EINVAL; 628 } 629 630 if (dpb_size < min_dpb_size) { 631 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 632 dpb_size, min_dpb_size); 633 return -EINVAL; 634 } 635 636 buf_sizes[0x1] = dpb_size; 637 buf_sizes[0x2] = image_size; 638 buf_sizes[0x4] = min_ctx_size; 639 return 0; 640 } 641 642 /** 643 * amdgpu_uvd_cs_msg - handle UVD message 644 * 645 * @ctx: UVD parser context 646 * @bo: buffer object containing the message 647 * @offset: offset into the buffer object 648 * 649 * Peek into the UVD message and extract the session id. 650 * Make sure that we don't open up to many sessions. 651 */ 652 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 653 struct amdgpu_bo *bo, unsigned offset) 654 { 655 struct amdgpu_device *adev = ctx->parser->adev; 656 int32_t *msg, msg_type, handle; 657 void *ptr; 658 long r; 659 int i; 660 661 if (offset & 0x3F) { 662 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 663 return -EINVAL; 664 } 665 666 r = amdgpu_bo_kmap(bo, &ptr); 667 if (r) { 668 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); 669 return r; 670 } 671 672 msg = ptr + offset; 673 674 msg_type = msg[1]; 675 handle = msg[2]; 676 677 if (handle == 0) { 678 DRM_ERROR("Invalid UVD handle!\n"); 679 return -EINVAL; 680 } 681 682 switch (msg_type) { 683 case 0: 684 /* it's a create msg, calc image size (width * height) */ 685 amdgpu_bo_kunmap(bo); 686 687 /* try to alloc a new handle */ 688 for (i = 0; i < adev->uvd.max_handles; ++i) { 689 if (atomic_read(&adev->uvd.handles[i]) == handle) { 690 DRM_ERROR("Handle 0x%x already in use!\n", handle); 691 return -EINVAL; 692 } 693 694 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 695 adev->uvd.filp[i] = ctx->parser->filp; 696 return 0; 697 } 698 } 699 700 DRM_ERROR("No more free UVD handles!\n"); 701 return -ENOSPC; 702 703 case 1: 704 /* it's a decode msg, calc buffer sizes */ 705 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 706 amdgpu_bo_kunmap(bo); 707 if (r) 708 return r; 709 710 /* validate the handle */ 711 for (i = 0; i < adev->uvd.max_handles; ++i) { 712 if (atomic_read(&adev->uvd.handles[i]) == handle) { 713 if (adev->uvd.filp[i] != ctx->parser->filp) { 714 DRM_ERROR("UVD handle collision detected!\n"); 715 return -EINVAL; 716 } 717 return 0; 718 } 719 } 720 721 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 722 return -ENOENT; 723 724 case 2: 725 /* it's a destroy msg, free the handle */ 726 for (i = 0; i < adev->uvd.max_handles; ++i) 727 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 728 amdgpu_bo_kunmap(bo); 729 return 0; 730 731 default: 732 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 733 return -EINVAL; 734 } 735 BUG(); 736 return -EINVAL; 737 } 738 739 /** 740 * amdgpu_uvd_cs_pass2 - second parsing round 741 * 742 * @ctx: UVD parser context 743 * 744 * Patch buffer addresses, make sure buffer sizes are correct. 745 */ 746 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 747 { 748 struct amdgpu_bo_va_mapping *mapping; 749 struct amdgpu_bo *bo; 750 uint32_t cmd; 751 uint64_t start, end; 752 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 753 int r; 754 755 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 756 if (r) { 757 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 758 return r; 759 } 760 761 start = amdgpu_bo_gpu_offset(bo); 762 763 end = (mapping->last + 1 - mapping->start); 764 end = end * AMDGPU_GPU_PAGE_SIZE + start; 765 766 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 767 start += addr; 768 769 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 770 lower_32_bits(start)); 771 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 772 upper_32_bits(start)); 773 774 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 775 if (cmd < 0x4) { 776 if ((end - start) < ctx->buf_sizes[cmd]) { 777 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 778 (unsigned)(end - start), 779 ctx->buf_sizes[cmd]); 780 return -EINVAL; 781 } 782 783 } else if (cmd == 0x206) { 784 if ((end - start) < ctx->buf_sizes[4]) { 785 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 786 (unsigned)(end - start), 787 ctx->buf_sizes[4]); 788 return -EINVAL; 789 } 790 } else if ((cmd != 0x100) && (cmd != 0x204)) { 791 DRM_ERROR("invalid UVD command %X!\n", cmd); 792 return -EINVAL; 793 } 794 795 if (!ctx->parser->adev->uvd.address_64_bit) { 796 if ((start >> 28) != ((end - 1) >> 28)) { 797 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 798 start, end); 799 return -EINVAL; 800 } 801 802 if ((cmd == 0 || cmd == 0x3) && 803 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { 804 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 805 start, end); 806 return -EINVAL; 807 } 808 } 809 810 if (cmd == 0) { 811 ctx->has_msg_cmd = true; 812 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 813 if (r) 814 return r; 815 } else if (!ctx->has_msg_cmd) { 816 DRM_ERROR("Message needed before other commands are send!\n"); 817 return -EINVAL; 818 } 819 820 return 0; 821 } 822 823 /** 824 * amdgpu_uvd_cs_reg - parse register writes 825 * 826 * @ctx: UVD parser context 827 * @cb: callback function 828 * 829 * Parse the register writes, call cb on each complete command. 830 */ 831 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 832 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 833 { 834 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 835 int i, r; 836 837 ctx->idx++; 838 for (i = 0; i <= ctx->count; ++i) { 839 unsigned reg = ctx->reg + i; 840 841 if (ctx->idx >= ib->length_dw) { 842 DRM_ERROR("Register command after end of CS!\n"); 843 return -EINVAL; 844 } 845 846 switch (reg) { 847 case mmUVD_GPCOM_VCPU_DATA0: 848 ctx->data0 = ctx->idx; 849 break; 850 case mmUVD_GPCOM_VCPU_DATA1: 851 ctx->data1 = ctx->idx; 852 break; 853 case mmUVD_GPCOM_VCPU_CMD: 854 r = cb(ctx); 855 if (r) 856 return r; 857 break; 858 case mmUVD_ENGINE_CNTL: 859 case mmUVD_NO_OP: 860 break; 861 default: 862 DRM_ERROR("Invalid reg 0x%X!\n", reg); 863 return -EINVAL; 864 } 865 ctx->idx++; 866 } 867 return 0; 868 } 869 870 /** 871 * amdgpu_uvd_cs_packets - parse UVD packets 872 * 873 * @ctx: UVD parser context 874 * @cb: callback function 875 * 876 * Parse the command stream packets. 877 */ 878 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 879 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 880 { 881 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 882 int r; 883 884 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 885 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 886 unsigned type = CP_PACKET_GET_TYPE(cmd); 887 switch (type) { 888 case PACKET_TYPE0: 889 ctx->reg = CP_PACKET0_GET_REG(cmd); 890 ctx->count = CP_PACKET_GET_COUNT(cmd); 891 r = amdgpu_uvd_cs_reg(ctx, cb); 892 if (r) 893 return r; 894 break; 895 case PACKET_TYPE2: 896 ++ctx->idx; 897 break; 898 default: 899 DRM_ERROR("Unknown packet type %d !\n", type); 900 return -EINVAL; 901 } 902 } 903 return 0; 904 } 905 906 /** 907 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 908 * 909 * @parser: Command submission parser context 910 * 911 * Parse the command stream, patch in addresses as necessary. 912 */ 913 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 914 { 915 struct amdgpu_uvd_cs_ctx ctx = {}; 916 unsigned buf_sizes[] = { 917 [0x00000000] = 2048, 918 [0x00000001] = 0xFFFFFFFF, 919 [0x00000002] = 0xFFFFFFFF, 920 [0x00000003] = 2048, 921 [0x00000004] = 0xFFFFFFFF, 922 }; 923 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 924 int r; 925 926 parser->job->vm = NULL; 927 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 928 929 if (ib->length_dw % 16) { 930 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 931 ib->length_dw); 932 return -EINVAL; 933 } 934 935 ctx.parser = parser; 936 ctx.buf_sizes = buf_sizes; 937 ctx.ib_idx = ib_idx; 938 939 /* first round only required on chips without UVD 64 bit address support */ 940 if (!parser->adev->uvd.address_64_bit) { 941 /* first round, make sure the buffers are actually in the UVD segment */ 942 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 943 if (r) 944 return r; 945 } 946 947 /* second round, patch buffer addresses into the command stream */ 948 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 949 if (r) 950 return r; 951 952 if (!ctx.has_msg_cmd) { 953 DRM_ERROR("UVD-IBs need a msg command!\n"); 954 return -EINVAL; 955 } 956 957 return 0; 958 } 959 960 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 961 bool direct, struct dma_fence **fence) 962 { 963 struct amdgpu_device *adev = ring->adev; 964 struct dma_fence *f = NULL; 965 struct amdgpu_job *job; 966 struct amdgpu_ib *ib; 967 uint32_t data[4]; 968 uint64_t addr; 969 long r; 970 int i; 971 972 amdgpu_bo_kunmap(bo); 973 amdgpu_bo_unpin(bo); 974 975 if (!ring->adev->uvd.address_64_bit) { 976 struct ttm_operation_ctx ctx = { true, false }; 977 978 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 979 amdgpu_uvd_force_into_uvd_segment(bo); 980 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 981 if (r) 982 goto err; 983 } 984 985 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 986 if (r) 987 goto err; 988 989 if (adev->asic_type >= CHIP_VEGA10) { 990 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0); 991 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0); 992 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0); 993 data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0); 994 } else { 995 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); 996 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); 997 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 998 data[3] = PACKET0(mmUVD_NO_OP, 0); 999 } 1000 1001 ib = &job->ibs[0]; 1002 addr = amdgpu_bo_gpu_offset(bo); 1003 ib->ptr[0] = data[0]; 1004 ib->ptr[1] = addr; 1005 ib->ptr[2] = data[1]; 1006 ib->ptr[3] = addr >> 32; 1007 ib->ptr[4] = data[2]; 1008 ib->ptr[5] = 0; 1009 for (i = 6; i < 16; i += 2) { 1010 ib->ptr[i] = data[3]; 1011 ib->ptr[i+1] = 0; 1012 } 1013 ib->length_dw = 16; 1014 1015 if (direct) { 1016 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, 1017 true, false, 1018 msecs_to_jiffies(10)); 1019 if (r == 0) 1020 r = -ETIMEDOUT; 1021 if (r < 0) 1022 goto err_free; 1023 1024 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 1025 job->fence = dma_fence_get(f); 1026 if (r) 1027 goto err_free; 1028 1029 amdgpu_job_free(job); 1030 } else { 1031 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, 1032 AMDGPU_FENCE_OWNER_UNDEFINED, false); 1033 if (r) 1034 goto err_free; 1035 1036 r = amdgpu_job_submit(job, ring, &adev->uvd.entity, 1037 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1038 if (r) 1039 goto err_free; 1040 } 1041 1042 amdgpu_bo_fence(bo, f, false); 1043 amdgpu_bo_unreserve(bo); 1044 amdgpu_bo_unref(&bo); 1045 1046 if (fence) 1047 *fence = dma_fence_get(f); 1048 dma_fence_put(f); 1049 1050 return 0; 1051 1052 err_free: 1053 amdgpu_job_free(job); 1054 1055 err: 1056 amdgpu_bo_unreserve(bo); 1057 amdgpu_bo_unref(&bo); 1058 return r; 1059 } 1060 1061 /* multiple fence commands without any stream commands in between can 1062 crash the vcpu so just try to emmit a dummy create/destroy msg to 1063 avoid this */ 1064 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1065 struct dma_fence **fence) 1066 { 1067 struct amdgpu_device *adev = ring->adev; 1068 struct amdgpu_bo *bo = NULL; 1069 uint32_t *msg; 1070 int r, i; 1071 1072 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1073 AMDGPU_GEM_DOMAIN_VRAM, 1074 &bo, NULL, (void **)&msg); 1075 if (r) 1076 return r; 1077 1078 /* stitch together an UVD create msg */ 1079 msg[0] = cpu_to_le32(0x00000de4); 1080 msg[1] = cpu_to_le32(0x00000000); 1081 msg[2] = cpu_to_le32(handle); 1082 msg[3] = cpu_to_le32(0x00000000); 1083 msg[4] = cpu_to_le32(0x00000000); 1084 msg[5] = cpu_to_le32(0x00000000); 1085 msg[6] = cpu_to_le32(0x00000000); 1086 msg[7] = cpu_to_le32(0x00000780); 1087 msg[8] = cpu_to_le32(0x00000440); 1088 msg[9] = cpu_to_le32(0x00000000); 1089 msg[10] = cpu_to_le32(0x01b37000); 1090 for (i = 11; i < 1024; ++i) 1091 msg[i] = cpu_to_le32(0x0); 1092 1093 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1094 } 1095 1096 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1097 bool direct, struct dma_fence **fence) 1098 { 1099 struct amdgpu_device *adev = ring->adev; 1100 struct amdgpu_bo *bo = NULL; 1101 uint32_t *msg; 1102 int r, i; 1103 1104 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1105 AMDGPU_GEM_DOMAIN_VRAM, 1106 &bo, NULL, (void **)&msg); 1107 if (r) 1108 return r; 1109 1110 /* stitch together an UVD destroy msg */ 1111 msg[0] = cpu_to_le32(0x00000de4); 1112 msg[1] = cpu_to_le32(0x00000002); 1113 msg[2] = cpu_to_le32(handle); 1114 msg[3] = cpu_to_le32(0x00000000); 1115 for (i = 4; i < 1024; ++i) 1116 msg[i] = cpu_to_le32(0x0); 1117 1118 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1119 } 1120 1121 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1122 { 1123 struct amdgpu_device *adev = 1124 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1125 unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring); 1126 1127 if (fences == 0) { 1128 if (adev->pm.dpm_enabled) { 1129 amdgpu_dpm_enable_uvd(adev, false); 1130 } else { 1131 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1132 /* shutdown the UVD block */ 1133 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1134 AMD_PG_STATE_GATE); 1135 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1136 AMD_CG_STATE_GATE); 1137 } 1138 } else { 1139 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1140 } 1141 } 1142 1143 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1144 { 1145 struct amdgpu_device *adev = ring->adev; 1146 bool set_clocks; 1147 1148 if (amdgpu_sriov_vf(adev)) 1149 return; 1150 1151 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1152 if (set_clocks) { 1153 if (adev->pm.dpm_enabled) { 1154 amdgpu_dpm_enable_uvd(adev, true); 1155 } else { 1156 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1157 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1158 AMD_CG_STATE_UNGATE); 1159 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1160 AMD_PG_STATE_UNGATE); 1161 } 1162 } 1163 } 1164 1165 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1166 { 1167 if (!amdgpu_sriov_vf(ring->adev)) 1168 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1169 } 1170 1171 /** 1172 * amdgpu_uvd_ring_test_ib - test ib execution 1173 * 1174 * @ring: amdgpu_ring pointer 1175 * 1176 * Test if we can successfully execute an IB 1177 */ 1178 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1179 { 1180 struct dma_fence *fence; 1181 long r; 1182 1183 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1184 if (r) { 1185 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); 1186 goto error; 1187 } 1188 1189 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1190 if (r) { 1191 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); 1192 goto error; 1193 } 1194 1195 r = dma_fence_wait_timeout(fence, false, timeout); 1196 if (r == 0) { 1197 DRM_ERROR("amdgpu: IB test timed out.\n"); 1198 r = -ETIMEDOUT; 1199 } else if (r < 0) { 1200 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1201 } else { 1202 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 1203 r = 0; 1204 } 1205 1206 dma_fence_put(fence); 1207 1208 error: 1209 return r; 1210 } 1211 1212 /** 1213 * amdgpu_uvd_used_handles - returns used UVD handles 1214 * 1215 * @adev: amdgpu_device pointer 1216 * 1217 * Returns the number of UVD handles in use 1218 */ 1219 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1220 { 1221 unsigned i; 1222 uint32_t used_handles = 0; 1223 1224 for (i = 0; i < adev->uvd.max_handles; ++i) { 1225 /* 1226 * Handles can be freed in any order, and not 1227 * necessarily linear. So we need to count 1228 * all non-zero handles. 1229 */ 1230 if (atomic_read(&adev->uvd.handles[i])) 1231 used_handles++; 1232 } 1233 1234 return used_handles; 1235 } 1236