1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 /* 1 second timeout */ 43 #define UVD_IDLE_TIMEOUT_MS 1000 44 45 /* Firmware Names */ 46 #ifdef CONFIG_DRM_AMDGPU_CIK 47 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 48 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" 49 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" 50 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" 51 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" 52 #endif 53 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 54 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 55 56 /** 57 * amdgpu_uvd_cs_ctx - Command submission parser context 58 * 59 * Used for emulating virtual memory support on UVD 4.2. 60 */ 61 struct amdgpu_uvd_cs_ctx { 62 struct amdgpu_cs_parser *parser; 63 unsigned reg, count; 64 unsigned data0, data1; 65 unsigned idx; 66 unsigned ib_idx; 67 68 /* does the IB has a msg command */ 69 bool has_msg_cmd; 70 71 /* minimum buffer sizes */ 72 unsigned *buf_sizes; 73 }; 74 75 #ifdef CONFIG_DRM_AMDGPU_CIK 76 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 77 MODULE_FIRMWARE(FIRMWARE_KABINI); 78 MODULE_FIRMWARE(FIRMWARE_KAVERI); 79 MODULE_FIRMWARE(FIRMWARE_HAWAII); 80 MODULE_FIRMWARE(FIRMWARE_MULLINS); 81 #endif 82 MODULE_FIRMWARE(FIRMWARE_TONGA); 83 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 84 85 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); 86 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 87 88 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 89 { 90 unsigned long bo_size; 91 const char *fw_name; 92 const struct common_firmware_header *hdr; 93 unsigned version_major, version_minor, family_id; 94 int i, r; 95 96 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 97 98 switch (adev->asic_type) { 99 #ifdef CONFIG_DRM_AMDGPU_CIK 100 case CHIP_BONAIRE: 101 fw_name = FIRMWARE_BONAIRE; 102 break; 103 case CHIP_KABINI: 104 fw_name = FIRMWARE_KABINI; 105 break; 106 case CHIP_KAVERI: 107 fw_name = FIRMWARE_KAVERI; 108 break; 109 case CHIP_HAWAII: 110 fw_name = FIRMWARE_HAWAII; 111 break; 112 case CHIP_MULLINS: 113 fw_name = FIRMWARE_MULLINS; 114 break; 115 #endif 116 case CHIP_TONGA: 117 fw_name = FIRMWARE_TONGA; 118 break; 119 case CHIP_CARRIZO: 120 fw_name = FIRMWARE_CARRIZO; 121 break; 122 default: 123 return -EINVAL; 124 } 125 126 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 127 if (r) { 128 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 129 fw_name); 130 return r; 131 } 132 133 r = amdgpu_ucode_validate(adev->uvd.fw); 134 if (r) { 135 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 136 fw_name); 137 release_firmware(adev->uvd.fw); 138 adev->uvd.fw = NULL; 139 return r; 140 } 141 142 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 143 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 144 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 145 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 146 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 147 version_major, version_minor, family_id); 148 149 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) 150 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE; 151 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, 152 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->uvd.vcpu_bo); 153 if (r) { 154 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 155 return r; 156 } 157 158 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 159 if (r) { 160 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 161 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r); 162 return r; 163 } 164 165 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, 166 &adev->uvd.gpu_addr); 167 if (r) { 168 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 169 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 170 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r); 171 return r; 172 } 173 174 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr); 175 if (r) { 176 dev_err(adev->dev, "(%d) UVD map failed\n", r); 177 return r; 178 } 179 180 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 181 182 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 183 atomic_set(&adev->uvd.handles[i], 0); 184 adev->uvd.filp[i] = NULL; 185 } 186 187 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 188 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 189 adev->uvd.address_64_bit = true; 190 191 return 0; 192 } 193 194 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 195 { 196 int r; 197 198 if (adev->uvd.vcpu_bo == NULL) 199 return 0; 200 201 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 202 if (!r) { 203 amdgpu_bo_kunmap(adev->uvd.vcpu_bo); 204 amdgpu_bo_unpin(adev->uvd.vcpu_bo); 205 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 206 } 207 208 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 209 210 amdgpu_ring_fini(&adev->uvd.ring); 211 212 release_firmware(adev->uvd.fw); 213 214 return 0; 215 } 216 217 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 218 { 219 unsigned size; 220 void *ptr; 221 const struct common_firmware_header *hdr; 222 int i; 223 224 if (adev->uvd.vcpu_bo == NULL) 225 return 0; 226 227 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 228 if (atomic_read(&adev->uvd.handles[i])) 229 break; 230 231 if (i == AMDGPU_MAX_UVD_HANDLES) 232 return 0; 233 234 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 235 236 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 237 size -= le32_to_cpu(hdr->ucode_size_bytes); 238 239 ptr = adev->uvd.cpu_addr; 240 ptr += le32_to_cpu(hdr->ucode_size_bytes); 241 242 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 243 memcpy(adev->uvd.saved_bo, ptr, size); 244 245 return 0; 246 } 247 248 int amdgpu_uvd_resume(struct amdgpu_device *adev) 249 { 250 unsigned size; 251 void *ptr; 252 const struct common_firmware_header *hdr; 253 unsigned offset; 254 255 if (adev->uvd.vcpu_bo == NULL) 256 return -EINVAL; 257 258 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 259 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 260 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, 261 (adev->uvd.fw->size) - offset); 262 263 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 264 size -= le32_to_cpu(hdr->ucode_size_bytes); 265 ptr = adev->uvd.cpu_addr; 266 ptr += le32_to_cpu(hdr->ucode_size_bytes); 267 268 if (adev->uvd.saved_bo != NULL) { 269 memcpy(ptr, adev->uvd.saved_bo, size); 270 kfree(adev->uvd.saved_bo); 271 adev->uvd.saved_bo = NULL; 272 } else 273 memset(ptr, 0, size); 274 275 return 0; 276 } 277 278 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 279 { 280 struct amdgpu_ring *ring = &adev->uvd.ring; 281 int i, r; 282 283 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 284 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 285 if (handle != 0 && adev->uvd.filp[i] == filp) { 286 struct amdgpu_fence *fence; 287 288 amdgpu_uvd_note_usage(adev); 289 290 r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence); 291 if (r) { 292 DRM_ERROR("Error destroying UVD (%d)!\n", r); 293 continue; 294 } 295 296 amdgpu_fence_wait(fence, false); 297 amdgpu_fence_unref(&fence); 298 299 adev->uvd.filp[i] = NULL; 300 atomic_set(&adev->uvd.handles[i], 0); 301 } 302 } 303 } 304 305 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) 306 { 307 int i; 308 for (i = 0; i < rbo->placement.num_placement; ++i) { 309 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; 310 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 311 } 312 } 313 314 /** 315 * amdgpu_uvd_cs_pass1 - first parsing round 316 * 317 * @ctx: UVD parser context 318 * 319 * Make sure UVD message and feedback buffers are in VRAM and 320 * nobody is violating an 256MB boundary. 321 */ 322 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 323 { 324 struct amdgpu_bo_va_mapping *mapping; 325 struct amdgpu_bo *bo; 326 uint32_t cmd, lo, hi; 327 uint64_t addr; 328 int r = 0; 329 330 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 331 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 332 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 333 334 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 335 if (mapping == NULL) { 336 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 337 return -EINVAL; 338 } 339 340 if (!ctx->parser->adev->uvd.address_64_bit) { 341 /* check if it's a message or feedback command */ 342 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 343 if (cmd == 0x0 || cmd == 0x3) { 344 /* yes, force it into VRAM */ 345 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 346 amdgpu_ttm_placement_from_domain(bo, domain); 347 } 348 amdgpu_uvd_force_into_uvd_segment(bo); 349 350 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 351 } 352 353 return r; 354 } 355 356 /** 357 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 358 * 359 * @msg: pointer to message structure 360 * @buf_sizes: returned buffer sizes 361 * 362 * Peek into the decode message and calculate the necessary buffer sizes. 363 */ 364 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 365 { 366 unsigned stream_type = msg[4]; 367 unsigned width = msg[6]; 368 unsigned height = msg[7]; 369 unsigned dpb_size = msg[9]; 370 unsigned pitch = msg[28]; 371 unsigned level = msg[57]; 372 373 unsigned width_in_mb = width / 16; 374 unsigned height_in_mb = ALIGN(height / 16, 2); 375 unsigned fs_in_mb = width_in_mb * height_in_mb; 376 377 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 378 379 image_size = width * height; 380 image_size += image_size / 2; 381 image_size = ALIGN(image_size, 1024); 382 383 switch (stream_type) { 384 case 0: /* H264 */ 385 case 7: /* H264 Perf */ 386 switch(level) { 387 case 30: 388 num_dpb_buffer = 8100 / fs_in_mb; 389 break; 390 case 31: 391 num_dpb_buffer = 18000 / fs_in_mb; 392 break; 393 case 32: 394 num_dpb_buffer = 20480 / fs_in_mb; 395 break; 396 case 41: 397 num_dpb_buffer = 32768 / fs_in_mb; 398 break; 399 case 42: 400 num_dpb_buffer = 34816 / fs_in_mb; 401 break; 402 case 50: 403 num_dpb_buffer = 110400 / fs_in_mb; 404 break; 405 case 51: 406 num_dpb_buffer = 184320 / fs_in_mb; 407 break; 408 default: 409 num_dpb_buffer = 184320 / fs_in_mb; 410 break; 411 } 412 num_dpb_buffer++; 413 if (num_dpb_buffer > 17) 414 num_dpb_buffer = 17; 415 416 /* reference picture buffer */ 417 min_dpb_size = image_size * num_dpb_buffer; 418 419 /* macroblock context buffer */ 420 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 421 422 /* IT surface buffer */ 423 min_dpb_size += width_in_mb * height_in_mb * 32; 424 break; 425 426 case 1: /* VC1 */ 427 428 /* reference picture buffer */ 429 min_dpb_size = image_size * 3; 430 431 /* CONTEXT_BUFFER */ 432 min_dpb_size += width_in_mb * height_in_mb * 128; 433 434 /* IT surface buffer */ 435 min_dpb_size += width_in_mb * 64; 436 437 /* DB surface buffer */ 438 min_dpb_size += width_in_mb * 128; 439 440 /* BP */ 441 tmp = max(width_in_mb, height_in_mb); 442 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 443 break; 444 445 case 3: /* MPEG2 */ 446 447 /* reference picture buffer */ 448 min_dpb_size = image_size * 3; 449 break; 450 451 case 4: /* MPEG4 */ 452 453 /* reference picture buffer */ 454 min_dpb_size = image_size * 3; 455 456 /* CM */ 457 min_dpb_size += width_in_mb * height_in_mb * 64; 458 459 /* IT surface buffer */ 460 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 461 break; 462 463 case 16: /* H265 */ 464 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 465 image_size = ALIGN(image_size, 256); 466 467 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 468 min_dpb_size = image_size * num_dpb_buffer; 469 break; 470 471 default: 472 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 473 return -EINVAL; 474 } 475 476 if (width > pitch) { 477 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 478 return -EINVAL; 479 } 480 481 if (dpb_size < min_dpb_size) { 482 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 483 dpb_size, min_dpb_size); 484 return -EINVAL; 485 } 486 487 buf_sizes[0x1] = dpb_size; 488 buf_sizes[0x2] = image_size; 489 return 0; 490 } 491 492 /** 493 * amdgpu_uvd_cs_msg - handle UVD message 494 * 495 * @ctx: UVD parser context 496 * @bo: buffer object containing the message 497 * @offset: offset into the buffer object 498 * 499 * Peek into the UVD message and extract the session id. 500 * Make sure that we don't open up to many sessions. 501 */ 502 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 503 struct amdgpu_bo *bo, unsigned offset) 504 { 505 struct amdgpu_device *adev = ctx->parser->adev; 506 int32_t *msg, msg_type, handle; 507 struct fence *f; 508 void *ptr; 509 510 int i, r; 511 512 if (offset & 0x3F) { 513 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 514 return -EINVAL; 515 } 516 517 f = reservation_object_get_excl(bo->tbo.resv); 518 if (f) { 519 r = amdgpu_fence_wait((struct amdgpu_fence *)f, false); 520 if (r) { 521 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); 522 return r; 523 } 524 } 525 526 r = amdgpu_bo_kmap(bo, &ptr); 527 if (r) { 528 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); 529 return r; 530 } 531 532 msg = ptr + offset; 533 534 msg_type = msg[1]; 535 handle = msg[2]; 536 537 if (handle == 0) { 538 DRM_ERROR("Invalid UVD handle!\n"); 539 return -EINVAL; 540 } 541 542 if (msg_type == 1) { 543 /* it's a decode msg, calc buffer sizes */ 544 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes); 545 amdgpu_bo_kunmap(bo); 546 if (r) 547 return r; 548 549 } else if (msg_type == 2) { 550 /* it's a destroy msg, free the handle */ 551 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 552 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 553 amdgpu_bo_kunmap(bo); 554 return 0; 555 } else { 556 /* it's a create msg */ 557 amdgpu_bo_kunmap(bo); 558 559 if (msg_type != 0) { 560 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 561 return -EINVAL; 562 } 563 564 /* it's a create msg, no special handling needed */ 565 } 566 567 /* create or decode, validate the handle */ 568 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 569 if (atomic_read(&adev->uvd.handles[i]) == handle) 570 return 0; 571 } 572 573 /* handle not found try to alloc a new one */ 574 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 575 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 576 adev->uvd.filp[i] = ctx->parser->filp; 577 return 0; 578 } 579 } 580 581 DRM_ERROR("No more free UVD handles!\n"); 582 return -EINVAL; 583 } 584 585 /** 586 * amdgpu_uvd_cs_pass2 - second parsing round 587 * 588 * @ctx: UVD parser context 589 * 590 * Patch buffer addresses, make sure buffer sizes are correct. 591 */ 592 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 593 { 594 struct amdgpu_bo_va_mapping *mapping; 595 struct amdgpu_bo *bo; 596 struct amdgpu_ib *ib; 597 uint32_t cmd, lo, hi; 598 uint64_t start, end; 599 uint64_t addr; 600 int r; 601 602 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 603 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 604 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 605 606 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 607 if (mapping == NULL) 608 return -EINVAL; 609 610 start = amdgpu_bo_gpu_offset(bo); 611 612 end = (mapping->it.last + 1 - mapping->it.start); 613 end = end * AMDGPU_GPU_PAGE_SIZE + start; 614 615 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; 616 start += addr; 617 618 ib = &ctx->parser->ibs[ctx->ib_idx]; 619 ib->ptr[ctx->data0] = start & 0xFFFFFFFF; 620 ib->ptr[ctx->data1] = start >> 32; 621 622 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 623 if (cmd < 0x4) { 624 if ((end - start) < ctx->buf_sizes[cmd]) { 625 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 626 (unsigned)(end - start), 627 ctx->buf_sizes[cmd]); 628 return -EINVAL; 629 } 630 631 } else if ((cmd != 0x100) && (cmd != 0x204)) { 632 DRM_ERROR("invalid UVD command %X!\n", cmd); 633 return -EINVAL; 634 } 635 636 if (!ctx->parser->adev->uvd.address_64_bit) { 637 if ((start >> 28) != ((end - 1) >> 28)) { 638 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 639 start, end); 640 return -EINVAL; 641 } 642 643 if ((cmd == 0 || cmd == 0x3) && 644 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { 645 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 646 start, end); 647 return -EINVAL; 648 } 649 } 650 651 if (cmd == 0) { 652 ctx->has_msg_cmd = true; 653 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 654 if (r) 655 return r; 656 } else if (!ctx->has_msg_cmd) { 657 DRM_ERROR("Message needed before other commands are send!\n"); 658 return -EINVAL; 659 } 660 661 return 0; 662 } 663 664 /** 665 * amdgpu_uvd_cs_reg - parse register writes 666 * 667 * @ctx: UVD parser context 668 * @cb: callback function 669 * 670 * Parse the register writes, call cb on each complete command. 671 */ 672 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 673 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 674 { 675 struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx]; 676 int i, r; 677 678 ctx->idx++; 679 for (i = 0; i <= ctx->count; ++i) { 680 unsigned reg = ctx->reg + i; 681 682 if (ctx->idx >= ib->length_dw) { 683 DRM_ERROR("Register command after end of CS!\n"); 684 return -EINVAL; 685 } 686 687 switch (reg) { 688 case mmUVD_GPCOM_VCPU_DATA0: 689 ctx->data0 = ctx->idx; 690 break; 691 case mmUVD_GPCOM_VCPU_DATA1: 692 ctx->data1 = ctx->idx; 693 break; 694 case mmUVD_GPCOM_VCPU_CMD: 695 r = cb(ctx); 696 if (r) 697 return r; 698 break; 699 case mmUVD_ENGINE_CNTL: 700 break; 701 default: 702 DRM_ERROR("Invalid reg 0x%X!\n", reg); 703 return -EINVAL; 704 } 705 ctx->idx++; 706 } 707 return 0; 708 } 709 710 /** 711 * amdgpu_uvd_cs_packets - parse UVD packets 712 * 713 * @ctx: UVD parser context 714 * @cb: callback function 715 * 716 * Parse the command stream packets. 717 */ 718 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 719 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 720 { 721 struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx]; 722 int r; 723 724 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 725 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 726 unsigned type = CP_PACKET_GET_TYPE(cmd); 727 switch (type) { 728 case PACKET_TYPE0: 729 ctx->reg = CP_PACKET0_GET_REG(cmd); 730 ctx->count = CP_PACKET_GET_COUNT(cmd); 731 r = amdgpu_uvd_cs_reg(ctx, cb); 732 if (r) 733 return r; 734 break; 735 case PACKET_TYPE2: 736 ++ctx->idx; 737 break; 738 default: 739 DRM_ERROR("Unknown packet type %d !\n", type); 740 return -EINVAL; 741 } 742 } 743 return 0; 744 } 745 746 /** 747 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 748 * 749 * @parser: Command submission parser context 750 * 751 * Parse the command stream, patch in addresses as necessary. 752 */ 753 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 754 { 755 struct amdgpu_uvd_cs_ctx ctx = {}; 756 unsigned buf_sizes[] = { 757 [0x00000000] = 2048, 758 [0x00000001] = 32 * 1024 * 1024, 759 [0x00000002] = 2048 * 1152 * 3, 760 [0x00000003] = 2048, 761 }; 762 struct amdgpu_ib *ib = &parser->ibs[ib_idx]; 763 int r; 764 765 if (ib->length_dw % 16) { 766 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 767 ib->length_dw); 768 return -EINVAL; 769 } 770 771 ctx.parser = parser; 772 ctx.buf_sizes = buf_sizes; 773 ctx.ib_idx = ib_idx; 774 775 /* first round, make sure the buffers are actually in the UVD segment */ 776 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 777 if (r) 778 return r; 779 780 /* second round, patch buffer addresses into the command stream */ 781 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 782 if (r) 783 return r; 784 785 if (!ctx.has_msg_cmd) { 786 DRM_ERROR("UVD-IBs need a msg command!\n"); 787 return -EINVAL; 788 } 789 790 amdgpu_uvd_note_usage(ctx.parser->adev); 791 792 return 0; 793 } 794 795 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, 796 struct amdgpu_bo *bo, 797 struct amdgpu_fence **fence) 798 { 799 struct ttm_validate_buffer tv; 800 struct ww_acquire_ctx ticket; 801 struct list_head head; 802 struct amdgpu_ib ib; 803 uint64_t addr; 804 int i, r; 805 806 memset(&tv, 0, sizeof(tv)); 807 tv.bo = &bo->tbo; 808 809 INIT_LIST_HEAD(&head); 810 list_add(&tv.head, &head); 811 812 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); 813 if (r) 814 return r; 815 816 if (!bo->adev->uvd.address_64_bit) { 817 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 818 amdgpu_uvd_force_into_uvd_segment(bo); 819 } 820 821 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 822 if (r) 823 goto err; 824 825 r = amdgpu_ib_get(ring, NULL, 64, &ib); 826 if (r) 827 goto err; 828 829 addr = amdgpu_bo_gpu_offset(bo); 830 ib.ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); 831 ib.ptr[1] = addr; 832 ib.ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); 833 ib.ptr[3] = addr >> 32; 834 ib.ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 835 ib.ptr[5] = 0; 836 for (i = 6; i < 16; ++i) 837 ib.ptr[i] = PACKET2(0); 838 ib.length_dw = 16; 839 840 r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); 841 if (r) 842 goto err; 843 ttm_eu_fence_buffer_objects(&ticket, &head, &ib.fence->base); 844 845 if (fence) 846 *fence = amdgpu_fence_ref(ib.fence); 847 848 amdgpu_ib_free(ring->adev, &ib); 849 amdgpu_bo_unref(&bo); 850 return 0; 851 852 err: 853 ttm_eu_backoff_reservation(&ticket, &head); 854 return r; 855 } 856 857 /* multiple fence commands without any stream commands in between can 858 crash the vcpu so just try to emmit a dummy create/destroy msg to 859 avoid this */ 860 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 861 struct amdgpu_fence **fence) 862 { 863 struct amdgpu_device *adev = ring->adev; 864 struct amdgpu_bo *bo; 865 uint32_t *msg; 866 int r, i; 867 868 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 869 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo); 870 if (r) 871 return r; 872 873 r = amdgpu_bo_reserve(bo, false); 874 if (r) { 875 amdgpu_bo_unref(&bo); 876 return r; 877 } 878 879 r = amdgpu_bo_kmap(bo, (void **)&msg); 880 if (r) { 881 amdgpu_bo_unreserve(bo); 882 amdgpu_bo_unref(&bo); 883 return r; 884 } 885 886 /* stitch together an UVD create msg */ 887 msg[0] = cpu_to_le32(0x00000de4); 888 msg[1] = cpu_to_le32(0x00000000); 889 msg[2] = cpu_to_le32(handle); 890 msg[3] = cpu_to_le32(0x00000000); 891 msg[4] = cpu_to_le32(0x00000000); 892 msg[5] = cpu_to_le32(0x00000000); 893 msg[6] = cpu_to_le32(0x00000000); 894 msg[7] = cpu_to_le32(0x00000780); 895 msg[8] = cpu_to_le32(0x00000440); 896 msg[9] = cpu_to_le32(0x00000000); 897 msg[10] = cpu_to_le32(0x01b37000); 898 for (i = 11; i < 1024; ++i) 899 msg[i] = cpu_to_le32(0x0); 900 901 amdgpu_bo_kunmap(bo); 902 amdgpu_bo_unreserve(bo); 903 904 return amdgpu_uvd_send_msg(ring, bo, fence); 905 } 906 907 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 908 struct amdgpu_fence **fence) 909 { 910 struct amdgpu_device *adev = ring->adev; 911 struct amdgpu_bo *bo; 912 uint32_t *msg; 913 int r, i; 914 915 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 916 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo); 917 if (r) 918 return r; 919 920 r = amdgpu_bo_reserve(bo, false); 921 if (r) { 922 amdgpu_bo_unref(&bo); 923 return r; 924 } 925 926 r = amdgpu_bo_kmap(bo, (void **)&msg); 927 if (r) { 928 amdgpu_bo_unreserve(bo); 929 amdgpu_bo_unref(&bo); 930 return r; 931 } 932 933 /* stitch together an UVD destroy msg */ 934 msg[0] = cpu_to_le32(0x00000de4); 935 msg[1] = cpu_to_le32(0x00000002); 936 msg[2] = cpu_to_le32(handle); 937 msg[3] = cpu_to_le32(0x00000000); 938 for (i = 4; i < 1024; ++i) 939 msg[i] = cpu_to_le32(0x0); 940 941 amdgpu_bo_kunmap(bo); 942 amdgpu_bo_unreserve(bo); 943 944 return amdgpu_uvd_send_msg(ring, bo, fence); 945 } 946 947 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 948 { 949 struct amdgpu_device *adev = 950 container_of(work, struct amdgpu_device, uvd.idle_work.work); 951 unsigned i, fences, handles = 0; 952 953 fences = amdgpu_fence_count_emitted(&adev->uvd.ring); 954 955 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 956 if (atomic_read(&adev->uvd.handles[i])) 957 ++handles; 958 959 if (fences == 0 && handles == 0) { 960 if (adev->pm.dpm_enabled) { 961 amdgpu_dpm_enable_uvd(adev, false); 962 } else { 963 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 964 } 965 } else { 966 schedule_delayed_work(&adev->uvd.idle_work, 967 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 968 } 969 } 970 971 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev) 972 { 973 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 974 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work, 975 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 976 977 if (set_clocks) { 978 if (adev->pm.dpm_enabled) { 979 amdgpu_dpm_enable_uvd(adev, true); 980 } else { 981 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 982 } 983 } 984 } 985