1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Christian König <deathsimple@vodafone.de>
29  */
30 
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <drm/drmP.h>
34 #include <drm/drm.h>
35 
36 #include "amdgpu.h"
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
39 #include "cikd.h"
40 #include "uvd/uvd_4_2_d.h"
41 
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT	msecs_to_jiffies(1000)
44 
45 /* Firmware versions for VI */
46 #define FW_1_65_10	((1 << 24) | (65 << 16) | (10 << 8))
47 #define FW_1_87_11	((1 << 24) | (87 << 16) | (11 << 8))
48 #define FW_1_87_12	((1 << 24) | (87 << 16) | (12 << 8))
49 #define FW_1_37_15	((1 << 24) | (37 << 16) | (15 << 8))
50 
51 /* Polaris10/11 firmware version */
52 #define FW_1_66_16	((1 << 24) | (66 << 16) | (16 << 8))
53 
54 /* Firmware Names */
55 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #define FIRMWARE_BONAIRE	"amdgpu/bonaire_uvd.bin"
57 #define FIRMWARE_KABINI	"amdgpu/kabini_uvd.bin"
58 #define FIRMWARE_KAVERI	"amdgpu/kaveri_uvd.bin"
59 #define FIRMWARE_HAWAII	"amdgpu/hawaii_uvd.bin"
60 #define FIRMWARE_MULLINS	"amdgpu/mullins_uvd.bin"
61 #endif
62 #define FIRMWARE_TONGA		"amdgpu/tonga_uvd.bin"
63 #define FIRMWARE_CARRIZO	"amdgpu/carrizo_uvd.bin"
64 #define FIRMWARE_FIJI		"amdgpu/fiji_uvd.bin"
65 #define FIRMWARE_STONEY		"amdgpu/stoney_uvd.bin"
66 #define FIRMWARE_POLARIS10	"amdgpu/polaris10_uvd.bin"
67 #define FIRMWARE_POLARIS11	"amdgpu/polaris11_uvd.bin"
68 #define FIRMWARE_POLARIS12	"amdgpu/polaris12_uvd.bin"
69 #define FIRMWARE_VEGAM		"amdgpu/vegam_uvd.bin"
70 
71 #define FIRMWARE_VEGA10		"amdgpu/vega10_uvd.bin"
72 #define FIRMWARE_VEGA12		"amdgpu/vega12_uvd.bin"
73 #define FIRMWARE_VEGA20		"amdgpu/vega20_uvd.bin"
74 
75 /* These are common relative offsets for all asics, from uvd_7_0_offset.h,  */
76 #define UVD_GPCOM_VCPU_CMD		0x03c3
77 #define UVD_GPCOM_VCPU_DATA0	0x03c4
78 #define UVD_GPCOM_VCPU_DATA1	0x03c5
79 #define UVD_NO_OP				0x03ff
80 #define UVD_BASE_SI				0x3800
81 
82 /**
83  * amdgpu_uvd_cs_ctx - Command submission parser context
84  *
85  * Used for emulating virtual memory support on UVD 4.2.
86  */
87 struct amdgpu_uvd_cs_ctx {
88 	struct amdgpu_cs_parser *parser;
89 	unsigned reg, count;
90 	unsigned data0, data1;
91 	unsigned idx;
92 	unsigned ib_idx;
93 
94 	/* does the IB has a msg command */
95 	bool has_msg_cmd;
96 
97 	/* minimum buffer sizes */
98 	unsigned *buf_sizes;
99 };
100 
101 #ifdef CONFIG_DRM_AMDGPU_CIK
102 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
103 MODULE_FIRMWARE(FIRMWARE_KABINI);
104 MODULE_FIRMWARE(FIRMWARE_KAVERI);
105 MODULE_FIRMWARE(FIRMWARE_HAWAII);
106 MODULE_FIRMWARE(FIRMWARE_MULLINS);
107 #endif
108 MODULE_FIRMWARE(FIRMWARE_TONGA);
109 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
110 MODULE_FIRMWARE(FIRMWARE_FIJI);
111 MODULE_FIRMWARE(FIRMWARE_STONEY);
112 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
113 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
114 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
115 MODULE_FIRMWARE(FIRMWARE_VEGAM);
116 
117 MODULE_FIRMWARE(FIRMWARE_VEGA10);
118 MODULE_FIRMWARE(FIRMWARE_VEGA12);
119 MODULE_FIRMWARE(FIRMWARE_VEGA20);
120 
121 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
122 
123 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
124 {
125 	unsigned long bo_size;
126 	const char *fw_name;
127 	const struct common_firmware_header *hdr;
128 	unsigned family_id;
129 	int i, j, r;
130 
131 	INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
132 
133 	switch (adev->asic_type) {
134 #ifdef CONFIG_DRM_AMDGPU_CIK
135 	case CHIP_BONAIRE:
136 		fw_name = FIRMWARE_BONAIRE;
137 		break;
138 	case CHIP_KABINI:
139 		fw_name = FIRMWARE_KABINI;
140 		break;
141 	case CHIP_KAVERI:
142 		fw_name = FIRMWARE_KAVERI;
143 		break;
144 	case CHIP_HAWAII:
145 		fw_name = FIRMWARE_HAWAII;
146 		break;
147 	case CHIP_MULLINS:
148 		fw_name = FIRMWARE_MULLINS;
149 		break;
150 #endif
151 	case CHIP_TONGA:
152 		fw_name = FIRMWARE_TONGA;
153 		break;
154 	case CHIP_FIJI:
155 		fw_name = FIRMWARE_FIJI;
156 		break;
157 	case CHIP_CARRIZO:
158 		fw_name = FIRMWARE_CARRIZO;
159 		break;
160 	case CHIP_STONEY:
161 		fw_name = FIRMWARE_STONEY;
162 		break;
163 	case CHIP_POLARIS10:
164 		fw_name = FIRMWARE_POLARIS10;
165 		break;
166 	case CHIP_POLARIS11:
167 		fw_name = FIRMWARE_POLARIS11;
168 		break;
169 	case CHIP_POLARIS12:
170 		fw_name = FIRMWARE_POLARIS12;
171 		break;
172 	case CHIP_VEGA10:
173 		fw_name = FIRMWARE_VEGA10;
174 		break;
175 	case CHIP_VEGA12:
176 		fw_name = FIRMWARE_VEGA12;
177 		break;
178 	case CHIP_VEGAM:
179 		fw_name = FIRMWARE_VEGAM;
180 		break;
181 	case CHIP_VEGA20:
182 		fw_name = FIRMWARE_VEGA20;
183 		break;
184 	default:
185 		return -EINVAL;
186 	}
187 
188 	r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
189 	if (r) {
190 		dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
191 			fw_name);
192 		return r;
193 	}
194 
195 	r = amdgpu_ucode_validate(adev->uvd.fw);
196 	if (r) {
197 		dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
198 			fw_name);
199 		release_firmware(adev->uvd.fw);
200 		adev->uvd.fw = NULL;
201 		return r;
202 	}
203 
204 	/* Set the default UVD handles that the firmware can handle */
205 	adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
206 
207 	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
208 	family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
209 
210 	if (adev->asic_type < CHIP_VEGA20) {
211 		unsigned version_major, version_minor;
212 
213 		version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
214 		version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
215 		DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
216 			version_major, version_minor, family_id);
217 
218 		/*
219 		 * Limit the number of UVD handles depending on microcode major
220 		 * and minor versions. The firmware version which has 40 UVD
221 		 * instances support is 1.80. So all subsequent versions should
222 		 * also have the same support.
223 		 */
224 		if ((version_major > 0x01) ||
225 		    ((version_major == 0x01) && (version_minor >= 0x50)))
226 			adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
227 
228 		adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
229 					(family_id << 8));
230 
231 		if ((adev->asic_type == CHIP_POLARIS10 ||
232 		     adev->asic_type == CHIP_POLARIS11) &&
233 		    (adev->uvd.fw_version < FW_1_66_16))
234 			DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
235 				  version_major, version_minor);
236 	} else {
237 		unsigned int enc_major, enc_minor, dec_minor;
238 
239 		dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
240 		enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
241 		enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
242 		DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n",
243 			enc_major, enc_minor, dec_minor, family_id);
244 
245 		adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
246 
247 		adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
248 	}
249 
250 	bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
251 		  +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
252 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
253 		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
254 
255 	for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
256 		if (adev->uvd.harvest_config & (1 << j))
257 			continue;
258 		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
259 					    AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
260 					    &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
261 		if (r) {
262 			dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
263 			return r;
264 		}
265 	}
266 
267 	for (i = 0; i < adev->uvd.max_handles; ++i) {
268 		atomic_set(&adev->uvd.handles[i], 0);
269 		adev->uvd.filp[i] = NULL;
270 	}
271 
272 	/* from uvd v5.0 HW addressing capacity increased to 64 bits */
273 	if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
274 		adev->uvd.address_64_bit = true;
275 
276 	switch (adev->asic_type) {
277 	case CHIP_TONGA:
278 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
279 		break;
280 	case CHIP_CARRIZO:
281 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
282 		break;
283 	case CHIP_FIJI:
284 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
285 		break;
286 	case CHIP_STONEY:
287 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
288 		break;
289 	default:
290 		adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
291 	}
292 
293 	return 0;
294 }
295 
296 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
297 {
298 	int i, j;
299 
300 	drm_sched_entity_destroy(&adev->uvd.entity);
301 
302 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
303 		if (adev->uvd.harvest_config & (1 << j))
304 			continue;
305 		kvfree(adev->uvd.inst[j].saved_bo);
306 
307 		amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
308 				      &adev->uvd.inst[j].gpu_addr,
309 				      (void **)&adev->uvd.inst[j].cpu_addr);
310 
311 		amdgpu_ring_fini(&adev->uvd.inst[j].ring);
312 
313 		for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
314 			amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
315 	}
316 	release_firmware(adev->uvd.fw);
317 
318 	return 0;
319 }
320 
321 /**
322  * amdgpu_uvd_entity_init - init entity
323  *
324  * @adev: amdgpu_device pointer
325  *
326  */
327 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
328 {
329 	struct amdgpu_ring *ring;
330 	struct drm_sched_rq *rq;
331 	int r;
332 
333 	ring = &adev->uvd.inst[0].ring;
334 	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
335 	r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL);
336 	if (r) {
337 		DRM_ERROR("Failed setting up UVD kernel entity.\n");
338 		return r;
339 	}
340 
341 	return 0;
342 }
343 
344 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
345 {
346 	unsigned size;
347 	void *ptr;
348 	int i, j;
349 
350 	cancel_delayed_work_sync(&adev->uvd.idle_work);
351 
352 	/* only valid for physical mode */
353 	if (adev->asic_type < CHIP_POLARIS10) {
354 		for (i = 0; i < adev->uvd.max_handles; ++i)
355 			if (atomic_read(&adev->uvd.handles[i]))
356 				break;
357 
358 		if (i == adev->uvd.max_handles)
359 			return 0;
360 	}
361 
362 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
363 		if (adev->uvd.harvest_config & (1 << j))
364 			continue;
365 		if (adev->uvd.inst[j].vcpu_bo == NULL)
366 			continue;
367 
368 		size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
369 		ptr = adev->uvd.inst[j].cpu_addr;
370 
371 		adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);
372 		if (!adev->uvd.inst[j].saved_bo)
373 			return -ENOMEM;
374 
375 		memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
376 	}
377 	return 0;
378 }
379 
380 int amdgpu_uvd_resume(struct amdgpu_device *adev)
381 {
382 	unsigned size;
383 	void *ptr;
384 	int i;
385 
386 	for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
387 		if (adev->uvd.harvest_config & (1 << i))
388 			continue;
389 		if (adev->uvd.inst[i].vcpu_bo == NULL)
390 			return -EINVAL;
391 
392 		size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
393 		ptr = adev->uvd.inst[i].cpu_addr;
394 
395 		if (adev->uvd.inst[i].saved_bo != NULL) {
396 			memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
397 			kvfree(adev->uvd.inst[i].saved_bo);
398 			adev->uvd.inst[i].saved_bo = NULL;
399 		} else {
400 			const struct common_firmware_header *hdr;
401 			unsigned offset;
402 
403 			hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
404 			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
405 				offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
406 				memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
407 					    le32_to_cpu(hdr->ucode_size_bytes));
408 				size -= le32_to_cpu(hdr->ucode_size_bytes);
409 				ptr += le32_to_cpu(hdr->ucode_size_bytes);
410 			}
411 			memset_io(ptr, 0, size);
412 			/* to restore uvd fence seq */
413 			amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
414 		}
415 	}
416 	return 0;
417 }
418 
419 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
420 {
421 	struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
422 	int i, r;
423 
424 	for (i = 0; i < adev->uvd.max_handles; ++i) {
425 		uint32_t handle = atomic_read(&adev->uvd.handles[i]);
426 
427 		if (handle != 0 && adev->uvd.filp[i] == filp) {
428 			struct dma_fence *fence;
429 
430 			r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
431 						       &fence);
432 			if (r) {
433 				DRM_ERROR("Error destroying UVD %d!\n", r);
434 				continue;
435 			}
436 
437 			dma_fence_wait(fence, false);
438 			dma_fence_put(fence);
439 
440 			adev->uvd.filp[i] = NULL;
441 			atomic_set(&adev->uvd.handles[i], 0);
442 		}
443 	}
444 }
445 
446 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
447 {
448 	int i;
449 	for (i = 0; i < abo->placement.num_placement; ++i) {
450 		abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
451 		abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
452 	}
453 }
454 
455 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
456 {
457 	uint32_t lo, hi;
458 	uint64_t addr;
459 
460 	lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
461 	hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
462 	addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
463 
464 	return addr;
465 }
466 
467 /**
468  * amdgpu_uvd_cs_pass1 - first parsing round
469  *
470  * @ctx: UVD parser context
471  *
472  * Make sure UVD message and feedback buffers are in VRAM and
473  * nobody is violating an 256MB boundary.
474  */
475 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
476 {
477 	struct ttm_operation_ctx tctx = { false, false };
478 	struct amdgpu_bo_va_mapping *mapping;
479 	struct amdgpu_bo *bo;
480 	uint32_t cmd;
481 	uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
482 	int r = 0;
483 
484 	r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
485 	if (r) {
486 		DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
487 		return r;
488 	}
489 
490 	if (!ctx->parser->adev->uvd.address_64_bit) {
491 		/* check if it's a message or feedback command */
492 		cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
493 		if (cmd == 0x0 || cmd == 0x3) {
494 			/* yes, force it into VRAM */
495 			uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
496 			amdgpu_bo_placement_from_domain(bo, domain);
497 		}
498 		amdgpu_uvd_force_into_uvd_segment(bo);
499 
500 		r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
501 	}
502 
503 	return r;
504 }
505 
506 /**
507  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
508  *
509  * @msg: pointer to message structure
510  * @buf_sizes: returned buffer sizes
511  *
512  * Peek into the decode message and calculate the necessary buffer sizes.
513  */
514 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
515 	unsigned buf_sizes[])
516 {
517 	unsigned stream_type = msg[4];
518 	unsigned width = msg[6];
519 	unsigned height = msg[7];
520 	unsigned dpb_size = msg[9];
521 	unsigned pitch = msg[28];
522 	unsigned level = msg[57];
523 
524 	unsigned width_in_mb = width / 16;
525 	unsigned height_in_mb = ALIGN(height / 16, 2);
526 	unsigned fs_in_mb = width_in_mb * height_in_mb;
527 
528 	unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
529 	unsigned min_ctx_size = ~0;
530 
531 	image_size = width * height;
532 	image_size += image_size / 2;
533 	image_size = ALIGN(image_size, 1024);
534 
535 	switch (stream_type) {
536 	case 0: /* H264 */
537 		switch(level) {
538 		case 30:
539 			num_dpb_buffer = 8100 / fs_in_mb;
540 			break;
541 		case 31:
542 			num_dpb_buffer = 18000 / fs_in_mb;
543 			break;
544 		case 32:
545 			num_dpb_buffer = 20480 / fs_in_mb;
546 			break;
547 		case 41:
548 			num_dpb_buffer = 32768 / fs_in_mb;
549 			break;
550 		case 42:
551 			num_dpb_buffer = 34816 / fs_in_mb;
552 			break;
553 		case 50:
554 			num_dpb_buffer = 110400 / fs_in_mb;
555 			break;
556 		case 51:
557 			num_dpb_buffer = 184320 / fs_in_mb;
558 			break;
559 		default:
560 			num_dpb_buffer = 184320 / fs_in_mb;
561 			break;
562 		}
563 		num_dpb_buffer++;
564 		if (num_dpb_buffer > 17)
565 			num_dpb_buffer = 17;
566 
567 		/* reference picture buffer */
568 		min_dpb_size = image_size * num_dpb_buffer;
569 
570 		/* macroblock context buffer */
571 		min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
572 
573 		/* IT surface buffer */
574 		min_dpb_size += width_in_mb * height_in_mb * 32;
575 		break;
576 
577 	case 1: /* VC1 */
578 
579 		/* reference picture buffer */
580 		min_dpb_size = image_size * 3;
581 
582 		/* CONTEXT_BUFFER */
583 		min_dpb_size += width_in_mb * height_in_mb * 128;
584 
585 		/* IT surface buffer */
586 		min_dpb_size += width_in_mb * 64;
587 
588 		/* DB surface buffer */
589 		min_dpb_size += width_in_mb * 128;
590 
591 		/* BP */
592 		tmp = max(width_in_mb, height_in_mb);
593 		min_dpb_size += ALIGN(tmp * 7 * 16, 64);
594 		break;
595 
596 	case 3: /* MPEG2 */
597 
598 		/* reference picture buffer */
599 		min_dpb_size = image_size * 3;
600 		break;
601 
602 	case 4: /* MPEG4 */
603 
604 		/* reference picture buffer */
605 		min_dpb_size = image_size * 3;
606 
607 		/* CM */
608 		min_dpb_size += width_in_mb * height_in_mb * 64;
609 
610 		/* IT surface buffer */
611 		min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
612 		break;
613 
614 	case 7: /* H264 Perf */
615 		switch(level) {
616 		case 30:
617 			num_dpb_buffer = 8100 / fs_in_mb;
618 			break;
619 		case 31:
620 			num_dpb_buffer = 18000 / fs_in_mb;
621 			break;
622 		case 32:
623 			num_dpb_buffer = 20480 / fs_in_mb;
624 			break;
625 		case 41:
626 			num_dpb_buffer = 32768 / fs_in_mb;
627 			break;
628 		case 42:
629 			num_dpb_buffer = 34816 / fs_in_mb;
630 			break;
631 		case 50:
632 			num_dpb_buffer = 110400 / fs_in_mb;
633 			break;
634 		case 51:
635 			num_dpb_buffer = 184320 / fs_in_mb;
636 			break;
637 		default:
638 			num_dpb_buffer = 184320 / fs_in_mb;
639 			break;
640 		}
641 		num_dpb_buffer++;
642 		if (num_dpb_buffer > 17)
643 			num_dpb_buffer = 17;
644 
645 		/* reference picture buffer */
646 		min_dpb_size = image_size * num_dpb_buffer;
647 
648 		if (!adev->uvd.use_ctx_buf){
649 			/* macroblock context buffer */
650 			min_dpb_size +=
651 				width_in_mb * height_in_mb * num_dpb_buffer * 192;
652 
653 			/* IT surface buffer */
654 			min_dpb_size += width_in_mb * height_in_mb * 32;
655 		} else {
656 			/* macroblock context buffer */
657 			min_ctx_size =
658 				width_in_mb * height_in_mb * num_dpb_buffer * 192;
659 		}
660 		break;
661 
662 	case 8: /* MJPEG */
663 		min_dpb_size = 0;
664 		break;
665 
666 	case 16: /* H265 */
667 		image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
668 		image_size = ALIGN(image_size, 256);
669 
670 		num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
671 		min_dpb_size = image_size * num_dpb_buffer;
672 		min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
673 					   * 16 * num_dpb_buffer + 52 * 1024;
674 		break;
675 
676 	default:
677 		DRM_ERROR("UVD codec not handled %d!\n", stream_type);
678 		return -EINVAL;
679 	}
680 
681 	if (width > pitch) {
682 		DRM_ERROR("Invalid UVD decoding target pitch!\n");
683 		return -EINVAL;
684 	}
685 
686 	if (dpb_size < min_dpb_size) {
687 		DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
688 			  dpb_size, min_dpb_size);
689 		return -EINVAL;
690 	}
691 
692 	buf_sizes[0x1] = dpb_size;
693 	buf_sizes[0x2] = image_size;
694 	buf_sizes[0x4] = min_ctx_size;
695 	/* store image width to adjust nb memory pstate */
696 	adev->uvd.decode_image_width = width;
697 	return 0;
698 }
699 
700 /**
701  * amdgpu_uvd_cs_msg - handle UVD message
702  *
703  * @ctx: UVD parser context
704  * @bo: buffer object containing the message
705  * @offset: offset into the buffer object
706  *
707  * Peek into the UVD message and extract the session id.
708  * Make sure that we don't open up to many sessions.
709  */
710 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
711 			     struct amdgpu_bo *bo, unsigned offset)
712 {
713 	struct amdgpu_device *adev = ctx->parser->adev;
714 	int32_t *msg, msg_type, handle;
715 	void *ptr;
716 	long r;
717 	int i;
718 
719 	if (offset & 0x3F) {
720 		DRM_ERROR("UVD messages must be 64 byte aligned!\n");
721 		return -EINVAL;
722 	}
723 
724 	r = amdgpu_bo_kmap(bo, &ptr);
725 	if (r) {
726 		DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
727 		return r;
728 	}
729 
730 	msg = ptr + offset;
731 
732 	msg_type = msg[1];
733 	handle = msg[2];
734 
735 	if (handle == 0) {
736 		DRM_ERROR("Invalid UVD handle!\n");
737 		return -EINVAL;
738 	}
739 
740 	switch (msg_type) {
741 	case 0:
742 		/* it's a create msg, calc image size (width * height) */
743 		amdgpu_bo_kunmap(bo);
744 
745 		/* try to alloc a new handle */
746 		for (i = 0; i < adev->uvd.max_handles; ++i) {
747 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
748 				DRM_ERROR(")Handle 0x%x already in use!\n",
749 					  handle);
750 				return -EINVAL;
751 			}
752 
753 			if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
754 				adev->uvd.filp[i] = ctx->parser->filp;
755 				return 0;
756 			}
757 		}
758 
759 		DRM_ERROR("No more free UVD handles!\n");
760 		return -ENOSPC;
761 
762 	case 1:
763 		/* it's a decode msg, calc buffer sizes */
764 		r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
765 		amdgpu_bo_kunmap(bo);
766 		if (r)
767 			return r;
768 
769 		/* validate the handle */
770 		for (i = 0; i < adev->uvd.max_handles; ++i) {
771 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
772 				if (adev->uvd.filp[i] != ctx->parser->filp) {
773 					DRM_ERROR("UVD handle collision detected!\n");
774 					return -EINVAL;
775 				}
776 				return 0;
777 			}
778 		}
779 
780 		DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
781 		return -ENOENT;
782 
783 	case 2:
784 		/* it's a destroy msg, free the handle */
785 		for (i = 0; i < adev->uvd.max_handles; ++i)
786 			atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
787 		amdgpu_bo_kunmap(bo);
788 		return 0;
789 
790 	default:
791 		DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
792 		return -EINVAL;
793 	}
794 	BUG();
795 	return -EINVAL;
796 }
797 
798 /**
799  * amdgpu_uvd_cs_pass2 - second parsing round
800  *
801  * @ctx: UVD parser context
802  *
803  * Patch buffer addresses, make sure buffer sizes are correct.
804  */
805 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
806 {
807 	struct amdgpu_bo_va_mapping *mapping;
808 	struct amdgpu_bo *bo;
809 	uint32_t cmd;
810 	uint64_t start, end;
811 	uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
812 	int r;
813 
814 	r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
815 	if (r) {
816 		DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
817 		return r;
818 	}
819 
820 	start = amdgpu_bo_gpu_offset(bo);
821 
822 	end = (mapping->last + 1 - mapping->start);
823 	end = end * AMDGPU_GPU_PAGE_SIZE + start;
824 
825 	addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
826 	start += addr;
827 
828 	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
829 			    lower_32_bits(start));
830 	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
831 			    upper_32_bits(start));
832 
833 	cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
834 	if (cmd < 0x4) {
835 		if ((end - start) < ctx->buf_sizes[cmd]) {
836 			DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
837 				  (unsigned)(end - start),
838 				  ctx->buf_sizes[cmd]);
839 			return -EINVAL;
840 		}
841 
842 	} else if (cmd == 0x206) {
843 		if ((end - start) < ctx->buf_sizes[4]) {
844 			DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
845 					  (unsigned)(end - start),
846 					  ctx->buf_sizes[4]);
847 			return -EINVAL;
848 		}
849 	} else if ((cmd != 0x100) && (cmd != 0x204)) {
850 		DRM_ERROR("invalid UVD command %X!\n", cmd);
851 		return -EINVAL;
852 	}
853 
854 	if (!ctx->parser->adev->uvd.address_64_bit) {
855 		if ((start >> 28) != ((end - 1) >> 28)) {
856 			DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
857 				  start, end);
858 			return -EINVAL;
859 		}
860 
861 		if ((cmd == 0 || cmd == 0x3) &&
862 		    (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
863 			DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
864 				  start, end);
865 			return -EINVAL;
866 		}
867 	}
868 
869 	if (cmd == 0) {
870 		ctx->has_msg_cmd = true;
871 		r = amdgpu_uvd_cs_msg(ctx, bo, addr);
872 		if (r)
873 			return r;
874 	} else if (!ctx->has_msg_cmd) {
875 		DRM_ERROR("Message needed before other commands are send!\n");
876 		return -EINVAL;
877 	}
878 
879 	return 0;
880 }
881 
882 /**
883  * amdgpu_uvd_cs_reg - parse register writes
884  *
885  * @ctx: UVD parser context
886  * @cb: callback function
887  *
888  * Parse the register writes, call cb on each complete command.
889  */
890 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
891 			     int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
892 {
893 	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
894 	int i, r;
895 
896 	ctx->idx++;
897 	for (i = 0; i <= ctx->count; ++i) {
898 		unsigned reg = ctx->reg + i;
899 
900 		if (ctx->idx >= ib->length_dw) {
901 			DRM_ERROR("Register command after end of CS!\n");
902 			return -EINVAL;
903 		}
904 
905 		switch (reg) {
906 		case mmUVD_GPCOM_VCPU_DATA0:
907 			ctx->data0 = ctx->idx;
908 			break;
909 		case mmUVD_GPCOM_VCPU_DATA1:
910 			ctx->data1 = ctx->idx;
911 			break;
912 		case mmUVD_GPCOM_VCPU_CMD:
913 			r = cb(ctx);
914 			if (r)
915 				return r;
916 			break;
917 		case mmUVD_ENGINE_CNTL:
918 		case mmUVD_NO_OP:
919 			break;
920 		default:
921 			DRM_ERROR("Invalid reg 0x%X!\n", reg);
922 			return -EINVAL;
923 		}
924 		ctx->idx++;
925 	}
926 	return 0;
927 }
928 
929 /**
930  * amdgpu_uvd_cs_packets - parse UVD packets
931  *
932  * @ctx: UVD parser context
933  * @cb: callback function
934  *
935  * Parse the command stream packets.
936  */
937 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
938 				 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
939 {
940 	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
941 	int r;
942 
943 	for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
944 		uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
945 		unsigned type = CP_PACKET_GET_TYPE(cmd);
946 		switch (type) {
947 		case PACKET_TYPE0:
948 			ctx->reg = CP_PACKET0_GET_REG(cmd);
949 			ctx->count = CP_PACKET_GET_COUNT(cmd);
950 			r = amdgpu_uvd_cs_reg(ctx, cb);
951 			if (r)
952 				return r;
953 			break;
954 		case PACKET_TYPE2:
955 			++ctx->idx;
956 			break;
957 		default:
958 			DRM_ERROR("Unknown packet type %d !\n", type);
959 			return -EINVAL;
960 		}
961 	}
962 	return 0;
963 }
964 
965 /**
966  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
967  *
968  * @parser: Command submission parser context
969  *
970  * Parse the command stream, patch in addresses as necessary.
971  */
972 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
973 {
974 	struct amdgpu_uvd_cs_ctx ctx = {};
975 	unsigned buf_sizes[] = {
976 		[0x00000000]	=	2048,
977 		[0x00000001]	=	0xFFFFFFFF,
978 		[0x00000002]	=	0xFFFFFFFF,
979 		[0x00000003]	=	2048,
980 		[0x00000004]	=	0xFFFFFFFF,
981 	};
982 	struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
983 	int r;
984 
985 	parser->job->vm = NULL;
986 	ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
987 
988 	if (ib->length_dw % 16) {
989 		DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
990 			  ib->length_dw);
991 		return -EINVAL;
992 	}
993 
994 	ctx.parser = parser;
995 	ctx.buf_sizes = buf_sizes;
996 	ctx.ib_idx = ib_idx;
997 
998 	/* first round only required on chips without UVD 64 bit address support */
999 	if (!parser->adev->uvd.address_64_bit) {
1000 		/* first round, make sure the buffers are actually in the UVD segment */
1001 		r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
1002 		if (r)
1003 			return r;
1004 	}
1005 
1006 	/* second round, patch buffer addresses into the command stream */
1007 	r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
1008 	if (r)
1009 		return r;
1010 
1011 	if (!ctx.has_msg_cmd) {
1012 		DRM_ERROR("UVD-IBs need a msg command!\n");
1013 		return -EINVAL;
1014 	}
1015 
1016 	return 0;
1017 }
1018 
1019 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
1020 			       bool direct, struct dma_fence **fence)
1021 {
1022 	struct amdgpu_device *adev = ring->adev;
1023 	struct dma_fence *f = NULL;
1024 	struct amdgpu_job *job;
1025 	struct amdgpu_ib *ib;
1026 	uint32_t data[4];
1027 	uint64_t addr;
1028 	long r;
1029 	int i;
1030 	unsigned offset_idx = 0;
1031 	unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
1032 
1033 	amdgpu_bo_kunmap(bo);
1034 	amdgpu_bo_unpin(bo);
1035 
1036 	if (!ring->adev->uvd.address_64_bit) {
1037 		struct ttm_operation_ctx ctx = { true, false };
1038 
1039 		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
1040 		amdgpu_uvd_force_into_uvd_segment(bo);
1041 		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1042 		if (r)
1043 			goto err;
1044 	}
1045 
1046 	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
1047 	if (r)
1048 		goto err;
1049 
1050 	if (adev->asic_type >= CHIP_VEGA10) {
1051 		offset_idx = 1 + ring->me;
1052 		offset[1] = adev->reg_offset[UVD_HWIP][0][1];
1053 		offset[2] = adev->reg_offset[UVD_HWIP][1][1];
1054 	}
1055 
1056 	data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1057 	data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1058 	data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1059 	data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
1060 
1061 	ib = &job->ibs[0];
1062 	addr = amdgpu_bo_gpu_offset(bo);
1063 	ib->ptr[0] = data[0];
1064 	ib->ptr[1] = addr;
1065 	ib->ptr[2] = data[1];
1066 	ib->ptr[3] = addr >> 32;
1067 	ib->ptr[4] = data[2];
1068 	ib->ptr[5] = 0;
1069 	for (i = 6; i < 16; i += 2) {
1070 		ib->ptr[i] = data[3];
1071 		ib->ptr[i+1] = 0;
1072 	}
1073 	ib->length_dw = 16;
1074 
1075 	if (direct) {
1076 		r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
1077 							true, false,
1078 							msecs_to_jiffies(10));
1079 		if (r == 0)
1080 			r = -ETIMEDOUT;
1081 		if (r < 0)
1082 			goto err_free;
1083 
1084 		r = amdgpu_job_submit_direct(job, ring, &f);
1085 		if (r)
1086 			goto err_free;
1087 	} else {
1088 		r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
1089 				     AMDGPU_FENCE_OWNER_UNDEFINED, false);
1090 		if (r)
1091 			goto err_free;
1092 
1093 		r = amdgpu_job_submit(job, &adev->uvd.entity,
1094 				      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
1095 		if (r)
1096 			goto err_free;
1097 	}
1098 
1099 	amdgpu_bo_fence(bo, f, false);
1100 	amdgpu_bo_unreserve(bo);
1101 	amdgpu_bo_unref(&bo);
1102 
1103 	if (fence)
1104 		*fence = dma_fence_get(f);
1105 	dma_fence_put(f);
1106 
1107 	return 0;
1108 
1109 err_free:
1110 	amdgpu_job_free(job);
1111 
1112 err:
1113 	amdgpu_bo_unreserve(bo);
1114 	amdgpu_bo_unref(&bo);
1115 	return r;
1116 }
1117 
1118 /* multiple fence commands without any stream commands in between can
1119    crash the vcpu so just try to emmit a dummy create/destroy msg to
1120    avoid this */
1121 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1122 			      struct dma_fence **fence)
1123 {
1124 	struct amdgpu_device *adev = ring->adev;
1125 	struct amdgpu_bo *bo = NULL;
1126 	uint32_t *msg;
1127 	int r, i;
1128 
1129 	r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1130 				      AMDGPU_GEM_DOMAIN_VRAM,
1131 				      &bo, NULL, (void **)&msg);
1132 	if (r)
1133 		return r;
1134 
1135 	/* stitch together an UVD create msg */
1136 	msg[0] = cpu_to_le32(0x00000de4);
1137 	msg[1] = cpu_to_le32(0x00000000);
1138 	msg[2] = cpu_to_le32(handle);
1139 	msg[3] = cpu_to_le32(0x00000000);
1140 	msg[4] = cpu_to_le32(0x00000000);
1141 	msg[5] = cpu_to_le32(0x00000000);
1142 	msg[6] = cpu_to_le32(0x00000000);
1143 	msg[7] = cpu_to_le32(0x00000780);
1144 	msg[8] = cpu_to_le32(0x00000440);
1145 	msg[9] = cpu_to_le32(0x00000000);
1146 	msg[10] = cpu_to_le32(0x01b37000);
1147 	for (i = 11; i < 1024; ++i)
1148 		msg[i] = cpu_to_le32(0x0);
1149 
1150 	return amdgpu_uvd_send_msg(ring, bo, true, fence);
1151 }
1152 
1153 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1154 			       bool direct, struct dma_fence **fence)
1155 {
1156 	struct amdgpu_device *adev = ring->adev;
1157 	struct amdgpu_bo *bo = NULL;
1158 	uint32_t *msg;
1159 	int r, i;
1160 
1161 	r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1162 				      AMDGPU_GEM_DOMAIN_VRAM,
1163 				      &bo, NULL, (void **)&msg);
1164 	if (r)
1165 		return r;
1166 
1167 	/* stitch together an UVD destroy msg */
1168 	msg[0] = cpu_to_le32(0x00000de4);
1169 	msg[1] = cpu_to_le32(0x00000002);
1170 	msg[2] = cpu_to_le32(handle);
1171 	msg[3] = cpu_to_le32(0x00000000);
1172 	for (i = 4; i < 1024; ++i)
1173 		msg[i] = cpu_to_le32(0x0);
1174 
1175 	return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1176 }
1177 
1178 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1179 {
1180 	struct amdgpu_device *adev =
1181 		container_of(work, struct amdgpu_device, uvd.idle_work.work);
1182 	unsigned fences = 0, i, j;
1183 
1184 	for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1185 		if (adev->uvd.harvest_config & (1 << i))
1186 			continue;
1187 		fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1188 		for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
1189 			fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1190 		}
1191 	}
1192 
1193 	if (fences == 0) {
1194 		if (adev->pm.dpm_enabled) {
1195 			amdgpu_dpm_enable_uvd(adev, false);
1196 		} else {
1197 			amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1198 			/* shutdown the UVD block */
1199 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1200 							       AMD_PG_STATE_GATE);
1201 			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1202 							       AMD_CG_STATE_GATE);
1203 		}
1204 	} else {
1205 		schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1206 	}
1207 }
1208 
1209 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1210 {
1211 	struct amdgpu_device *adev = ring->adev;
1212 	bool set_clocks;
1213 
1214 	if (amdgpu_sriov_vf(adev))
1215 		return;
1216 
1217 	set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1218 	if (set_clocks) {
1219 		if (adev->pm.dpm_enabled) {
1220 			amdgpu_dpm_enable_uvd(adev, true);
1221 		} else {
1222 			amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1223 			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1224 							       AMD_CG_STATE_UNGATE);
1225 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1226 							       AMD_PG_STATE_UNGATE);
1227 		}
1228 	}
1229 }
1230 
1231 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1232 {
1233 	if (!amdgpu_sriov_vf(ring->adev))
1234 		schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1235 }
1236 
1237 /**
1238  * amdgpu_uvd_ring_test_ib - test ib execution
1239  *
1240  * @ring: amdgpu_ring pointer
1241  *
1242  * Test if we can successfully execute an IB
1243  */
1244 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1245 {
1246 	struct dma_fence *fence;
1247 	long r;
1248 
1249 	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1250 	if (r)
1251 		goto error;
1252 
1253 	r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1254 	if (r)
1255 		goto error;
1256 
1257 	r = dma_fence_wait_timeout(fence, false, timeout);
1258 	if (r == 0)
1259 		r = -ETIMEDOUT;
1260 	else if (r > 0)
1261 		r = 0;
1262 
1263 	dma_fence_put(fence);
1264 
1265 error:
1266 	return r;
1267 }
1268 
1269 /**
1270  * amdgpu_uvd_used_handles - returns used UVD handles
1271  *
1272  * @adev: amdgpu_device pointer
1273  *
1274  * Returns the number of UVD handles in use
1275  */
1276 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1277 {
1278 	unsigned i;
1279 	uint32_t used_handles = 0;
1280 
1281 	for (i = 0; i < adev->uvd.max_handles; ++i) {
1282 		/*
1283 		 * Handles can be freed in any order, and not
1284 		 * necessarily linear. So we need to count
1285 		 * all non-zero handles.
1286 		 */
1287 		if (atomic_read(&adev->uvd.handles[i]))
1288 			used_handles++;
1289 	}
1290 
1291 	return used_handles;
1292 }
1293