1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 #include "amdgpu_ras.h" 43 44 /* 1 second timeout */ 45 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 46 47 /* Firmware versions for VI */ 48 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 49 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 50 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 51 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 52 53 /* Polaris10/11 firmware version */ 54 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 55 56 /* Firmware Names */ 57 #ifdef CONFIG_DRM_AMDGPU_CIK 58 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 59 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 60 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 61 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 62 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 63 #endif 64 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 65 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 66 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 67 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 68 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 69 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 70 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 71 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 72 73 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 74 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 75 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 76 77 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 78 #define UVD_GPCOM_VCPU_CMD 0x03c3 79 #define UVD_GPCOM_VCPU_DATA0 0x03c4 80 #define UVD_GPCOM_VCPU_DATA1 0x03c5 81 #define UVD_NO_OP 0x03ff 82 #define UVD_BASE_SI 0x3800 83 84 /** 85 * amdgpu_uvd_cs_ctx - Command submission parser context 86 * 87 * Used for emulating virtual memory support on UVD 4.2. 88 */ 89 struct amdgpu_uvd_cs_ctx { 90 struct amdgpu_cs_parser *parser; 91 unsigned reg, count; 92 unsigned data0, data1; 93 unsigned idx; 94 unsigned ib_idx; 95 96 /* does the IB has a msg command */ 97 bool has_msg_cmd; 98 99 /* minimum buffer sizes */ 100 unsigned *buf_sizes; 101 }; 102 103 #ifdef CONFIG_DRM_AMDGPU_CIK 104 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 105 MODULE_FIRMWARE(FIRMWARE_KABINI); 106 MODULE_FIRMWARE(FIRMWARE_KAVERI); 107 MODULE_FIRMWARE(FIRMWARE_HAWAII); 108 MODULE_FIRMWARE(FIRMWARE_MULLINS); 109 #endif 110 MODULE_FIRMWARE(FIRMWARE_TONGA); 111 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 112 MODULE_FIRMWARE(FIRMWARE_FIJI); 113 MODULE_FIRMWARE(FIRMWARE_STONEY); 114 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 115 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 116 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 117 MODULE_FIRMWARE(FIRMWARE_VEGAM); 118 119 MODULE_FIRMWARE(FIRMWARE_VEGA10); 120 MODULE_FIRMWARE(FIRMWARE_VEGA12); 121 MODULE_FIRMWARE(FIRMWARE_VEGA20); 122 123 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 124 125 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 126 { 127 unsigned long bo_size; 128 const char *fw_name; 129 const struct common_firmware_header *hdr; 130 unsigned family_id; 131 int i, j, r; 132 133 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 134 135 switch (adev->asic_type) { 136 #ifdef CONFIG_DRM_AMDGPU_CIK 137 case CHIP_BONAIRE: 138 fw_name = FIRMWARE_BONAIRE; 139 break; 140 case CHIP_KABINI: 141 fw_name = FIRMWARE_KABINI; 142 break; 143 case CHIP_KAVERI: 144 fw_name = FIRMWARE_KAVERI; 145 break; 146 case CHIP_HAWAII: 147 fw_name = FIRMWARE_HAWAII; 148 break; 149 case CHIP_MULLINS: 150 fw_name = FIRMWARE_MULLINS; 151 break; 152 #endif 153 case CHIP_TONGA: 154 fw_name = FIRMWARE_TONGA; 155 break; 156 case CHIP_FIJI: 157 fw_name = FIRMWARE_FIJI; 158 break; 159 case CHIP_CARRIZO: 160 fw_name = FIRMWARE_CARRIZO; 161 break; 162 case CHIP_STONEY: 163 fw_name = FIRMWARE_STONEY; 164 break; 165 case CHIP_POLARIS10: 166 fw_name = FIRMWARE_POLARIS10; 167 break; 168 case CHIP_POLARIS11: 169 fw_name = FIRMWARE_POLARIS11; 170 break; 171 case CHIP_POLARIS12: 172 fw_name = FIRMWARE_POLARIS12; 173 break; 174 case CHIP_VEGA10: 175 fw_name = FIRMWARE_VEGA10; 176 break; 177 case CHIP_VEGA12: 178 fw_name = FIRMWARE_VEGA12; 179 break; 180 case CHIP_VEGAM: 181 fw_name = FIRMWARE_VEGAM; 182 break; 183 case CHIP_VEGA20: 184 fw_name = FIRMWARE_VEGA20; 185 break; 186 default: 187 return -EINVAL; 188 } 189 190 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 191 if (r) { 192 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 193 fw_name); 194 return r; 195 } 196 197 r = amdgpu_ucode_validate(adev->uvd.fw); 198 if (r) { 199 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 200 fw_name); 201 release_firmware(adev->uvd.fw); 202 adev->uvd.fw = NULL; 203 return r; 204 } 205 206 /* Set the default UVD handles that the firmware can handle */ 207 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 208 209 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 210 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 211 212 if (adev->asic_type < CHIP_VEGA20) { 213 unsigned version_major, version_minor; 214 215 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 216 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 217 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 218 version_major, version_minor, family_id); 219 220 /* 221 * Limit the number of UVD handles depending on microcode major 222 * and minor versions. The firmware version which has 40 UVD 223 * instances support is 1.80. So all subsequent versions should 224 * also have the same support. 225 */ 226 if ((version_major > 0x01) || 227 ((version_major == 0x01) && (version_minor >= 0x50))) 228 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 229 230 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 231 (family_id << 8)); 232 233 if ((adev->asic_type == CHIP_POLARIS10 || 234 adev->asic_type == CHIP_POLARIS11) && 235 (adev->uvd.fw_version < FW_1_66_16)) 236 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", 237 version_major, version_minor); 238 } else { 239 unsigned int enc_major, enc_minor, dec_minor; 240 241 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 242 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 243 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 244 DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n", 245 enc_major, enc_minor, dec_minor, family_id); 246 247 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 248 249 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 250 } 251 252 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 253 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 254 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 255 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 256 257 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 258 if (adev->uvd.harvest_config & (1 << j)) 259 continue; 260 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 261 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo, 262 &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr); 263 if (r) { 264 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 265 return r; 266 } 267 } 268 269 for (i = 0; i < adev->uvd.max_handles; ++i) { 270 atomic_set(&adev->uvd.handles[i], 0); 271 adev->uvd.filp[i] = NULL; 272 } 273 274 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 275 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 276 adev->uvd.address_64_bit = true; 277 278 switch (adev->asic_type) { 279 case CHIP_TONGA: 280 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 281 break; 282 case CHIP_CARRIZO: 283 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 284 break; 285 case CHIP_FIJI: 286 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 287 break; 288 case CHIP_STONEY: 289 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 290 break; 291 default: 292 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 293 } 294 295 return 0; 296 } 297 298 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 299 { 300 int i, j; 301 302 cancel_delayed_work_sync(&adev->uvd.idle_work); 303 drm_sched_entity_destroy(&adev->uvd.entity); 304 305 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 306 if (adev->uvd.harvest_config & (1 << j)) 307 continue; 308 kvfree(adev->uvd.inst[j].saved_bo); 309 310 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 311 &adev->uvd.inst[j].gpu_addr, 312 (void **)&adev->uvd.inst[j].cpu_addr); 313 314 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 315 316 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 317 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 318 } 319 release_firmware(adev->uvd.fw); 320 321 return 0; 322 } 323 324 /** 325 * amdgpu_uvd_entity_init - init entity 326 * 327 * @adev: amdgpu_device pointer 328 * 329 */ 330 int amdgpu_uvd_entity_init(struct amdgpu_device *adev) 331 { 332 struct amdgpu_ring *ring; 333 struct drm_gpu_scheduler *sched; 334 int r; 335 336 ring = &adev->uvd.inst[0].ring; 337 sched = &ring->sched; 338 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 339 &sched, 1, NULL); 340 if (r) { 341 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 342 return r; 343 } 344 345 return 0; 346 } 347 348 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 349 { 350 unsigned size; 351 void *ptr; 352 int i, j; 353 bool in_ras_intr = amdgpu_ras_intr_triggered(); 354 355 cancel_delayed_work_sync(&adev->uvd.idle_work); 356 357 /* only valid for physical mode */ 358 if (adev->asic_type < CHIP_POLARIS10) { 359 for (i = 0; i < adev->uvd.max_handles; ++i) 360 if (atomic_read(&adev->uvd.handles[i])) 361 break; 362 363 if (i == adev->uvd.max_handles) 364 return 0; 365 } 366 367 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 368 if (adev->uvd.harvest_config & (1 << j)) 369 continue; 370 if (adev->uvd.inst[j].vcpu_bo == NULL) 371 continue; 372 373 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 374 ptr = adev->uvd.inst[j].cpu_addr; 375 376 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 377 if (!adev->uvd.inst[j].saved_bo) 378 return -ENOMEM; 379 380 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 381 if (in_ras_intr) 382 memset(adev->uvd.inst[j].saved_bo, 0, size); 383 else 384 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 385 } 386 387 if (in_ras_intr) 388 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 389 390 return 0; 391 } 392 393 int amdgpu_uvd_resume(struct amdgpu_device *adev) 394 { 395 unsigned size; 396 void *ptr; 397 int i; 398 399 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 400 if (adev->uvd.harvest_config & (1 << i)) 401 continue; 402 if (adev->uvd.inst[i].vcpu_bo == NULL) 403 return -EINVAL; 404 405 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 406 ptr = adev->uvd.inst[i].cpu_addr; 407 408 if (adev->uvd.inst[i].saved_bo != NULL) { 409 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 410 kvfree(adev->uvd.inst[i].saved_bo); 411 adev->uvd.inst[i].saved_bo = NULL; 412 } else { 413 const struct common_firmware_header *hdr; 414 unsigned offset; 415 416 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 417 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 418 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 419 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 420 le32_to_cpu(hdr->ucode_size_bytes)); 421 size -= le32_to_cpu(hdr->ucode_size_bytes); 422 ptr += le32_to_cpu(hdr->ucode_size_bytes); 423 } 424 memset_io(ptr, 0, size); 425 /* to restore uvd fence seq */ 426 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); 427 } 428 } 429 return 0; 430 } 431 432 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 433 { 434 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 435 int i, r; 436 437 for (i = 0; i < adev->uvd.max_handles; ++i) { 438 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 439 440 if (handle != 0 && adev->uvd.filp[i] == filp) { 441 struct dma_fence *fence; 442 443 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 444 &fence); 445 if (r) { 446 DRM_ERROR("Error destroying UVD %d!\n", r); 447 continue; 448 } 449 450 dma_fence_wait(fence, false); 451 dma_fence_put(fence); 452 453 adev->uvd.filp[i] = NULL; 454 atomic_set(&adev->uvd.handles[i], 0); 455 } 456 } 457 } 458 459 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 460 { 461 int i; 462 for (i = 0; i < abo->placement.num_placement; ++i) { 463 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 464 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 465 } 466 } 467 468 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 469 { 470 uint32_t lo, hi; 471 uint64_t addr; 472 473 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 474 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 475 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 476 477 return addr; 478 } 479 480 /** 481 * amdgpu_uvd_cs_pass1 - first parsing round 482 * 483 * @ctx: UVD parser context 484 * 485 * Make sure UVD message and feedback buffers are in VRAM and 486 * nobody is violating an 256MB boundary. 487 */ 488 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 489 { 490 struct ttm_operation_ctx tctx = { false, false }; 491 struct amdgpu_bo_va_mapping *mapping; 492 struct amdgpu_bo *bo; 493 uint32_t cmd; 494 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 495 int r = 0; 496 497 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 498 if (r) { 499 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 500 return r; 501 } 502 503 if (!ctx->parser->adev->uvd.address_64_bit) { 504 /* check if it's a message or feedback command */ 505 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 506 if (cmd == 0x0 || cmd == 0x3) { 507 /* yes, force it into VRAM */ 508 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 509 amdgpu_bo_placement_from_domain(bo, domain); 510 } 511 amdgpu_uvd_force_into_uvd_segment(bo); 512 513 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 514 } 515 516 return r; 517 } 518 519 /** 520 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 521 * 522 * @msg: pointer to message structure 523 * @buf_sizes: returned buffer sizes 524 * 525 * Peek into the decode message and calculate the necessary buffer sizes. 526 */ 527 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 528 unsigned buf_sizes[]) 529 { 530 unsigned stream_type = msg[4]; 531 unsigned width = msg[6]; 532 unsigned height = msg[7]; 533 unsigned dpb_size = msg[9]; 534 unsigned pitch = msg[28]; 535 unsigned level = msg[57]; 536 537 unsigned width_in_mb = width / 16; 538 unsigned height_in_mb = ALIGN(height / 16, 2); 539 unsigned fs_in_mb = width_in_mb * height_in_mb; 540 541 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 542 unsigned min_ctx_size = ~0; 543 544 image_size = width * height; 545 image_size += image_size / 2; 546 image_size = ALIGN(image_size, 1024); 547 548 switch (stream_type) { 549 case 0: /* H264 */ 550 switch(level) { 551 case 30: 552 num_dpb_buffer = 8100 / fs_in_mb; 553 break; 554 case 31: 555 num_dpb_buffer = 18000 / fs_in_mb; 556 break; 557 case 32: 558 num_dpb_buffer = 20480 / fs_in_mb; 559 break; 560 case 41: 561 num_dpb_buffer = 32768 / fs_in_mb; 562 break; 563 case 42: 564 num_dpb_buffer = 34816 / fs_in_mb; 565 break; 566 case 50: 567 num_dpb_buffer = 110400 / fs_in_mb; 568 break; 569 case 51: 570 num_dpb_buffer = 184320 / fs_in_mb; 571 break; 572 default: 573 num_dpb_buffer = 184320 / fs_in_mb; 574 break; 575 } 576 num_dpb_buffer++; 577 if (num_dpb_buffer > 17) 578 num_dpb_buffer = 17; 579 580 /* reference picture buffer */ 581 min_dpb_size = image_size * num_dpb_buffer; 582 583 /* macroblock context buffer */ 584 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 585 586 /* IT surface buffer */ 587 min_dpb_size += width_in_mb * height_in_mb * 32; 588 break; 589 590 case 1: /* VC1 */ 591 592 /* reference picture buffer */ 593 min_dpb_size = image_size * 3; 594 595 /* CONTEXT_BUFFER */ 596 min_dpb_size += width_in_mb * height_in_mb * 128; 597 598 /* IT surface buffer */ 599 min_dpb_size += width_in_mb * 64; 600 601 /* DB surface buffer */ 602 min_dpb_size += width_in_mb * 128; 603 604 /* BP */ 605 tmp = max(width_in_mb, height_in_mb); 606 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 607 break; 608 609 case 3: /* MPEG2 */ 610 611 /* reference picture buffer */ 612 min_dpb_size = image_size * 3; 613 break; 614 615 case 4: /* MPEG4 */ 616 617 /* reference picture buffer */ 618 min_dpb_size = image_size * 3; 619 620 /* CM */ 621 min_dpb_size += width_in_mb * height_in_mb * 64; 622 623 /* IT surface buffer */ 624 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 625 break; 626 627 case 7: /* H264 Perf */ 628 switch(level) { 629 case 30: 630 num_dpb_buffer = 8100 / fs_in_mb; 631 break; 632 case 31: 633 num_dpb_buffer = 18000 / fs_in_mb; 634 break; 635 case 32: 636 num_dpb_buffer = 20480 / fs_in_mb; 637 break; 638 case 41: 639 num_dpb_buffer = 32768 / fs_in_mb; 640 break; 641 case 42: 642 num_dpb_buffer = 34816 / fs_in_mb; 643 break; 644 case 50: 645 num_dpb_buffer = 110400 / fs_in_mb; 646 break; 647 case 51: 648 num_dpb_buffer = 184320 / fs_in_mb; 649 break; 650 default: 651 num_dpb_buffer = 184320 / fs_in_mb; 652 break; 653 } 654 num_dpb_buffer++; 655 if (num_dpb_buffer > 17) 656 num_dpb_buffer = 17; 657 658 /* reference picture buffer */ 659 min_dpb_size = image_size * num_dpb_buffer; 660 661 if (!adev->uvd.use_ctx_buf){ 662 /* macroblock context buffer */ 663 min_dpb_size += 664 width_in_mb * height_in_mb * num_dpb_buffer * 192; 665 666 /* IT surface buffer */ 667 min_dpb_size += width_in_mb * height_in_mb * 32; 668 } else { 669 /* macroblock context buffer */ 670 min_ctx_size = 671 width_in_mb * height_in_mb * num_dpb_buffer * 192; 672 } 673 break; 674 675 case 8: /* MJPEG */ 676 min_dpb_size = 0; 677 break; 678 679 case 16: /* H265 */ 680 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 681 image_size = ALIGN(image_size, 256); 682 683 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 684 min_dpb_size = image_size * num_dpb_buffer; 685 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 686 * 16 * num_dpb_buffer + 52 * 1024; 687 break; 688 689 default: 690 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 691 return -EINVAL; 692 } 693 694 if (width > pitch) { 695 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 696 return -EINVAL; 697 } 698 699 if (dpb_size < min_dpb_size) { 700 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 701 dpb_size, min_dpb_size); 702 return -EINVAL; 703 } 704 705 buf_sizes[0x1] = dpb_size; 706 buf_sizes[0x2] = image_size; 707 buf_sizes[0x4] = min_ctx_size; 708 /* store image width to adjust nb memory pstate */ 709 adev->uvd.decode_image_width = width; 710 return 0; 711 } 712 713 /** 714 * amdgpu_uvd_cs_msg - handle UVD message 715 * 716 * @ctx: UVD parser context 717 * @bo: buffer object containing the message 718 * @offset: offset into the buffer object 719 * 720 * Peek into the UVD message and extract the session id. 721 * Make sure that we don't open up to many sessions. 722 */ 723 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 724 struct amdgpu_bo *bo, unsigned offset) 725 { 726 struct amdgpu_device *adev = ctx->parser->adev; 727 int32_t *msg, msg_type, handle; 728 void *ptr; 729 long r; 730 int i; 731 732 if (offset & 0x3F) { 733 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 734 return -EINVAL; 735 } 736 737 r = amdgpu_bo_kmap(bo, &ptr); 738 if (r) { 739 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 740 return r; 741 } 742 743 msg = ptr + offset; 744 745 msg_type = msg[1]; 746 handle = msg[2]; 747 748 if (handle == 0) { 749 DRM_ERROR("Invalid UVD handle!\n"); 750 return -EINVAL; 751 } 752 753 switch (msg_type) { 754 case 0: 755 /* it's a create msg, calc image size (width * height) */ 756 amdgpu_bo_kunmap(bo); 757 758 /* try to alloc a new handle */ 759 for (i = 0; i < adev->uvd.max_handles; ++i) { 760 if (atomic_read(&adev->uvd.handles[i]) == handle) { 761 DRM_ERROR(")Handle 0x%x already in use!\n", 762 handle); 763 return -EINVAL; 764 } 765 766 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 767 adev->uvd.filp[i] = ctx->parser->filp; 768 return 0; 769 } 770 } 771 772 DRM_ERROR("No more free UVD handles!\n"); 773 return -ENOSPC; 774 775 case 1: 776 /* it's a decode msg, calc buffer sizes */ 777 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 778 amdgpu_bo_kunmap(bo); 779 if (r) 780 return r; 781 782 /* validate the handle */ 783 for (i = 0; i < adev->uvd.max_handles; ++i) { 784 if (atomic_read(&adev->uvd.handles[i]) == handle) { 785 if (adev->uvd.filp[i] != ctx->parser->filp) { 786 DRM_ERROR("UVD handle collision detected!\n"); 787 return -EINVAL; 788 } 789 return 0; 790 } 791 } 792 793 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 794 return -ENOENT; 795 796 case 2: 797 /* it's a destroy msg, free the handle */ 798 for (i = 0; i < adev->uvd.max_handles; ++i) 799 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 800 amdgpu_bo_kunmap(bo); 801 return 0; 802 803 default: 804 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 805 return -EINVAL; 806 } 807 BUG(); 808 return -EINVAL; 809 } 810 811 /** 812 * amdgpu_uvd_cs_pass2 - second parsing round 813 * 814 * @ctx: UVD parser context 815 * 816 * Patch buffer addresses, make sure buffer sizes are correct. 817 */ 818 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 819 { 820 struct amdgpu_bo_va_mapping *mapping; 821 struct amdgpu_bo *bo; 822 uint32_t cmd; 823 uint64_t start, end; 824 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 825 int r; 826 827 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 828 if (r) { 829 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 830 return r; 831 } 832 833 start = amdgpu_bo_gpu_offset(bo); 834 835 end = (mapping->last + 1 - mapping->start); 836 end = end * AMDGPU_GPU_PAGE_SIZE + start; 837 838 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 839 start += addr; 840 841 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 842 lower_32_bits(start)); 843 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 844 upper_32_bits(start)); 845 846 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 847 if (cmd < 0x4) { 848 if ((end - start) < ctx->buf_sizes[cmd]) { 849 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 850 (unsigned)(end - start), 851 ctx->buf_sizes[cmd]); 852 return -EINVAL; 853 } 854 855 } else if (cmd == 0x206) { 856 if ((end - start) < ctx->buf_sizes[4]) { 857 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 858 (unsigned)(end - start), 859 ctx->buf_sizes[4]); 860 return -EINVAL; 861 } 862 } else if ((cmd != 0x100) && (cmd != 0x204)) { 863 DRM_ERROR("invalid UVD command %X!\n", cmd); 864 return -EINVAL; 865 } 866 867 if (!ctx->parser->adev->uvd.address_64_bit) { 868 if ((start >> 28) != ((end - 1) >> 28)) { 869 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 870 start, end); 871 return -EINVAL; 872 } 873 874 if ((cmd == 0 || cmd == 0x3) && 875 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 876 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 877 start, end); 878 return -EINVAL; 879 } 880 } 881 882 if (cmd == 0) { 883 ctx->has_msg_cmd = true; 884 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 885 if (r) 886 return r; 887 } else if (!ctx->has_msg_cmd) { 888 DRM_ERROR("Message needed before other commands are send!\n"); 889 return -EINVAL; 890 } 891 892 return 0; 893 } 894 895 /** 896 * amdgpu_uvd_cs_reg - parse register writes 897 * 898 * @ctx: UVD parser context 899 * @cb: callback function 900 * 901 * Parse the register writes, call cb on each complete command. 902 */ 903 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 904 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 905 { 906 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 907 int i, r; 908 909 ctx->idx++; 910 for (i = 0; i <= ctx->count; ++i) { 911 unsigned reg = ctx->reg + i; 912 913 if (ctx->idx >= ib->length_dw) { 914 DRM_ERROR("Register command after end of CS!\n"); 915 return -EINVAL; 916 } 917 918 switch (reg) { 919 case mmUVD_GPCOM_VCPU_DATA0: 920 ctx->data0 = ctx->idx; 921 break; 922 case mmUVD_GPCOM_VCPU_DATA1: 923 ctx->data1 = ctx->idx; 924 break; 925 case mmUVD_GPCOM_VCPU_CMD: 926 r = cb(ctx); 927 if (r) 928 return r; 929 break; 930 case mmUVD_ENGINE_CNTL: 931 case mmUVD_NO_OP: 932 break; 933 default: 934 DRM_ERROR("Invalid reg 0x%X!\n", reg); 935 return -EINVAL; 936 } 937 ctx->idx++; 938 } 939 return 0; 940 } 941 942 /** 943 * amdgpu_uvd_cs_packets - parse UVD packets 944 * 945 * @ctx: UVD parser context 946 * @cb: callback function 947 * 948 * Parse the command stream packets. 949 */ 950 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 951 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 952 { 953 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 954 int r; 955 956 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 957 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 958 unsigned type = CP_PACKET_GET_TYPE(cmd); 959 switch (type) { 960 case PACKET_TYPE0: 961 ctx->reg = CP_PACKET0_GET_REG(cmd); 962 ctx->count = CP_PACKET_GET_COUNT(cmd); 963 r = amdgpu_uvd_cs_reg(ctx, cb); 964 if (r) 965 return r; 966 break; 967 case PACKET_TYPE2: 968 ++ctx->idx; 969 break; 970 default: 971 DRM_ERROR("Unknown packet type %d !\n", type); 972 return -EINVAL; 973 } 974 } 975 return 0; 976 } 977 978 /** 979 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 980 * 981 * @parser: Command submission parser context 982 * 983 * Parse the command stream, patch in addresses as necessary. 984 */ 985 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 986 { 987 struct amdgpu_uvd_cs_ctx ctx = {}; 988 unsigned buf_sizes[] = { 989 [0x00000000] = 2048, 990 [0x00000001] = 0xFFFFFFFF, 991 [0x00000002] = 0xFFFFFFFF, 992 [0x00000003] = 2048, 993 [0x00000004] = 0xFFFFFFFF, 994 }; 995 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 996 int r; 997 998 parser->job->vm = NULL; 999 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 1000 1001 if (ib->length_dw % 16) { 1002 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1003 ib->length_dw); 1004 return -EINVAL; 1005 } 1006 1007 ctx.parser = parser; 1008 ctx.buf_sizes = buf_sizes; 1009 ctx.ib_idx = ib_idx; 1010 1011 /* first round only required on chips without UVD 64 bit address support */ 1012 if (!parser->adev->uvd.address_64_bit) { 1013 /* first round, make sure the buffers are actually in the UVD segment */ 1014 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1015 if (r) 1016 return r; 1017 } 1018 1019 /* second round, patch buffer addresses into the command stream */ 1020 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1021 if (r) 1022 return r; 1023 1024 if (!ctx.has_msg_cmd) { 1025 DRM_ERROR("UVD-IBs need a msg command!\n"); 1026 return -EINVAL; 1027 } 1028 1029 return 0; 1030 } 1031 1032 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1033 bool direct, struct dma_fence **fence) 1034 { 1035 struct amdgpu_device *adev = ring->adev; 1036 struct dma_fence *f = NULL; 1037 struct amdgpu_job *job; 1038 struct amdgpu_ib *ib; 1039 uint32_t data[4]; 1040 uint64_t addr; 1041 long r; 1042 int i; 1043 unsigned offset_idx = 0; 1044 unsigned offset[3] = { UVD_BASE_SI, 0, 0 }; 1045 1046 amdgpu_bo_kunmap(bo); 1047 amdgpu_bo_unpin(bo); 1048 1049 if (!ring->adev->uvd.address_64_bit) { 1050 struct ttm_operation_ctx ctx = { true, false }; 1051 1052 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 1053 amdgpu_uvd_force_into_uvd_segment(bo); 1054 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1055 if (r) 1056 goto err; 1057 } 1058 1059 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 1060 if (r) 1061 goto err; 1062 1063 if (adev->asic_type >= CHIP_VEGA10) { 1064 offset_idx = 1 + ring->me; 1065 offset[1] = adev->reg_offset[UVD_HWIP][0][1]; 1066 offset[2] = adev->reg_offset[UVD_HWIP][1][1]; 1067 } 1068 1069 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0); 1070 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0); 1071 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0); 1072 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); 1073 1074 ib = &job->ibs[0]; 1075 addr = amdgpu_bo_gpu_offset(bo); 1076 ib->ptr[0] = data[0]; 1077 ib->ptr[1] = addr; 1078 ib->ptr[2] = data[1]; 1079 ib->ptr[3] = addr >> 32; 1080 ib->ptr[4] = data[2]; 1081 ib->ptr[5] = 0; 1082 for (i = 6; i < 16; i += 2) { 1083 ib->ptr[i] = data[3]; 1084 ib->ptr[i+1] = 0; 1085 } 1086 ib->length_dw = 16; 1087 1088 if (direct) { 1089 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, 1090 true, false, 1091 msecs_to_jiffies(10)); 1092 if (r == 0) 1093 r = -ETIMEDOUT; 1094 if (r < 0) 1095 goto err_free; 1096 1097 r = amdgpu_job_submit_direct(job, ring, &f); 1098 if (r) 1099 goto err_free; 1100 } else { 1101 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv, 1102 AMDGPU_SYNC_ALWAYS, 1103 AMDGPU_FENCE_OWNER_UNDEFINED); 1104 if (r) 1105 goto err_free; 1106 1107 r = amdgpu_job_submit(job, &adev->uvd.entity, 1108 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1109 if (r) 1110 goto err_free; 1111 } 1112 1113 amdgpu_bo_fence(bo, f, false); 1114 amdgpu_bo_unreserve(bo); 1115 amdgpu_bo_unref(&bo); 1116 1117 if (fence) 1118 *fence = dma_fence_get(f); 1119 dma_fence_put(f); 1120 1121 return 0; 1122 1123 err_free: 1124 amdgpu_job_free(job); 1125 1126 err: 1127 amdgpu_bo_unreserve(bo); 1128 amdgpu_bo_unref(&bo); 1129 return r; 1130 } 1131 1132 /* multiple fence commands without any stream commands in between can 1133 crash the vcpu so just try to emmit a dummy create/destroy msg to 1134 avoid this */ 1135 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1136 struct dma_fence **fence) 1137 { 1138 struct amdgpu_device *adev = ring->adev; 1139 struct amdgpu_bo *bo = NULL; 1140 uint32_t *msg; 1141 int r, i; 1142 1143 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1144 AMDGPU_GEM_DOMAIN_VRAM, 1145 &bo, NULL, (void **)&msg); 1146 if (r) 1147 return r; 1148 1149 /* stitch together an UVD create msg */ 1150 msg[0] = cpu_to_le32(0x00000de4); 1151 msg[1] = cpu_to_le32(0x00000000); 1152 msg[2] = cpu_to_le32(handle); 1153 msg[3] = cpu_to_le32(0x00000000); 1154 msg[4] = cpu_to_le32(0x00000000); 1155 msg[5] = cpu_to_le32(0x00000000); 1156 msg[6] = cpu_to_le32(0x00000000); 1157 msg[7] = cpu_to_le32(0x00000780); 1158 msg[8] = cpu_to_le32(0x00000440); 1159 msg[9] = cpu_to_le32(0x00000000); 1160 msg[10] = cpu_to_le32(0x01b37000); 1161 for (i = 11; i < 1024; ++i) 1162 msg[i] = cpu_to_le32(0x0); 1163 1164 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1165 } 1166 1167 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1168 bool direct, struct dma_fence **fence) 1169 { 1170 struct amdgpu_device *adev = ring->adev; 1171 struct amdgpu_bo *bo = NULL; 1172 uint32_t *msg; 1173 int r, i; 1174 1175 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1176 AMDGPU_GEM_DOMAIN_VRAM, 1177 &bo, NULL, (void **)&msg); 1178 if (r) 1179 return r; 1180 1181 /* stitch together an UVD destroy msg */ 1182 msg[0] = cpu_to_le32(0x00000de4); 1183 msg[1] = cpu_to_le32(0x00000002); 1184 msg[2] = cpu_to_le32(handle); 1185 msg[3] = cpu_to_le32(0x00000000); 1186 for (i = 4; i < 1024; ++i) 1187 msg[i] = cpu_to_le32(0x0); 1188 1189 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1190 } 1191 1192 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1193 { 1194 struct amdgpu_device *adev = 1195 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1196 unsigned fences = 0, i, j; 1197 1198 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1199 if (adev->uvd.harvest_config & (1 << i)) 1200 continue; 1201 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1202 for (j = 0; j < adev->uvd.num_enc_rings; ++j) { 1203 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1204 } 1205 } 1206 1207 if (fences == 0) { 1208 if (adev->pm.dpm_enabled) { 1209 amdgpu_dpm_enable_uvd(adev, false); 1210 } else { 1211 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1212 /* shutdown the UVD block */ 1213 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1214 AMD_PG_STATE_GATE); 1215 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1216 AMD_CG_STATE_GATE); 1217 } 1218 } else { 1219 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1220 } 1221 } 1222 1223 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1224 { 1225 struct amdgpu_device *adev = ring->adev; 1226 bool set_clocks; 1227 1228 if (amdgpu_sriov_vf(adev)) 1229 return; 1230 1231 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1232 if (set_clocks) { 1233 if (adev->pm.dpm_enabled) { 1234 amdgpu_dpm_enable_uvd(adev, true); 1235 } else { 1236 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1237 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1238 AMD_CG_STATE_UNGATE); 1239 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1240 AMD_PG_STATE_UNGATE); 1241 } 1242 } 1243 } 1244 1245 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1246 { 1247 if (!amdgpu_sriov_vf(ring->adev)) 1248 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1249 } 1250 1251 /** 1252 * amdgpu_uvd_ring_test_ib - test ib execution 1253 * 1254 * @ring: amdgpu_ring pointer 1255 * 1256 * Test if we can successfully execute an IB 1257 */ 1258 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1259 { 1260 struct dma_fence *fence; 1261 long r; 1262 1263 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1264 if (r) 1265 goto error; 1266 1267 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1268 if (r) 1269 goto error; 1270 1271 r = dma_fence_wait_timeout(fence, false, timeout); 1272 if (r == 0) 1273 r = -ETIMEDOUT; 1274 else if (r > 0) 1275 r = 0; 1276 1277 dma_fence_put(fence); 1278 1279 error: 1280 return r; 1281 } 1282 1283 /** 1284 * amdgpu_uvd_used_handles - returns used UVD handles 1285 * 1286 * @adev: amdgpu_device pointer 1287 * 1288 * Returns the number of UVD handles in use 1289 */ 1290 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1291 { 1292 unsigned i; 1293 uint32_t used_handles = 0; 1294 1295 for (i = 0; i < adev->uvd.max_handles; ++i) { 1296 /* 1297 * Handles can be freed in any order, and not 1298 * necessarily linear. So we need to count 1299 * all non-zero handles. 1300 */ 1301 if (atomic_read(&adev->uvd.handles[i])) 1302 used_handles++; 1303 } 1304 1305 return used_handles; 1306 } 1307