1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 /* 1 second timeout */ 43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 44 45 /* Firmware versions for VI */ 46 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 47 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 48 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 49 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 50 51 /* Polaris10/11 firmware version */ 52 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 53 54 /* Firmware Names */ 55 #ifdef CONFIG_DRM_AMDGPU_CIK 56 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 57 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" 58 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" 59 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" 60 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" 61 #endif 62 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 63 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 64 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 65 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 66 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 67 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 68 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 69 70 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 71 72 #define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00) 73 #define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00) 74 #define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00) 75 #define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00) 76 #define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00) 77 78 /** 79 * amdgpu_uvd_cs_ctx - Command submission parser context 80 * 81 * Used for emulating virtual memory support on UVD 4.2. 82 */ 83 struct amdgpu_uvd_cs_ctx { 84 struct amdgpu_cs_parser *parser; 85 unsigned reg, count; 86 unsigned data0, data1; 87 unsigned idx; 88 unsigned ib_idx; 89 90 /* does the IB has a msg command */ 91 bool has_msg_cmd; 92 93 /* minimum buffer sizes */ 94 unsigned *buf_sizes; 95 }; 96 97 #ifdef CONFIG_DRM_AMDGPU_CIK 98 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 99 MODULE_FIRMWARE(FIRMWARE_KABINI); 100 MODULE_FIRMWARE(FIRMWARE_KAVERI); 101 MODULE_FIRMWARE(FIRMWARE_HAWAII); 102 MODULE_FIRMWARE(FIRMWARE_MULLINS); 103 #endif 104 MODULE_FIRMWARE(FIRMWARE_TONGA); 105 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 106 MODULE_FIRMWARE(FIRMWARE_FIJI); 107 MODULE_FIRMWARE(FIRMWARE_STONEY); 108 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 109 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 110 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 111 112 MODULE_FIRMWARE(FIRMWARE_VEGA10); 113 114 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 115 116 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 117 { 118 struct amdgpu_ring *ring; 119 struct amd_sched_rq *rq; 120 unsigned long bo_size; 121 const char *fw_name; 122 const struct common_firmware_header *hdr; 123 unsigned version_major, version_minor, family_id; 124 int i, r; 125 126 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 127 128 switch (adev->asic_type) { 129 #ifdef CONFIG_DRM_AMDGPU_CIK 130 case CHIP_BONAIRE: 131 fw_name = FIRMWARE_BONAIRE; 132 break; 133 case CHIP_KABINI: 134 fw_name = FIRMWARE_KABINI; 135 break; 136 case CHIP_KAVERI: 137 fw_name = FIRMWARE_KAVERI; 138 break; 139 case CHIP_HAWAII: 140 fw_name = FIRMWARE_HAWAII; 141 break; 142 case CHIP_MULLINS: 143 fw_name = FIRMWARE_MULLINS; 144 break; 145 #endif 146 case CHIP_TONGA: 147 fw_name = FIRMWARE_TONGA; 148 break; 149 case CHIP_FIJI: 150 fw_name = FIRMWARE_FIJI; 151 break; 152 case CHIP_CARRIZO: 153 fw_name = FIRMWARE_CARRIZO; 154 break; 155 case CHIP_STONEY: 156 fw_name = FIRMWARE_STONEY; 157 break; 158 case CHIP_POLARIS10: 159 fw_name = FIRMWARE_POLARIS10; 160 break; 161 case CHIP_POLARIS11: 162 fw_name = FIRMWARE_POLARIS11; 163 break; 164 case CHIP_VEGA10: 165 fw_name = FIRMWARE_VEGA10; 166 break; 167 case CHIP_POLARIS12: 168 fw_name = FIRMWARE_POLARIS12; 169 break; 170 default: 171 return -EINVAL; 172 } 173 174 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 175 if (r) { 176 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 177 fw_name); 178 return r; 179 } 180 181 r = amdgpu_ucode_validate(adev->uvd.fw); 182 if (r) { 183 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 184 fw_name); 185 release_firmware(adev->uvd.fw); 186 adev->uvd.fw = NULL; 187 return r; 188 } 189 190 /* Set the default UVD handles that the firmware can handle */ 191 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 192 193 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 194 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 195 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 196 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 197 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 198 version_major, version_minor, family_id); 199 200 /* 201 * Limit the number of UVD handles depending on microcode major 202 * and minor versions. The firmware version which has 40 UVD 203 * instances support is 1.80. So all subsequent versions should 204 * also have the same support. 205 */ 206 if ((version_major > 0x01) || 207 ((version_major == 0x01) && (version_minor >= 0x50))) 208 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 209 210 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 211 (family_id << 8)); 212 213 if ((adev->asic_type == CHIP_POLARIS10 || 214 adev->asic_type == CHIP_POLARIS11) && 215 (adev->uvd.fw_version < FW_1_66_16)) 216 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", 217 version_major, version_minor); 218 219 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 220 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 221 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 222 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 223 224 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 225 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo, 226 &adev->uvd.gpu_addr, &adev->uvd.cpu_addr); 227 if (r) { 228 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 229 return r; 230 } 231 232 ring = &adev->uvd.ring; 233 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; 234 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, 235 rq, amdgpu_sched_jobs); 236 if (r != 0) { 237 DRM_ERROR("Failed setting up UVD run queue.\n"); 238 return r; 239 } 240 241 for (i = 0; i < adev->uvd.max_handles; ++i) { 242 atomic_set(&adev->uvd.handles[i], 0); 243 adev->uvd.filp[i] = NULL; 244 } 245 246 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 247 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 248 adev->uvd.address_64_bit = true; 249 250 switch (adev->asic_type) { 251 case CHIP_TONGA: 252 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 253 break; 254 case CHIP_CARRIZO: 255 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 256 break; 257 case CHIP_FIJI: 258 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 259 break; 260 case CHIP_STONEY: 261 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 262 break; 263 default: 264 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 265 } 266 267 return 0; 268 } 269 270 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 271 { 272 kfree(adev->uvd.saved_bo); 273 274 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); 275 276 amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo, 277 &adev->uvd.gpu_addr, 278 (void **)&adev->uvd.cpu_addr); 279 280 amdgpu_ring_fini(&adev->uvd.ring); 281 282 release_firmware(adev->uvd.fw); 283 284 return 0; 285 } 286 287 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 288 { 289 unsigned size; 290 void *ptr; 291 int i; 292 293 if (adev->uvd.vcpu_bo == NULL) 294 return 0; 295 296 for (i = 0; i < adev->uvd.max_handles; ++i) 297 if (atomic_read(&adev->uvd.handles[i])) 298 break; 299 300 if (i == AMDGPU_MAX_UVD_HANDLES) 301 return 0; 302 303 cancel_delayed_work_sync(&adev->uvd.idle_work); 304 305 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 306 ptr = adev->uvd.cpu_addr; 307 308 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 309 if (!adev->uvd.saved_bo) 310 return -ENOMEM; 311 312 memcpy_fromio(adev->uvd.saved_bo, ptr, size); 313 314 return 0; 315 } 316 317 int amdgpu_uvd_resume(struct amdgpu_device *adev) 318 { 319 unsigned size; 320 void *ptr; 321 322 if (adev->uvd.vcpu_bo == NULL) 323 return -EINVAL; 324 325 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 326 ptr = adev->uvd.cpu_addr; 327 328 if (adev->uvd.saved_bo != NULL) { 329 memcpy_toio(ptr, adev->uvd.saved_bo, size); 330 kfree(adev->uvd.saved_bo); 331 adev->uvd.saved_bo = NULL; 332 } else { 333 const struct common_firmware_header *hdr; 334 unsigned offset; 335 336 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 337 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 338 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 339 memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset, 340 le32_to_cpu(hdr->ucode_size_bytes)); 341 size -= le32_to_cpu(hdr->ucode_size_bytes); 342 ptr += le32_to_cpu(hdr->ucode_size_bytes); 343 } 344 memset_io(ptr, 0, size); 345 } 346 347 return 0; 348 } 349 350 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 351 { 352 struct amdgpu_ring *ring = &adev->uvd.ring; 353 int i, r; 354 355 for (i = 0; i < adev->uvd.max_handles; ++i) { 356 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 357 if (handle != 0 && adev->uvd.filp[i] == filp) { 358 struct dma_fence *fence; 359 360 r = amdgpu_uvd_get_destroy_msg(ring, handle, 361 false, &fence); 362 if (r) { 363 DRM_ERROR("Error destroying UVD (%d)!\n", r); 364 continue; 365 } 366 367 dma_fence_wait(fence, false); 368 dma_fence_put(fence); 369 370 adev->uvd.filp[i] = NULL; 371 atomic_set(&adev->uvd.handles[i], 0); 372 } 373 } 374 } 375 376 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 377 { 378 int i; 379 for (i = 0; i < abo->placement.num_placement; ++i) { 380 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 381 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 382 } 383 } 384 385 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 386 { 387 uint32_t lo, hi; 388 uint64_t addr; 389 390 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 391 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 392 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 393 394 return addr; 395 } 396 397 /** 398 * amdgpu_uvd_cs_pass1 - first parsing round 399 * 400 * @ctx: UVD parser context 401 * 402 * Make sure UVD message and feedback buffers are in VRAM and 403 * nobody is violating an 256MB boundary. 404 */ 405 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 406 { 407 struct amdgpu_bo_va_mapping *mapping; 408 struct amdgpu_bo *bo; 409 uint32_t cmd; 410 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 411 int r = 0; 412 413 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 414 if (mapping == NULL) { 415 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 416 return -EINVAL; 417 } 418 419 if (!ctx->parser->adev->uvd.address_64_bit) { 420 /* check if it's a message or feedback command */ 421 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 422 if (cmd == 0x0 || cmd == 0x3) { 423 /* yes, force it into VRAM */ 424 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 425 amdgpu_ttm_placement_from_domain(bo, domain); 426 } 427 amdgpu_uvd_force_into_uvd_segment(bo); 428 429 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 430 } 431 432 return r; 433 } 434 435 /** 436 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 437 * 438 * @msg: pointer to message structure 439 * @buf_sizes: returned buffer sizes 440 * 441 * Peek into the decode message and calculate the necessary buffer sizes. 442 */ 443 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 444 unsigned buf_sizes[]) 445 { 446 unsigned stream_type = msg[4]; 447 unsigned width = msg[6]; 448 unsigned height = msg[7]; 449 unsigned dpb_size = msg[9]; 450 unsigned pitch = msg[28]; 451 unsigned level = msg[57]; 452 453 unsigned width_in_mb = width / 16; 454 unsigned height_in_mb = ALIGN(height / 16, 2); 455 unsigned fs_in_mb = width_in_mb * height_in_mb; 456 457 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 458 unsigned min_ctx_size = ~0; 459 460 image_size = width * height; 461 image_size += image_size / 2; 462 image_size = ALIGN(image_size, 1024); 463 464 switch (stream_type) { 465 case 0: /* H264 */ 466 switch(level) { 467 case 30: 468 num_dpb_buffer = 8100 / fs_in_mb; 469 break; 470 case 31: 471 num_dpb_buffer = 18000 / fs_in_mb; 472 break; 473 case 32: 474 num_dpb_buffer = 20480 / fs_in_mb; 475 break; 476 case 41: 477 num_dpb_buffer = 32768 / fs_in_mb; 478 break; 479 case 42: 480 num_dpb_buffer = 34816 / fs_in_mb; 481 break; 482 case 50: 483 num_dpb_buffer = 110400 / fs_in_mb; 484 break; 485 case 51: 486 num_dpb_buffer = 184320 / fs_in_mb; 487 break; 488 default: 489 num_dpb_buffer = 184320 / fs_in_mb; 490 break; 491 } 492 num_dpb_buffer++; 493 if (num_dpb_buffer > 17) 494 num_dpb_buffer = 17; 495 496 /* reference picture buffer */ 497 min_dpb_size = image_size * num_dpb_buffer; 498 499 /* macroblock context buffer */ 500 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 501 502 /* IT surface buffer */ 503 min_dpb_size += width_in_mb * height_in_mb * 32; 504 break; 505 506 case 1: /* VC1 */ 507 508 /* reference picture buffer */ 509 min_dpb_size = image_size * 3; 510 511 /* CONTEXT_BUFFER */ 512 min_dpb_size += width_in_mb * height_in_mb * 128; 513 514 /* IT surface buffer */ 515 min_dpb_size += width_in_mb * 64; 516 517 /* DB surface buffer */ 518 min_dpb_size += width_in_mb * 128; 519 520 /* BP */ 521 tmp = max(width_in_mb, height_in_mb); 522 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 523 break; 524 525 case 3: /* MPEG2 */ 526 527 /* reference picture buffer */ 528 min_dpb_size = image_size * 3; 529 break; 530 531 case 4: /* MPEG4 */ 532 533 /* reference picture buffer */ 534 min_dpb_size = image_size * 3; 535 536 /* CM */ 537 min_dpb_size += width_in_mb * height_in_mb * 64; 538 539 /* IT surface buffer */ 540 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 541 break; 542 543 case 7: /* H264 Perf */ 544 switch(level) { 545 case 30: 546 num_dpb_buffer = 8100 / fs_in_mb; 547 break; 548 case 31: 549 num_dpb_buffer = 18000 / fs_in_mb; 550 break; 551 case 32: 552 num_dpb_buffer = 20480 / fs_in_mb; 553 break; 554 case 41: 555 num_dpb_buffer = 32768 / fs_in_mb; 556 break; 557 case 42: 558 num_dpb_buffer = 34816 / fs_in_mb; 559 break; 560 case 50: 561 num_dpb_buffer = 110400 / fs_in_mb; 562 break; 563 case 51: 564 num_dpb_buffer = 184320 / fs_in_mb; 565 break; 566 default: 567 num_dpb_buffer = 184320 / fs_in_mb; 568 break; 569 } 570 num_dpb_buffer++; 571 if (num_dpb_buffer > 17) 572 num_dpb_buffer = 17; 573 574 /* reference picture buffer */ 575 min_dpb_size = image_size * num_dpb_buffer; 576 577 if (!adev->uvd.use_ctx_buf){ 578 /* macroblock context buffer */ 579 min_dpb_size += 580 width_in_mb * height_in_mb * num_dpb_buffer * 192; 581 582 /* IT surface buffer */ 583 min_dpb_size += width_in_mb * height_in_mb * 32; 584 } else { 585 /* macroblock context buffer */ 586 min_ctx_size = 587 width_in_mb * height_in_mb * num_dpb_buffer * 192; 588 } 589 break; 590 591 case 8: /* MJPEG */ 592 min_dpb_size = 0; 593 break; 594 595 case 16: /* H265 */ 596 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 597 image_size = ALIGN(image_size, 256); 598 599 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 600 min_dpb_size = image_size * num_dpb_buffer; 601 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 602 * 16 * num_dpb_buffer + 52 * 1024; 603 break; 604 605 default: 606 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 607 return -EINVAL; 608 } 609 610 if (width > pitch) { 611 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 612 return -EINVAL; 613 } 614 615 if (dpb_size < min_dpb_size) { 616 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 617 dpb_size, min_dpb_size); 618 return -EINVAL; 619 } 620 621 buf_sizes[0x1] = dpb_size; 622 buf_sizes[0x2] = image_size; 623 buf_sizes[0x4] = min_ctx_size; 624 return 0; 625 } 626 627 /** 628 * amdgpu_uvd_cs_msg - handle UVD message 629 * 630 * @ctx: UVD parser context 631 * @bo: buffer object containing the message 632 * @offset: offset into the buffer object 633 * 634 * Peek into the UVD message and extract the session id. 635 * Make sure that we don't open up to many sessions. 636 */ 637 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 638 struct amdgpu_bo *bo, unsigned offset) 639 { 640 struct amdgpu_device *adev = ctx->parser->adev; 641 int32_t *msg, msg_type, handle; 642 void *ptr; 643 long r; 644 int i; 645 646 if (offset & 0x3F) { 647 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 648 return -EINVAL; 649 } 650 651 r = amdgpu_bo_kmap(bo, &ptr); 652 if (r) { 653 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); 654 return r; 655 } 656 657 msg = ptr + offset; 658 659 msg_type = msg[1]; 660 handle = msg[2]; 661 662 if (handle == 0) { 663 DRM_ERROR("Invalid UVD handle!\n"); 664 return -EINVAL; 665 } 666 667 switch (msg_type) { 668 case 0: 669 /* it's a create msg, calc image size (width * height) */ 670 amdgpu_bo_kunmap(bo); 671 672 /* try to alloc a new handle */ 673 for (i = 0; i < adev->uvd.max_handles; ++i) { 674 if (atomic_read(&adev->uvd.handles[i]) == handle) { 675 DRM_ERROR("Handle 0x%x already in use!\n", handle); 676 return -EINVAL; 677 } 678 679 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 680 adev->uvd.filp[i] = ctx->parser->filp; 681 return 0; 682 } 683 } 684 685 DRM_ERROR("No more free UVD handles!\n"); 686 return -ENOSPC; 687 688 case 1: 689 /* it's a decode msg, calc buffer sizes */ 690 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 691 amdgpu_bo_kunmap(bo); 692 if (r) 693 return r; 694 695 /* validate the handle */ 696 for (i = 0; i < adev->uvd.max_handles; ++i) { 697 if (atomic_read(&adev->uvd.handles[i]) == handle) { 698 if (adev->uvd.filp[i] != ctx->parser->filp) { 699 DRM_ERROR("UVD handle collision detected!\n"); 700 return -EINVAL; 701 } 702 return 0; 703 } 704 } 705 706 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 707 return -ENOENT; 708 709 case 2: 710 /* it's a destroy msg, free the handle */ 711 for (i = 0; i < adev->uvd.max_handles; ++i) 712 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 713 amdgpu_bo_kunmap(bo); 714 return 0; 715 716 default: 717 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 718 return -EINVAL; 719 } 720 BUG(); 721 return -EINVAL; 722 } 723 724 /** 725 * amdgpu_uvd_cs_pass2 - second parsing round 726 * 727 * @ctx: UVD parser context 728 * 729 * Patch buffer addresses, make sure buffer sizes are correct. 730 */ 731 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 732 { 733 struct amdgpu_bo_va_mapping *mapping; 734 struct amdgpu_bo *bo; 735 uint32_t cmd; 736 uint64_t start, end; 737 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 738 int r; 739 740 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 741 if (mapping == NULL) { 742 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 743 return -EINVAL; 744 } 745 746 start = amdgpu_bo_gpu_offset(bo); 747 748 end = (mapping->last + 1 - mapping->start); 749 end = end * AMDGPU_GPU_PAGE_SIZE + start; 750 751 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 752 start += addr; 753 754 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 755 lower_32_bits(start)); 756 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 757 upper_32_bits(start)); 758 759 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 760 if (cmd < 0x4) { 761 if ((end - start) < ctx->buf_sizes[cmd]) { 762 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 763 (unsigned)(end - start), 764 ctx->buf_sizes[cmd]); 765 return -EINVAL; 766 } 767 768 } else if (cmd == 0x206) { 769 if ((end - start) < ctx->buf_sizes[4]) { 770 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 771 (unsigned)(end - start), 772 ctx->buf_sizes[4]); 773 return -EINVAL; 774 } 775 } else if ((cmd != 0x100) && (cmd != 0x204)) { 776 DRM_ERROR("invalid UVD command %X!\n", cmd); 777 return -EINVAL; 778 } 779 780 if (!ctx->parser->adev->uvd.address_64_bit) { 781 if ((start >> 28) != ((end - 1) >> 28)) { 782 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 783 start, end); 784 return -EINVAL; 785 } 786 787 if ((cmd == 0 || cmd == 0x3) && 788 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { 789 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 790 start, end); 791 return -EINVAL; 792 } 793 } 794 795 if (cmd == 0) { 796 ctx->has_msg_cmd = true; 797 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 798 if (r) 799 return r; 800 } else if (!ctx->has_msg_cmd) { 801 DRM_ERROR("Message needed before other commands are send!\n"); 802 return -EINVAL; 803 } 804 805 return 0; 806 } 807 808 /** 809 * amdgpu_uvd_cs_reg - parse register writes 810 * 811 * @ctx: UVD parser context 812 * @cb: callback function 813 * 814 * Parse the register writes, call cb on each complete command. 815 */ 816 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 817 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 818 { 819 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 820 int i, r; 821 822 ctx->idx++; 823 for (i = 0; i <= ctx->count; ++i) { 824 unsigned reg = ctx->reg + i; 825 826 if (ctx->idx >= ib->length_dw) { 827 DRM_ERROR("Register command after end of CS!\n"); 828 return -EINVAL; 829 } 830 831 switch (reg) { 832 case mmUVD_GPCOM_VCPU_DATA0: 833 ctx->data0 = ctx->idx; 834 break; 835 case mmUVD_GPCOM_VCPU_DATA1: 836 ctx->data1 = ctx->idx; 837 break; 838 case mmUVD_GPCOM_VCPU_CMD: 839 r = cb(ctx); 840 if (r) 841 return r; 842 break; 843 case mmUVD_ENGINE_CNTL: 844 case mmUVD_NO_OP: 845 break; 846 default: 847 DRM_ERROR("Invalid reg 0x%X!\n", reg); 848 return -EINVAL; 849 } 850 ctx->idx++; 851 } 852 return 0; 853 } 854 855 /** 856 * amdgpu_uvd_cs_packets - parse UVD packets 857 * 858 * @ctx: UVD parser context 859 * @cb: callback function 860 * 861 * Parse the command stream packets. 862 */ 863 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 864 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 865 { 866 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 867 int r; 868 869 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 870 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 871 unsigned type = CP_PACKET_GET_TYPE(cmd); 872 switch (type) { 873 case PACKET_TYPE0: 874 ctx->reg = CP_PACKET0_GET_REG(cmd); 875 ctx->count = CP_PACKET_GET_COUNT(cmd); 876 r = amdgpu_uvd_cs_reg(ctx, cb); 877 if (r) 878 return r; 879 break; 880 case PACKET_TYPE2: 881 ++ctx->idx; 882 break; 883 default: 884 DRM_ERROR("Unknown packet type %d !\n", type); 885 return -EINVAL; 886 } 887 } 888 return 0; 889 } 890 891 /** 892 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 893 * 894 * @parser: Command submission parser context 895 * 896 * Parse the command stream, patch in addresses as necessary. 897 */ 898 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 899 { 900 struct amdgpu_uvd_cs_ctx ctx = {}; 901 unsigned buf_sizes[] = { 902 [0x00000000] = 2048, 903 [0x00000001] = 0xFFFFFFFF, 904 [0x00000002] = 0xFFFFFFFF, 905 [0x00000003] = 2048, 906 [0x00000004] = 0xFFFFFFFF, 907 }; 908 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 909 int r; 910 911 parser->job->vm = NULL; 912 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 913 914 if (ib->length_dw % 16) { 915 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 916 ib->length_dw); 917 return -EINVAL; 918 } 919 920 r = amdgpu_cs_sysvm_access_required(parser); 921 if (r) 922 return r; 923 924 ctx.parser = parser; 925 ctx.buf_sizes = buf_sizes; 926 ctx.ib_idx = ib_idx; 927 928 /* first round only required on chips without UVD 64 bit address support */ 929 if (!parser->adev->uvd.address_64_bit) { 930 /* first round, make sure the buffers are actually in the UVD segment */ 931 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 932 if (r) 933 return r; 934 } 935 936 /* second round, patch buffer addresses into the command stream */ 937 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 938 if (r) 939 return r; 940 941 if (!ctx.has_msg_cmd) { 942 DRM_ERROR("UVD-IBs need a msg command!\n"); 943 return -EINVAL; 944 } 945 946 return 0; 947 } 948 949 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 950 bool direct, struct dma_fence **fence) 951 { 952 struct ttm_validate_buffer tv; 953 struct ww_acquire_ctx ticket; 954 struct list_head head; 955 struct amdgpu_job *job; 956 struct amdgpu_ib *ib; 957 struct dma_fence *f = NULL; 958 struct amdgpu_device *adev = ring->adev; 959 uint64_t addr; 960 uint32_t data[4]; 961 int i, r; 962 963 memset(&tv, 0, sizeof(tv)); 964 tv.bo = &bo->tbo; 965 966 INIT_LIST_HEAD(&head); 967 list_add(&tv.head, &head); 968 969 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); 970 if (r) 971 return r; 972 973 if (!ring->adev->uvd.address_64_bit) { 974 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 975 amdgpu_uvd_force_into_uvd_segment(bo); 976 } 977 978 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 979 if (r) 980 goto err; 981 982 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 983 if (r) 984 goto err; 985 986 if (adev->asic_type >= CHIP_VEGA10) { 987 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0); 988 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0); 989 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0); 990 data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0); 991 } else { 992 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); 993 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); 994 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 995 data[3] = PACKET0(mmUVD_NO_OP, 0); 996 } 997 998 ib = &job->ibs[0]; 999 addr = amdgpu_bo_gpu_offset(bo); 1000 ib->ptr[0] = data[0]; 1001 ib->ptr[1] = addr; 1002 ib->ptr[2] = data[1]; 1003 ib->ptr[3] = addr >> 32; 1004 ib->ptr[4] = data[2]; 1005 ib->ptr[5] = 0; 1006 for (i = 6; i < 16; i += 2) { 1007 ib->ptr[i] = data[3]; 1008 ib->ptr[i+1] = 0; 1009 } 1010 ib->length_dw = 16; 1011 1012 if (direct) { 1013 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 1014 job->fence = dma_fence_get(f); 1015 if (r) 1016 goto err_free; 1017 1018 amdgpu_job_free(job); 1019 } else { 1020 r = amdgpu_job_submit(job, ring, &adev->uvd.entity, 1021 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1022 if (r) 1023 goto err_free; 1024 } 1025 1026 ttm_eu_fence_buffer_objects(&ticket, &head, f); 1027 1028 if (fence) 1029 *fence = dma_fence_get(f); 1030 amdgpu_bo_unref(&bo); 1031 dma_fence_put(f); 1032 1033 return 0; 1034 1035 err_free: 1036 amdgpu_job_free(job); 1037 1038 err: 1039 ttm_eu_backoff_reservation(&ticket, &head); 1040 return r; 1041 } 1042 1043 /* multiple fence commands without any stream commands in between can 1044 crash the vcpu so just try to emmit a dummy create/destroy msg to 1045 avoid this */ 1046 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1047 struct dma_fence **fence) 1048 { 1049 struct amdgpu_device *adev = ring->adev; 1050 struct amdgpu_bo *bo; 1051 uint32_t *msg; 1052 int r, i; 1053 1054 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 1055 AMDGPU_GEM_DOMAIN_VRAM, 1056 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1057 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1058 NULL, NULL, 0, &bo); 1059 if (r) 1060 return r; 1061 1062 r = amdgpu_bo_reserve(bo, false); 1063 if (r) { 1064 amdgpu_bo_unref(&bo); 1065 return r; 1066 } 1067 1068 r = amdgpu_bo_kmap(bo, (void **)&msg); 1069 if (r) { 1070 amdgpu_bo_unreserve(bo); 1071 amdgpu_bo_unref(&bo); 1072 return r; 1073 } 1074 1075 /* stitch together an UVD create msg */ 1076 msg[0] = cpu_to_le32(0x00000de4); 1077 msg[1] = cpu_to_le32(0x00000000); 1078 msg[2] = cpu_to_le32(handle); 1079 msg[3] = cpu_to_le32(0x00000000); 1080 msg[4] = cpu_to_le32(0x00000000); 1081 msg[5] = cpu_to_le32(0x00000000); 1082 msg[6] = cpu_to_le32(0x00000000); 1083 msg[7] = cpu_to_le32(0x00000780); 1084 msg[8] = cpu_to_le32(0x00000440); 1085 msg[9] = cpu_to_le32(0x00000000); 1086 msg[10] = cpu_to_le32(0x01b37000); 1087 for (i = 11; i < 1024; ++i) 1088 msg[i] = cpu_to_le32(0x0); 1089 1090 amdgpu_bo_kunmap(bo); 1091 amdgpu_bo_unreserve(bo); 1092 1093 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1094 } 1095 1096 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1097 bool direct, struct dma_fence **fence) 1098 { 1099 struct amdgpu_device *adev = ring->adev; 1100 struct amdgpu_bo *bo; 1101 uint32_t *msg; 1102 int r, i; 1103 1104 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 1105 AMDGPU_GEM_DOMAIN_VRAM, 1106 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1107 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1108 NULL, NULL, 0, &bo); 1109 if (r) 1110 return r; 1111 1112 r = amdgpu_bo_reserve(bo, false); 1113 if (r) { 1114 amdgpu_bo_unref(&bo); 1115 return r; 1116 } 1117 1118 r = amdgpu_bo_kmap(bo, (void **)&msg); 1119 if (r) { 1120 amdgpu_bo_unreserve(bo); 1121 amdgpu_bo_unref(&bo); 1122 return r; 1123 } 1124 1125 /* stitch together an UVD destroy msg */ 1126 msg[0] = cpu_to_le32(0x00000de4); 1127 msg[1] = cpu_to_le32(0x00000002); 1128 msg[2] = cpu_to_le32(handle); 1129 msg[3] = cpu_to_le32(0x00000000); 1130 for (i = 4; i < 1024; ++i) 1131 msg[i] = cpu_to_le32(0x0); 1132 1133 amdgpu_bo_kunmap(bo); 1134 amdgpu_bo_unreserve(bo); 1135 1136 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1137 } 1138 1139 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1140 { 1141 struct amdgpu_device *adev = 1142 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1143 unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring); 1144 1145 if (amdgpu_sriov_vf(adev)) 1146 return; 1147 1148 if (fences == 0) { 1149 if (adev->pm.dpm_enabled) { 1150 amdgpu_dpm_enable_uvd(adev, false); 1151 } else { 1152 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1153 /* shutdown the UVD block */ 1154 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1155 AMD_PG_STATE_GATE); 1156 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1157 AMD_CG_STATE_GATE); 1158 } 1159 } else { 1160 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1161 } 1162 } 1163 1164 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1165 { 1166 struct amdgpu_device *adev = ring->adev; 1167 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1168 1169 if (amdgpu_sriov_vf(adev)) 1170 return; 1171 1172 if (set_clocks) { 1173 if (adev->pm.dpm_enabled) { 1174 amdgpu_dpm_enable_uvd(adev, true); 1175 } else { 1176 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1177 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1178 AMD_CG_STATE_UNGATE); 1179 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1180 AMD_PG_STATE_UNGATE); 1181 } 1182 } 1183 } 1184 1185 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1186 { 1187 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1188 } 1189 1190 /** 1191 * amdgpu_uvd_ring_test_ib - test ib execution 1192 * 1193 * @ring: amdgpu_ring pointer 1194 * 1195 * Test if we can successfully execute an IB 1196 */ 1197 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1198 { 1199 struct dma_fence *fence; 1200 long r; 1201 1202 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1203 if (r) { 1204 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); 1205 goto error; 1206 } 1207 1208 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1209 if (r) { 1210 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); 1211 goto error; 1212 } 1213 1214 r = dma_fence_wait_timeout(fence, false, timeout); 1215 if (r == 0) { 1216 DRM_ERROR("amdgpu: IB test timed out.\n"); 1217 r = -ETIMEDOUT; 1218 } else if (r < 0) { 1219 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1220 } else { 1221 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 1222 r = 0; 1223 } 1224 1225 dma_fence_put(fence); 1226 1227 error: 1228 return r; 1229 } 1230 1231 /** 1232 * amdgpu_uvd_used_handles - returns used UVD handles 1233 * 1234 * @adev: amdgpu_device pointer 1235 * 1236 * Returns the number of UVD handles in use 1237 */ 1238 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1239 { 1240 unsigned i; 1241 uint32_t used_handles = 0; 1242 1243 for (i = 0; i < adev->uvd.max_handles; ++i) { 1244 /* 1245 * Handles can be freed in any order, and not 1246 * necessarily linear. So we need to count 1247 * all non-zero handles. 1248 */ 1249 if (atomic_read(&adev->uvd.handles[i])) 1250 used_handles++; 1251 } 1252 1253 return used_handles; 1254 } 1255