1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 /* 1 second timeout */ 43 #define UVD_IDLE_TIMEOUT_MS 1000 44 /* Polaris10/11 firmware version */ 45 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 46 47 /* Firmware Names */ 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 50 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" 51 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" 52 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" 53 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" 54 #endif 55 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 56 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 57 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 58 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 59 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 60 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 61 62 /** 63 * amdgpu_uvd_cs_ctx - Command submission parser context 64 * 65 * Used for emulating virtual memory support on UVD 4.2. 66 */ 67 struct amdgpu_uvd_cs_ctx { 68 struct amdgpu_cs_parser *parser; 69 unsigned reg, count; 70 unsigned data0, data1; 71 unsigned idx; 72 unsigned ib_idx; 73 74 /* does the IB has a msg command */ 75 bool has_msg_cmd; 76 77 /* minimum buffer sizes */ 78 unsigned *buf_sizes; 79 }; 80 81 #ifdef CONFIG_DRM_AMDGPU_CIK 82 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 83 MODULE_FIRMWARE(FIRMWARE_KABINI); 84 MODULE_FIRMWARE(FIRMWARE_KAVERI); 85 MODULE_FIRMWARE(FIRMWARE_HAWAII); 86 MODULE_FIRMWARE(FIRMWARE_MULLINS); 87 #endif 88 MODULE_FIRMWARE(FIRMWARE_TONGA); 89 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 90 MODULE_FIRMWARE(FIRMWARE_FIJI); 91 MODULE_FIRMWARE(FIRMWARE_STONEY); 92 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 93 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 94 95 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); 96 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 97 98 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 99 { 100 struct amdgpu_ring *ring; 101 struct amd_sched_rq *rq; 102 unsigned long bo_size; 103 const char *fw_name; 104 const struct common_firmware_header *hdr; 105 unsigned version_major, version_minor, family_id; 106 int i, r; 107 108 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 109 110 switch (adev->asic_type) { 111 #ifdef CONFIG_DRM_AMDGPU_CIK 112 case CHIP_BONAIRE: 113 fw_name = FIRMWARE_BONAIRE; 114 break; 115 case CHIP_KABINI: 116 fw_name = FIRMWARE_KABINI; 117 break; 118 case CHIP_KAVERI: 119 fw_name = FIRMWARE_KAVERI; 120 break; 121 case CHIP_HAWAII: 122 fw_name = FIRMWARE_HAWAII; 123 break; 124 case CHIP_MULLINS: 125 fw_name = FIRMWARE_MULLINS; 126 break; 127 #endif 128 case CHIP_TONGA: 129 fw_name = FIRMWARE_TONGA; 130 break; 131 case CHIP_FIJI: 132 fw_name = FIRMWARE_FIJI; 133 break; 134 case CHIP_CARRIZO: 135 fw_name = FIRMWARE_CARRIZO; 136 break; 137 case CHIP_STONEY: 138 fw_name = FIRMWARE_STONEY; 139 break; 140 case CHIP_POLARIS10: 141 fw_name = FIRMWARE_POLARIS10; 142 break; 143 case CHIP_POLARIS11: 144 fw_name = FIRMWARE_POLARIS11; 145 break; 146 default: 147 return -EINVAL; 148 } 149 150 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 151 if (r) { 152 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 153 fw_name); 154 return r; 155 } 156 157 r = amdgpu_ucode_validate(adev->uvd.fw); 158 if (r) { 159 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 160 fw_name); 161 release_firmware(adev->uvd.fw); 162 adev->uvd.fw = NULL; 163 return r; 164 } 165 166 /* Set the default UVD handles that the firmware can handle */ 167 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 168 169 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 170 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 171 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 172 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 173 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 174 version_major, version_minor, family_id); 175 176 /* 177 * Limit the number of UVD handles depending on microcode major 178 * and minor versions. The firmware version which has 40 UVD 179 * instances support is 1.80. So all subsequent versions should 180 * also have the same support. 181 */ 182 if ((version_major > 0x01) || 183 ((version_major == 0x01) && (version_minor >= 0x50))) 184 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 185 186 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 187 (family_id << 8)); 188 189 if ((adev->asic_type == CHIP_POLARIS10 || 190 adev->asic_type == CHIP_POLARIS11) && 191 (adev->uvd.fw_version < FW_1_66_16)) 192 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", 193 version_major, version_minor); 194 195 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) 196 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 197 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 198 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, 199 AMDGPU_GEM_DOMAIN_VRAM, 200 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 201 NULL, NULL, &adev->uvd.vcpu_bo); 202 if (r) { 203 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 204 return r; 205 } 206 207 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 208 if (r) { 209 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 210 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r); 211 return r; 212 } 213 214 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, 215 &adev->uvd.gpu_addr); 216 if (r) { 217 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 218 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 219 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r); 220 return r; 221 } 222 223 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr); 224 if (r) { 225 dev_err(adev->dev, "(%d) UVD map failed\n", r); 226 return r; 227 } 228 229 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 230 231 ring = &adev->uvd.ring; 232 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; 233 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, 234 rq, amdgpu_sched_jobs); 235 if (r != 0) { 236 DRM_ERROR("Failed setting up UVD run queue.\n"); 237 return r; 238 } 239 240 for (i = 0; i < adev->uvd.max_handles; ++i) { 241 atomic_set(&adev->uvd.handles[i], 0); 242 adev->uvd.filp[i] = NULL; 243 } 244 245 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 246 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 247 adev->uvd.address_64_bit = true; 248 249 return 0; 250 } 251 252 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 253 { 254 int r; 255 256 if (adev->uvd.vcpu_bo == NULL) 257 return 0; 258 259 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); 260 261 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 262 if (!r) { 263 amdgpu_bo_kunmap(adev->uvd.vcpu_bo); 264 amdgpu_bo_unpin(adev->uvd.vcpu_bo); 265 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 266 } 267 268 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 269 270 amdgpu_ring_fini(&adev->uvd.ring); 271 272 release_firmware(adev->uvd.fw); 273 274 return 0; 275 } 276 277 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 278 { 279 unsigned size; 280 void *ptr; 281 int i; 282 283 if (adev->uvd.vcpu_bo == NULL) 284 return 0; 285 286 for (i = 0; i < adev->uvd.max_handles; ++i) 287 if (atomic_read(&adev->uvd.handles[i])) 288 break; 289 290 if (i == AMDGPU_MAX_UVD_HANDLES) 291 return 0; 292 293 cancel_delayed_work_sync(&adev->uvd.idle_work); 294 295 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 296 ptr = adev->uvd.cpu_addr; 297 298 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 299 if (!adev->uvd.saved_bo) 300 return -ENOMEM; 301 302 memcpy(adev->uvd.saved_bo, ptr, size); 303 304 return 0; 305 } 306 307 int amdgpu_uvd_resume(struct amdgpu_device *adev) 308 { 309 unsigned size; 310 void *ptr; 311 312 if (adev->uvd.vcpu_bo == NULL) 313 return -EINVAL; 314 315 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 316 ptr = adev->uvd.cpu_addr; 317 318 if (adev->uvd.saved_bo != NULL) { 319 memcpy(ptr, adev->uvd.saved_bo, size); 320 kfree(adev->uvd.saved_bo); 321 adev->uvd.saved_bo = NULL; 322 } else { 323 const struct common_firmware_header *hdr; 324 unsigned offset; 325 326 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 327 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 328 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, 329 (adev->uvd.fw->size) - offset); 330 size -= le32_to_cpu(hdr->ucode_size_bytes); 331 ptr += le32_to_cpu(hdr->ucode_size_bytes); 332 memset(ptr, 0, size); 333 } 334 335 return 0; 336 } 337 338 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 339 { 340 struct amdgpu_ring *ring = &adev->uvd.ring; 341 int i, r; 342 343 for (i = 0; i < adev->uvd.max_handles; ++i) { 344 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 345 if (handle != 0 && adev->uvd.filp[i] == filp) { 346 struct fence *fence; 347 348 amdgpu_uvd_note_usage(adev); 349 350 r = amdgpu_uvd_get_destroy_msg(ring, handle, 351 false, &fence); 352 if (r) { 353 DRM_ERROR("Error destroying UVD (%d)!\n", r); 354 continue; 355 } 356 357 fence_wait(fence, false); 358 fence_put(fence); 359 360 adev->uvd.filp[i] = NULL; 361 atomic_set(&adev->uvd.handles[i], 0); 362 } 363 } 364 } 365 366 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) 367 { 368 int i; 369 for (i = 0; i < rbo->placement.num_placement; ++i) { 370 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; 371 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 372 } 373 } 374 375 /** 376 * amdgpu_uvd_cs_pass1 - first parsing round 377 * 378 * @ctx: UVD parser context 379 * 380 * Make sure UVD message and feedback buffers are in VRAM and 381 * nobody is violating an 256MB boundary. 382 */ 383 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 384 { 385 struct amdgpu_bo_va_mapping *mapping; 386 struct amdgpu_bo *bo; 387 uint32_t cmd, lo, hi; 388 uint64_t addr; 389 int r = 0; 390 391 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 392 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 393 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 394 395 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 396 if (mapping == NULL) { 397 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 398 return -EINVAL; 399 } 400 401 if (!ctx->parser->adev->uvd.address_64_bit) { 402 /* check if it's a message or feedback command */ 403 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 404 if (cmd == 0x0 || cmd == 0x3) { 405 /* yes, force it into VRAM */ 406 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 407 amdgpu_ttm_placement_from_domain(bo, domain); 408 } 409 amdgpu_uvd_force_into_uvd_segment(bo); 410 411 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 412 } 413 414 return r; 415 } 416 417 /** 418 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 419 * 420 * @msg: pointer to message structure 421 * @buf_sizes: returned buffer sizes 422 * 423 * Peek into the decode message and calculate the necessary buffer sizes. 424 */ 425 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 426 unsigned buf_sizes[]) 427 { 428 unsigned stream_type = msg[4]; 429 unsigned width = msg[6]; 430 unsigned height = msg[7]; 431 unsigned dpb_size = msg[9]; 432 unsigned pitch = msg[28]; 433 unsigned level = msg[57]; 434 435 unsigned width_in_mb = width / 16; 436 unsigned height_in_mb = ALIGN(height / 16, 2); 437 unsigned fs_in_mb = width_in_mb * height_in_mb; 438 439 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 440 unsigned min_ctx_size = 0; 441 442 image_size = width * height; 443 image_size += image_size / 2; 444 image_size = ALIGN(image_size, 1024); 445 446 switch (stream_type) { 447 case 0: /* H264 */ 448 switch(level) { 449 case 30: 450 num_dpb_buffer = 8100 / fs_in_mb; 451 break; 452 case 31: 453 num_dpb_buffer = 18000 / fs_in_mb; 454 break; 455 case 32: 456 num_dpb_buffer = 20480 / fs_in_mb; 457 break; 458 case 41: 459 num_dpb_buffer = 32768 / fs_in_mb; 460 break; 461 case 42: 462 num_dpb_buffer = 34816 / fs_in_mb; 463 break; 464 case 50: 465 num_dpb_buffer = 110400 / fs_in_mb; 466 break; 467 case 51: 468 num_dpb_buffer = 184320 / fs_in_mb; 469 break; 470 default: 471 num_dpb_buffer = 184320 / fs_in_mb; 472 break; 473 } 474 num_dpb_buffer++; 475 if (num_dpb_buffer > 17) 476 num_dpb_buffer = 17; 477 478 /* reference picture buffer */ 479 min_dpb_size = image_size * num_dpb_buffer; 480 481 /* macroblock context buffer */ 482 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 483 484 /* IT surface buffer */ 485 min_dpb_size += width_in_mb * height_in_mb * 32; 486 break; 487 488 case 1: /* VC1 */ 489 490 /* reference picture buffer */ 491 min_dpb_size = image_size * 3; 492 493 /* CONTEXT_BUFFER */ 494 min_dpb_size += width_in_mb * height_in_mb * 128; 495 496 /* IT surface buffer */ 497 min_dpb_size += width_in_mb * 64; 498 499 /* DB surface buffer */ 500 min_dpb_size += width_in_mb * 128; 501 502 /* BP */ 503 tmp = max(width_in_mb, height_in_mb); 504 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 505 break; 506 507 case 3: /* MPEG2 */ 508 509 /* reference picture buffer */ 510 min_dpb_size = image_size * 3; 511 break; 512 513 case 4: /* MPEG4 */ 514 515 /* reference picture buffer */ 516 min_dpb_size = image_size * 3; 517 518 /* CM */ 519 min_dpb_size += width_in_mb * height_in_mb * 64; 520 521 /* IT surface buffer */ 522 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 523 break; 524 525 case 7: /* H264 Perf */ 526 switch(level) { 527 case 30: 528 num_dpb_buffer = 8100 / fs_in_mb; 529 break; 530 case 31: 531 num_dpb_buffer = 18000 / fs_in_mb; 532 break; 533 case 32: 534 num_dpb_buffer = 20480 / fs_in_mb; 535 break; 536 case 41: 537 num_dpb_buffer = 32768 / fs_in_mb; 538 break; 539 case 42: 540 num_dpb_buffer = 34816 / fs_in_mb; 541 break; 542 case 50: 543 num_dpb_buffer = 110400 / fs_in_mb; 544 break; 545 case 51: 546 num_dpb_buffer = 184320 / fs_in_mb; 547 break; 548 default: 549 num_dpb_buffer = 184320 / fs_in_mb; 550 break; 551 } 552 num_dpb_buffer++; 553 if (num_dpb_buffer > 17) 554 num_dpb_buffer = 17; 555 556 /* reference picture buffer */ 557 min_dpb_size = image_size * num_dpb_buffer; 558 559 if (adev->asic_type < CHIP_POLARIS10){ 560 /* macroblock context buffer */ 561 min_dpb_size += 562 width_in_mb * height_in_mb * num_dpb_buffer * 192; 563 564 /* IT surface buffer */ 565 min_dpb_size += width_in_mb * height_in_mb * 32; 566 } else { 567 /* macroblock context buffer */ 568 min_ctx_size = 569 width_in_mb * height_in_mb * num_dpb_buffer * 192; 570 } 571 break; 572 573 case 16: /* H265 */ 574 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 575 image_size = ALIGN(image_size, 256); 576 577 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 578 min_dpb_size = image_size * num_dpb_buffer; 579 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 580 * 16 * num_dpb_buffer + 52 * 1024; 581 break; 582 583 default: 584 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 585 return -EINVAL; 586 } 587 588 if (width > pitch) { 589 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 590 return -EINVAL; 591 } 592 593 if (dpb_size < min_dpb_size) { 594 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 595 dpb_size, min_dpb_size); 596 return -EINVAL; 597 } 598 599 buf_sizes[0x1] = dpb_size; 600 buf_sizes[0x2] = image_size; 601 buf_sizes[0x4] = min_ctx_size; 602 return 0; 603 } 604 605 /** 606 * amdgpu_uvd_cs_msg - handle UVD message 607 * 608 * @ctx: UVD parser context 609 * @bo: buffer object containing the message 610 * @offset: offset into the buffer object 611 * 612 * Peek into the UVD message and extract the session id. 613 * Make sure that we don't open up to many sessions. 614 */ 615 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 616 struct amdgpu_bo *bo, unsigned offset) 617 { 618 struct amdgpu_device *adev = ctx->parser->adev; 619 int32_t *msg, msg_type, handle; 620 void *ptr; 621 long r; 622 int i; 623 624 if (offset & 0x3F) { 625 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 626 return -EINVAL; 627 } 628 629 r = amdgpu_bo_kmap(bo, &ptr); 630 if (r) { 631 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); 632 return r; 633 } 634 635 msg = ptr + offset; 636 637 msg_type = msg[1]; 638 handle = msg[2]; 639 640 if (handle == 0) { 641 DRM_ERROR("Invalid UVD handle!\n"); 642 return -EINVAL; 643 } 644 645 switch (msg_type) { 646 case 0: 647 /* it's a create msg, calc image size (width * height) */ 648 amdgpu_bo_kunmap(bo); 649 650 /* try to alloc a new handle */ 651 for (i = 0; i < adev->uvd.max_handles; ++i) { 652 if (atomic_read(&adev->uvd.handles[i]) == handle) { 653 DRM_ERROR("Handle 0x%x already in use!\n", handle); 654 return -EINVAL; 655 } 656 657 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 658 adev->uvd.filp[i] = ctx->parser->filp; 659 return 0; 660 } 661 } 662 663 DRM_ERROR("No more free UVD handles!\n"); 664 return -EINVAL; 665 666 case 1: 667 /* it's a decode msg, calc buffer sizes */ 668 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 669 amdgpu_bo_kunmap(bo); 670 if (r) 671 return r; 672 673 /* validate the handle */ 674 for (i = 0; i < adev->uvd.max_handles; ++i) { 675 if (atomic_read(&adev->uvd.handles[i]) == handle) { 676 if (adev->uvd.filp[i] != ctx->parser->filp) { 677 DRM_ERROR("UVD handle collision detected!\n"); 678 return -EINVAL; 679 } 680 return 0; 681 } 682 } 683 684 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 685 return -ENOENT; 686 687 case 2: 688 /* it's a destroy msg, free the handle */ 689 for (i = 0; i < adev->uvd.max_handles; ++i) 690 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 691 amdgpu_bo_kunmap(bo); 692 return 0; 693 694 default: 695 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 696 return -EINVAL; 697 } 698 BUG(); 699 return -EINVAL; 700 } 701 702 /** 703 * amdgpu_uvd_cs_pass2 - second parsing round 704 * 705 * @ctx: UVD parser context 706 * 707 * Patch buffer addresses, make sure buffer sizes are correct. 708 */ 709 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 710 { 711 struct amdgpu_bo_va_mapping *mapping; 712 struct amdgpu_bo *bo; 713 uint32_t cmd, lo, hi; 714 uint64_t start, end; 715 uint64_t addr; 716 int r; 717 718 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 719 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 720 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 721 722 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 723 if (mapping == NULL) 724 return -EINVAL; 725 726 start = amdgpu_bo_gpu_offset(bo); 727 728 end = (mapping->it.last + 1 - mapping->it.start); 729 end = end * AMDGPU_GPU_PAGE_SIZE + start; 730 731 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; 732 start += addr; 733 734 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 735 lower_32_bits(start)); 736 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 737 upper_32_bits(start)); 738 739 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 740 if (cmd < 0x4) { 741 if ((end - start) < ctx->buf_sizes[cmd]) { 742 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 743 (unsigned)(end - start), 744 ctx->buf_sizes[cmd]); 745 return -EINVAL; 746 } 747 748 } else if (cmd == 0x206) { 749 if ((end - start) < ctx->buf_sizes[4]) { 750 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 751 (unsigned)(end - start), 752 ctx->buf_sizes[4]); 753 return -EINVAL; 754 } 755 } else if ((cmd != 0x100) && (cmd != 0x204)) { 756 DRM_ERROR("invalid UVD command %X!\n", cmd); 757 return -EINVAL; 758 } 759 760 if (!ctx->parser->adev->uvd.address_64_bit) { 761 if ((start >> 28) != ((end - 1) >> 28)) { 762 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 763 start, end); 764 return -EINVAL; 765 } 766 767 if ((cmd == 0 || cmd == 0x3) && 768 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { 769 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 770 start, end); 771 return -EINVAL; 772 } 773 } 774 775 if (cmd == 0) { 776 ctx->has_msg_cmd = true; 777 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 778 if (r) 779 return r; 780 } else if (!ctx->has_msg_cmd) { 781 DRM_ERROR("Message needed before other commands are send!\n"); 782 return -EINVAL; 783 } 784 785 return 0; 786 } 787 788 /** 789 * amdgpu_uvd_cs_reg - parse register writes 790 * 791 * @ctx: UVD parser context 792 * @cb: callback function 793 * 794 * Parse the register writes, call cb on each complete command. 795 */ 796 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 797 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 798 { 799 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 800 int i, r; 801 802 ctx->idx++; 803 for (i = 0; i <= ctx->count; ++i) { 804 unsigned reg = ctx->reg + i; 805 806 if (ctx->idx >= ib->length_dw) { 807 DRM_ERROR("Register command after end of CS!\n"); 808 return -EINVAL; 809 } 810 811 switch (reg) { 812 case mmUVD_GPCOM_VCPU_DATA0: 813 ctx->data0 = ctx->idx; 814 break; 815 case mmUVD_GPCOM_VCPU_DATA1: 816 ctx->data1 = ctx->idx; 817 break; 818 case mmUVD_GPCOM_VCPU_CMD: 819 r = cb(ctx); 820 if (r) 821 return r; 822 break; 823 case mmUVD_ENGINE_CNTL: 824 break; 825 default: 826 DRM_ERROR("Invalid reg 0x%X!\n", reg); 827 return -EINVAL; 828 } 829 ctx->idx++; 830 } 831 return 0; 832 } 833 834 /** 835 * amdgpu_uvd_cs_packets - parse UVD packets 836 * 837 * @ctx: UVD parser context 838 * @cb: callback function 839 * 840 * Parse the command stream packets. 841 */ 842 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 843 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 844 { 845 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 846 int r; 847 848 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 849 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 850 unsigned type = CP_PACKET_GET_TYPE(cmd); 851 switch (type) { 852 case PACKET_TYPE0: 853 ctx->reg = CP_PACKET0_GET_REG(cmd); 854 ctx->count = CP_PACKET_GET_COUNT(cmd); 855 r = amdgpu_uvd_cs_reg(ctx, cb); 856 if (r) 857 return r; 858 break; 859 case PACKET_TYPE2: 860 ++ctx->idx; 861 break; 862 default: 863 DRM_ERROR("Unknown packet type %d !\n", type); 864 return -EINVAL; 865 } 866 } 867 return 0; 868 } 869 870 /** 871 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 872 * 873 * @parser: Command submission parser context 874 * 875 * Parse the command stream, patch in addresses as necessary. 876 */ 877 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 878 { 879 struct amdgpu_uvd_cs_ctx ctx = {}; 880 unsigned buf_sizes[] = { 881 [0x00000000] = 2048, 882 [0x00000001] = 0xFFFFFFFF, 883 [0x00000002] = 0xFFFFFFFF, 884 [0x00000003] = 2048, 885 [0x00000004] = 0xFFFFFFFF, 886 }; 887 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 888 int r; 889 890 if (ib->length_dw % 16) { 891 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 892 ib->length_dw); 893 return -EINVAL; 894 } 895 896 ctx.parser = parser; 897 ctx.buf_sizes = buf_sizes; 898 ctx.ib_idx = ib_idx; 899 900 /* first round, make sure the buffers are actually in the UVD segment */ 901 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 902 if (r) 903 return r; 904 905 /* second round, patch buffer addresses into the command stream */ 906 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 907 if (r) 908 return r; 909 910 if (!ctx.has_msg_cmd) { 911 DRM_ERROR("UVD-IBs need a msg command!\n"); 912 return -EINVAL; 913 } 914 915 amdgpu_uvd_note_usage(ctx.parser->adev); 916 917 return 0; 918 } 919 920 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 921 bool direct, struct fence **fence) 922 { 923 struct ttm_validate_buffer tv; 924 struct ww_acquire_ctx ticket; 925 struct list_head head; 926 struct amdgpu_job *job; 927 struct amdgpu_ib *ib; 928 struct fence *f = NULL; 929 struct amdgpu_device *adev = ring->adev; 930 uint64_t addr; 931 int i, r; 932 933 memset(&tv, 0, sizeof(tv)); 934 tv.bo = &bo->tbo; 935 936 INIT_LIST_HEAD(&head); 937 list_add(&tv.head, &head); 938 939 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); 940 if (r) 941 return r; 942 943 if (!bo->adev->uvd.address_64_bit) { 944 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 945 amdgpu_uvd_force_into_uvd_segment(bo); 946 } 947 948 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 949 if (r) 950 goto err; 951 952 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 953 if (r) 954 goto err; 955 956 ib = &job->ibs[0]; 957 addr = amdgpu_bo_gpu_offset(bo); 958 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); 959 ib->ptr[1] = addr; 960 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); 961 ib->ptr[3] = addr >> 32; 962 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 963 ib->ptr[5] = 0; 964 for (i = 6; i < 16; ++i) 965 ib->ptr[i] = PACKET2(0); 966 ib->length_dw = 16; 967 968 if (direct) { 969 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); 970 job->fence = f; 971 if (r) 972 goto err_free; 973 974 amdgpu_job_free(job); 975 } else { 976 r = amdgpu_job_submit(job, ring, &adev->uvd.entity, 977 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 978 if (r) 979 goto err_free; 980 } 981 982 ttm_eu_fence_buffer_objects(&ticket, &head, f); 983 984 if (fence) 985 *fence = fence_get(f); 986 amdgpu_bo_unref(&bo); 987 fence_put(f); 988 989 return 0; 990 991 err_free: 992 amdgpu_job_free(job); 993 994 err: 995 ttm_eu_backoff_reservation(&ticket, &head); 996 return r; 997 } 998 999 /* multiple fence commands without any stream commands in between can 1000 crash the vcpu so just try to emmit a dummy create/destroy msg to 1001 avoid this */ 1002 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1003 struct fence **fence) 1004 { 1005 struct amdgpu_device *adev = ring->adev; 1006 struct amdgpu_bo *bo; 1007 uint32_t *msg; 1008 int r, i; 1009 1010 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 1011 AMDGPU_GEM_DOMAIN_VRAM, 1012 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 1013 NULL, NULL, &bo); 1014 if (r) 1015 return r; 1016 1017 r = amdgpu_bo_reserve(bo, false); 1018 if (r) { 1019 amdgpu_bo_unref(&bo); 1020 return r; 1021 } 1022 1023 r = amdgpu_bo_kmap(bo, (void **)&msg); 1024 if (r) { 1025 amdgpu_bo_unreserve(bo); 1026 amdgpu_bo_unref(&bo); 1027 return r; 1028 } 1029 1030 /* stitch together an UVD create msg */ 1031 msg[0] = cpu_to_le32(0x00000de4); 1032 msg[1] = cpu_to_le32(0x00000000); 1033 msg[2] = cpu_to_le32(handle); 1034 msg[3] = cpu_to_le32(0x00000000); 1035 msg[4] = cpu_to_le32(0x00000000); 1036 msg[5] = cpu_to_le32(0x00000000); 1037 msg[6] = cpu_to_le32(0x00000000); 1038 msg[7] = cpu_to_le32(0x00000780); 1039 msg[8] = cpu_to_le32(0x00000440); 1040 msg[9] = cpu_to_le32(0x00000000); 1041 msg[10] = cpu_to_le32(0x01b37000); 1042 for (i = 11; i < 1024; ++i) 1043 msg[i] = cpu_to_le32(0x0); 1044 1045 amdgpu_bo_kunmap(bo); 1046 amdgpu_bo_unreserve(bo); 1047 1048 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1049 } 1050 1051 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1052 bool direct, struct fence **fence) 1053 { 1054 struct amdgpu_device *adev = ring->adev; 1055 struct amdgpu_bo *bo; 1056 uint32_t *msg; 1057 int r, i; 1058 1059 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 1060 AMDGPU_GEM_DOMAIN_VRAM, 1061 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 1062 NULL, NULL, &bo); 1063 if (r) 1064 return r; 1065 1066 r = amdgpu_bo_reserve(bo, false); 1067 if (r) { 1068 amdgpu_bo_unref(&bo); 1069 return r; 1070 } 1071 1072 r = amdgpu_bo_kmap(bo, (void **)&msg); 1073 if (r) { 1074 amdgpu_bo_unreserve(bo); 1075 amdgpu_bo_unref(&bo); 1076 return r; 1077 } 1078 1079 /* stitch together an UVD destroy msg */ 1080 msg[0] = cpu_to_le32(0x00000de4); 1081 msg[1] = cpu_to_le32(0x00000002); 1082 msg[2] = cpu_to_le32(handle); 1083 msg[3] = cpu_to_le32(0x00000000); 1084 for (i = 4; i < 1024; ++i) 1085 msg[i] = cpu_to_le32(0x0); 1086 1087 amdgpu_bo_kunmap(bo); 1088 amdgpu_bo_unreserve(bo); 1089 1090 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1091 } 1092 1093 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1094 { 1095 struct amdgpu_device *adev = 1096 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1097 unsigned i, fences, handles = 0; 1098 1099 fences = amdgpu_fence_count_emitted(&adev->uvd.ring); 1100 1101 for (i = 0; i < adev->uvd.max_handles; ++i) 1102 if (atomic_read(&adev->uvd.handles[i])) 1103 ++handles; 1104 1105 if (fences == 0 && handles == 0) { 1106 if (adev->pm.dpm_enabled) { 1107 amdgpu_dpm_enable_uvd(adev, false); 1108 } else { 1109 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1110 } 1111 } else { 1112 schedule_delayed_work(&adev->uvd.idle_work, 1113 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 1114 } 1115 } 1116 1117 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev) 1118 { 1119 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1120 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work, 1121 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 1122 1123 if (set_clocks) { 1124 if (adev->pm.dpm_enabled) { 1125 amdgpu_dpm_enable_uvd(adev, true); 1126 } else { 1127 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1128 } 1129 } 1130 } 1131