1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 #include <drm/drm_drv.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_pm.h" 39 #include "amdgpu_uvd.h" 40 #include "cikd.h" 41 #include "uvd/uvd_4_2_d.h" 42 43 #include "amdgpu_ras.h" 44 45 /* 1 second timeout */ 46 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 47 48 /* Firmware versions for VI */ 49 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 50 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 51 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 52 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 53 54 /* Polaris10/11 firmware version */ 55 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 56 57 /* Firmware Names */ 58 #ifdef CONFIG_DRM_AMDGPU_SI 59 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin" 60 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin" 61 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin" 62 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin" 63 #endif 64 #ifdef CONFIG_DRM_AMDGPU_CIK 65 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 66 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 67 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 68 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 69 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 70 #endif 71 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 72 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 73 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 74 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 75 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 76 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 77 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 78 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 79 80 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 81 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 82 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 83 84 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 85 #define UVD_GPCOM_VCPU_CMD 0x03c3 86 #define UVD_GPCOM_VCPU_DATA0 0x03c4 87 #define UVD_GPCOM_VCPU_DATA1 0x03c5 88 #define UVD_NO_OP 0x03ff 89 #define UVD_BASE_SI 0x3800 90 91 /* 92 * amdgpu_uvd_cs_ctx - Command submission parser context 93 * 94 * Used for emulating virtual memory support on UVD 4.2. 95 */ 96 struct amdgpu_uvd_cs_ctx { 97 struct amdgpu_cs_parser *parser; 98 unsigned reg, count; 99 unsigned data0, data1; 100 unsigned idx; 101 unsigned ib_idx; 102 103 /* does the IB has a msg command */ 104 bool has_msg_cmd; 105 106 /* minimum buffer sizes */ 107 unsigned *buf_sizes; 108 }; 109 110 #ifdef CONFIG_DRM_AMDGPU_SI 111 MODULE_FIRMWARE(FIRMWARE_TAHITI); 112 MODULE_FIRMWARE(FIRMWARE_VERDE); 113 MODULE_FIRMWARE(FIRMWARE_PITCAIRN); 114 MODULE_FIRMWARE(FIRMWARE_OLAND); 115 #endif 116 #ifdef CONFIG_DRM_AMDGPU_CIK 117 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 118 MODULE_FIRMWARE(FIRMWARE_KABINI); 119 MODULE_FIRMWARE(FIRMWARE_KAVERI); 120 MODULE_FIRMWARE(FIRMWARE_HAWAII); 121 MODULE_FIRMWARE(FIRMWARE_MULLINS); 122 #endif 123 MODULE_FIRMWARE(FIRMWARE_TONGA); 124 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 125 MODULE_FIRMWARE(FIRMWARE_FIJI); 126 MODULE_FIRMWARE(FIRMWARE_STONEY); 127 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 128 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 129 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 130 MODULE_FIRMWARE(FIRMWARE_VEGAM); 131 132 MODULE_FIRMWARE(FIRMWARE_VEGA10); 133 MODULE_FIRMWARE(FIRMWARE_VEGA12); 134 MODULE_FIRMWARE(FIRMWARE_VEGA20); 135 136 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 137 138 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 139 { 140 unsigned long bo_size; 141 const char *fw_name; 142 const struct common_firmware_header *hdr; 143 unsigned family_id; 144 int i, j, r; 145 146 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 147 148 switch (adev->asic_type) { 149 #ifdef CONFIG_DRM_AMDGPU_SI 150 case CHIP_TAHITI: 151 fw_name = FIRMWARE_TAHITI; 152 break; 153 case CHIP_VERDE: 154 fw_name = FIRMWARE_VERDE; 155 break; 156 case CHIP_PITCAIRN: 157 fw_name = FIRMWARE_PITCAIRN; 158 break; 159 case CHIP_OLAND: 160 fw_name = FIRMWARE_OLAND; 161 break; 162 #endif 163 #ifdef CONFIG_DRM_AMDGPU_CIK 164 case CHIP_BONAIRE: 165 fw_name = FIRMWARE_BONAIRE; 166 break; 167 case CHIP_KABINI: 168 fw_name = FIRMWARE_KABINI; 169 break; 170 case CHIP_KAVERI: 171 fw_name = FIRMWARE_KAVERI; 172 break; 173 case CHIP_HAWAII: 174 fw_name = FIRMWARE_HAWAII; 175 break; 176 case CHIP_MULLINS: 177 fw_name = FIRMWARE_MULLINS; 178 break; 179 #endif 180 case CHIP_TONGA: 181 fw_name = FIRMWARE_TONGA; 182 break; 183 case CHIP_FIJI: 184 fw_name = FIRMWARE_FIJI; 185 break; 186 case CHIP_CARRIZO: 187 fw_name = FIRMWARE_CARRIZO; 188 break; 189 case CHIP_STONEY: 190 fw_name = FIRMWARE_STONEY; 191 break; 192 case CHIP_POLARIS10: 193 fw_name = FIRMWARE_POLARIS10; 194 break; 195 case CHIP_POLARIS11: 196 fw_name = FIRMWARE_POLARIS11; 197 break; 198 case CHIP_POLARIS12: 199 fw_name = FIRMWARE_POLARIS12; 200 break; 201 case CHIP_VEGA10: 202 fw_name = FIRMWARE_VEGA10; 203 break; 204 case CHIP_VEGA12: 205 fw_name = FIRMWARE_VEGA12; 206 break; 207 case CHIP_VEGAM: 208 fw_name = FIRMWARE_VEGAM; 209 break; 210 case CHIP_VEGA20: 211 fw_name = FIRMWARE_VEGA20; 212 break; 213 default: 214 return -EINVAL; 215 } 216 217 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 218 if (r) { 219 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 220 fw_name); 221 return r; 222 } 223 224 r = amdgpu_ucode_validate(adev->uvd.fw); 225 if (r) { 226 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 227 fw_name); 228 release_firmware(adev->uvd.fw); 229 adev->uvd.fw = NULL; 230 return r; 231 } 232 233 /* Set the default UVD handles that the firmware can handle */ 234 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 235 236 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 237 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 238 239 if (adev->asic_type < CHIP_VEGA20) { 240 unsigned version_major, version_minor; 241 242 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 243 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 244 DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n", 245 version_major, version_minor, family_id); 246 247 /* 248 * Limit the number of UVD handles depending on microcode major 249 * and minor versions. The firmware version which has 40 UVD 250 * instances support is 1.80. So all subsequent versions should 251 * also have the same support. 252 */ 253 if ((version_major > 0x01) || 254 ((version_major == 0x01) && (version_minor >= 0x50))) 255 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 256 257 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 258 (family_id << 8)); 259 260 if ((adev->asic_type == CHIP_POLARIS10 || 261 adev->asic_type == CHIP_POLARIS11) && 262 (adev->uvd.fw_version < FW_1_66_16)) 263 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n", 264 version_major, version_minor); 265 } else { 266 unsigned int enc_major, enc_minor, dec_minor; 267 268 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 269 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 270 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 271 DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", 272 enc_major, enc_minor, dec_minor, family_id); 273 274 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 275 276 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 277 } 278 279 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 280 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 281 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 282 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 283 284 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 285 if (adev->uvd.harvest_config & (1 << j)) 286 continue; 287 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 288 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo, 289 &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr); 290 if (r) { 291 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 292 return r; 293 } 294 } 295 296 for (i = 0; i < adev->uvd.max_handles; ++i) { 297 atomic_set(&adev->uvd.handles[i], 0); 298 adev->uvd.filp[i] = NULL; 299 } 300 301 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 302 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 303 adev->uvd.address_64_bit = true; 304 305 switch (adev->asic_type) { 306 case CHIP_TONGA: 307 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 308 break; 309 case CHIP_CARRIZO: 310 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 311 break; 312 case CHIP_FIJI: 313 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 314 break; 315 case CHIP_STONEY: 316 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 317 break; 318 default: 319 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 320 } 321 322 return 0; 323 } 324 325 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 326 { 327 int i, j; 328 329 drm_sched_entity_destroy(&adev->uvd.entity); 330 331 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 332 if (adev->uvd.harvest_config & (1 << j)) 333 continue; 334 kvfree(adev->uvd.inst[j].saved_bo); 335 336 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 337 &adev->uvd.inst[j].gpu_addr, 338 (void **)&adev->uvd.inst[j].cpu_addr); 339 340 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 341 342 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 343 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 344 } 345 release_firmware(adev->uvd.fw); 346 347 return 0; 348 } 349 350 /** 351 * amdgpu_uvd_entity_init - init entity 352 * 353 * @adev: amdgpu_device pointer 354 * 355 */ 356 int amdgpu_uvd_entity_init(struct amdgpu_device *adev) 357 { 358 struct amdgpu_ring *ring; 359 struct drm_gpu_scheduler *sched; 360 int r; 361 362 ring = &adev->uvd.inst[0].ring; 363 sched = &ring->sched; 364 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 365 &sched, 1, NULL); 366 if (r) { 367 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 368 return r; 369 } 370 371 return 0; 372 } 373 374 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 375 { 376 unsigned size; 377 void *ptr; 378 int i, j, idx; 379 bool in_ras_intr = amdgpu_ras_intr_triggered(); 380 381 cancel_delayed_work_sync(&adev->uvd.idle_work); 382 383 /* only valid for physical mode */ 384 if (adev->asic_type < CHIP_POLARIS10) { 385 for (i = 0; i < adev->uvd.max_handles; ++i) 386 if (atomic_read(&adev->uvd.handles[i])) 387 break; 388 389 if (i == adev->uvd.max_handles) 390 return 0; 391 } 392 393 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 394 if (adev->uvd.harvest_config & (1 << j)) 395 continue; 396 if (adev->uvd.inst[j].vcpu_bo == NULL) 397 continue; 398 399 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 400 ptr = adev->uvd.inst[j].cpu_addr; 401 402 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 403 if (!adev->uvd.inst[j].saved_bo) 404 return -ENOMEM; 405 406 if (drm_dev_enter(&adev->ddev, &idx)) { 407 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 408 if (in_ras_intr) 409 memset(adev->uvd.inst[j].saved_bo, 0, size); 410 else 411 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 412 413 drm_dev_exit(idx); 414 } 415 } 416 417 if (in_ras_intr) 418 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 419 420 return 0; 421 } 422 423 int amdgpu_uvd_resume(struct amdgpu_device *adev) 424 { 425 unsigned size; 426 void *ptr; 427 int i, idx; 428 429 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 430 if (adev->uvd.harvest_config & (1 << i)) 431 continue; 432 if (adev->uvd.inst[i].vcpu_bo == NULL) 433 return -EINVAL; 434 435 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 436 ptr = adev->uvd.inst[i].cpu_addr; 437 438 if (adev->uvd.inst[i].saved_bo != NULL) { 439 if (drm_dev_enter(&adev->ddev, &idx)) { 440 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 441 drm_dev_exit(idx); 442 } 443 kvfree(adev->uvd.inst[i].saved_bo); 444 adev->uvd.inst[i].saved_bo = NULL; 445 } else { 446 const struct common_firmware_header *hdr; 447 unsigned offset; 448 449 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 450 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 451 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 452 if (drm_dev_enter(&adev->ddev, &idx)) { 453 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 454 le32_to_cpu(hdr->ucode_size_bytes)); 455 drm_dev_exit(idx); 456 } 457 size -= le32_to_cpu(hdr->ucode_size_bytes); 458 ptr += le32_to_cpu(hdr->ucode_size_bytes); 459 } 460 memset_io(ptr, 0, size); 461 /* to restore uvd fence seq */ 462 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); 463 } 464 } 465 return 0; 466 } 467 468 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 469 { 470 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 471 int i, r; 472 473 for (i = 0; i < adev->uvd.max_handles; ++i) { 474 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 475 476 if (handle != 0 && adev->uvd.filp[i] == filp) { 477 struct dma_fence *fence; 478 479 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 480 &fence); 481 if (r) { 482 DRM_ERROR("Error destroying UVD %d!\n", r); 483 continue; 484 } 485 486 dma_fence_wait(fence, false); 487 dma_fence_put(fence); 488 489 adev->uvd.filp[i] = NULL; 490 atomic_set(&adev->uvd.handles[i], 0); 491 } 492 } 493 } 494 495 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 496 { 497 int i; 498 for (i = 0; i < abo->placement.num_placement; ++i) { 499 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 500 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 501 } 502 } 503 504 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 505 { 506 uint32_t lo, hi; 507 uint64_t addr; 508 509 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 510 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 511 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 512 513 return addr; 514 } 515 516 /** 517 * amdgpu_uvd_cs_pass1 - first parsing round 518 * 519 * @ctx: UVD parser context 520 * 521 * Make sure UVD message and feedback buffers are in VRAM and 522 * nobody is violating an 256MB boundary. 523 */ 524 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 525 { 526 struct ttm_operation_ctx tctx = { false, false }; 527 struct amdgpu_bo_va_mapping *mapping; 528 struct amdgpu_bo *bo; 529 uint32_t cmd; 530 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 531 int r = 0; 532 533 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 534 if (r) { 535 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 536 return r; 537 } 538 539 if (!ctx->parser->adev->uvd.address_64_bit) { 540 /* check if it's a message or feedback command */ 541 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 542 if (cmd == 0x0 || cmd == 0x3) { 543 /* yes, force it into VRAM */ 544 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 545 amdgpu_bo_placement_from_domain(bo, domain); 546 } 547 amdgpu_uvd_force_into_uvd_segment(bo); 548 549 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 550 } 551 552 return r; 553 } 554 555 /** 556 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 557 * 558 * @adev: amdgpu_device pointer 559 * @msg: pointer to message structure 560 * @buf_sizes: placeholder to put the different buffer lengths 561 * 562 * Peek into the decode message and calculate the necessary buffer sizes. 563 */ 564 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 565 unsigned buf_sizes[]) 566 { 567 unsigned stream_type = msg[4]; 568 unsigned width = msg[6]; 569 unsigned height = msg[7]; 570 unsigned dpb_size = msg[9]; 571 unsigned pitch = msg[28]; 572 unsigned level = msg[57]; 573 574 unsigned width_in_mb = width / 16; 575 unsigned height_in_mb = ALIGN(height / 16, 2); 576 unsigned fs_in_mb = width_in_mb * height_in_mb; 577 578 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 579 unsigned min_ctx_size = ~0; 580 581 image_size = width * height; 582 image_size += image_size / 2; 583 image_size = ALIGN(image_size, 1024); 584 585 switch (stream_type) { 586 case 0: /* H264 */ 587 switch(level) { 588 case 30: 589 num_dpb_buffer = 8100 / fs_in_mb; 590 break; 591 case 31: 592 num_dpb_buffer = 18000 / fs_in_mb; 593 break; 594 case 32: 595 num_dpb_buffer = 20480 / fs_in_mb; 596 break; 597 case 41: 598 num_dpb_buffer = 32768 / fs_in_mb; 599 break; 600 case 42: 601 num_dpb_buffer = 34816 / fs_in_mb; 602 break; 603 case 50: 604 num_dpb_buffer = 110400 / fs_in_mb; 605 break; 606 case 51: 607 num_dpb_buffer = 184320 / fs_in_mb; 608 break; 609 default: 610 num_dpb_buffer = 184320 / fs_in_mb; 611 break; 612 } 613 num_dpb_buffer++; 614 if (num_dpb_buffer > 17) 615 num_dpb_buffer = 17; 616 617 /* reference picture buffer */ 618 min_dpb_size = image_size * num_dpb_buffer; 619 620 /* macroblock context buffer */ 621 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 622 623 /* IT surface buffer */ 624 min_dpb_size += width_in_mb * height_in_mb * 32; 625 break; 626 627 case 1: /* VC1 */ 628 629 /* reference picture buffer */ 630 min_dpb_size = image_size * 3; 631 632 /* CONTEXT_BUFFER */ 633 min_dpb_size += width_in_mb * height_in_mb * 128; 634 635 /* IT surface buffer */ 636 min_dpb_size += width_in_mb * 64; 637 638 /* DB surface buffer */ 639 min_dpb_size += width_in_mb * 128; 640 641 /* BP */ 642 tmp = max(width_in_mb, height_in_mb); 643 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 644 break; 645 646 case 3: /* MPEG2 */ 647 648 /* reference picture buffer */ 649 min_dpb_size = image_size * 3; 650 break; 651 652 case 4: /* MPEG4 */ 653 654 /* reference picture buffer */ 655 min_dpb_size = image_size * 3; 656 657 /* CM */ 658 min_dpb_size += width_in_mb * height_in_mb * 64; 659 660 /* IT surface buffer */ 661 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 662 break; 663 664 case 7: /* H264 Perf */ 665 switch(level) { 666 case 30: 667 num_dpb_buffer = 8100 / fs_in_mb; 668 break; 669 case 31: 670 num_dpb_buffer = 18000 / fs_in_mb; 671 break; 672 case 32: 673 num_dpb_buffer = 20480 / fs_in_mb; 674 break; 675 case 41: 676 num_dpb_buffer = 32768 / fs_in_mb; 677 break; 678 case 42: 679 num_dpb_buffer = 34816 / fs_in_mb; 680 break; 681 case 50: 682 num_dpb_buffer = 110400 / fs_in_mb; 683 break; 684 case 51: 685 num_dpb_buffer = 184320 / fs_in_mb; 686 break; 687 default: 688 num_dpb_buffer = 184320 / fs_in_mb; 689 break; 690 } 691 num_dpb_buffer++; 692 if (num_dpb_buffer > 17) 693 num_dpb_buffer = 17; 694 695 /* reference picture buffer */ 696 min_dpb_size = image_size * num_dpb_buffer; 697 698 if (!adev->uvd.use_ctx_buf){ 699 /* macroblock context buffer */ 700 min_dpb_size += 701 width_in_mb * height_in_mb * num_dpb_buffer * 192; 702 703 /* IT surface buffer */ 704 min_dpb_size += width_in_mb * height_in_mb * 32; 705 } else { 706 /* macroblock context buffer */ 707 min_ctx_size = 708 width_in_mb * height_in_mb * num_dpb_buffer * 192; 709 } 710 break; 711 712 case 8: /* MJPEG */ 713 min_dpb_size = 0; 714 break; 715 716 case 16: /* H265 */ 717 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 718 image_size = ALIGN(image_size, 256); 719 720 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 721 min_dpb_size = image_size * num_dpb_buffer; 722 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 723 * 16 * num_dpb_buffer + 52 * 1024; 724 break; 725 726 default: 727 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 728 return -EINVAL; 729 } 730 731 if (width > pitch) { 732 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 733 return -EINVAL; 734 } 735 736 if (dpb_size < min_dpb_size) { 737 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 738 dpb_size, min_dpb_size); 739 return -EINVAL; 740 } 741 742 buf_sizes[0x1] = dpb_size; 743 buf_sizes[0x2] = image_size; 744 buf_sizes[0x4] = min_ctx_size; 745 /* store image width to adjust nb memory pstate */ 746 adev->uvd.decode_image_width = width; 747 return 0; 748 } 749 750 /** 751 * amdgpu_uvd_cs_msg - handle UVD message 752 * 753 * @ctx: UVD parser context 754 * @bo: buffer object containing the message 755 * @offset: offset into the buffer object 756 * 757 * Peek into the UVD message and extract the session id. 758 * Make sure that we don't open up to many sessions. 759 */ 760 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 761 struct amdgpu_bo *bo, unsigned offset) 762 { 763 struct amdgpu_device *adev = ctx->parser->adev; 764 int32_t *msg, msg_type, handle; 765 void *ptr; 766 long r; 767 int i; 768 769 if (offset & 0x3F) { 770 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 771 return -EINVAL; 772 } 773 774 r = amdgpu_bo_kmap(bo, &ptr); 775 if (r) { 776 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 777 return r; 778 } 779 780 msg = ptr + offset; 781 782 msg_type = msg[1]; 783 handle = msg[2]; 784 785 if (handle == 0) { 786 DRM_ERROR("Invalid UVD handle!\n"); 787 return -EINVAL; 788 } 789 790 switch (msg_type) { 791 case 0: 792 /* it's a create msg, calc image size (width * height) */ 793 amdgpu_bo_kunmap(bo); 794 795 /* try to alloc a new handle */ 796 for (i = 0; i < adev->uvd.max_handles; ++i) { 797 if (atomic_read(&adev->uvd.handles[i]) == handle) { 798 DRM_ERROR(")Handle 0x%x already in use!\n", 799 handle); 800 return -EINVAL; 801 } 802 803 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 804 adev->uvd.filp[i] = ctx->parser->filp; 805 return 0; 806 } 807 } 808 809 DRM_ERROR("No more free UVD handles!\n"); 810 return -ENOSPC; 811 812 case 1: 813 /* it's a decode msg, calc buffer sizes */ 814 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 815 amdgpu_bo_kunmap(bo); 816 if (r) 817 return r; 818 819 /* validate the handle */ 820 for (i = 0; i < adev->uvd.max_handles; ++i) { 821 if (atomic_read(&adev->uvd.handles[i]) == handle) { 822 if (adev->uvd.filp[i] != ctx->parser->filp) { 823 DRM_ERROR("UVD handle collision detected!\n"); 824 return -EINVAL; 825 } 826 return 0; 827 } 828 } 829 830 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 831 return -ENOENT; 832 833 case 2: 834 /* it's a destroy msg, free the handle */ 835 for (i = 0; i < adev->uvd.max_handles; ++i) 836 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 837 amdgpu_bo_kunmap(bo); 838 return 0; 839 840 default: 841 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 842 } 843 844 return -EINVAL; 845 } 846 847 /** 848 * amdgpu_uvd_cs_pass2 - second parsing round 849 * 850 * @ctx: UVD parser context 851 * 852 * Patch buffer addresses, make sure buffer sizes are correct. 853 */ 854 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 855 { 856 struct amdgpu_bo_va_mapping *mapping; 857 struct amdgpu_bo *bo; 858 uint32_t cmd; 859 uint64_t start, end; 860 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 861 int r; 862 863 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 864 if (r) { 865 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 866 return r; 867 } 868 869 start = amdgpu_bo_gpu_offset(bo); 870 871 end = (mapping->last + 1 - mapping->start); 872 end = end * AMDGPU_GPU_PAGE_SIZE + start; 873 874 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 875 start += addr; 876 877 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 878 lower_32_bits(start)); 879 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 880 upper_32_bits(start)); 881 882 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 883 if (cmd < 0x4) { 884 if ((end - start) < ctx->buf_sizes[cmd]) { 885 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 886 (unsigned)(end - start), 887 ctx->buf_sizes[cmd]); 888 return -EINVAL; 889 } 890 891 } else if (cmd == 0x206) { 892 if ((end - start) < ctx->buf_sizes[4]) { 893 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 894 (unsigned)(end - start), 895 ctx->buf_sizes[4]); 896 return -EINVAL; 897 } 898 } else if ((cmd != 0x100) && (cmd != 0x204)) { 899 DRM_ERROR("invalid UVD command %X!\n", cmd); 900 return -EINVAL; 901 } 902 903 if (!ctx->parser->adev->uvd.address_64_bit) { 904 if ((start >> 28) != ((end - 1) >> 28)) { 905 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 906 start, end); 907 return -EINVAL; 908 } 909 910 if ((cmd == 0 || cmd == 0x3) && 911 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 912 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 913 start, end); 914 return -EINVAL; 915 } 916 } 917 918 if (cmd == 0) { 919 ctx->has_msg_cmd = true; 920 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 921 if (r) 922 return r; 923 } else if (!ctx->has_msg_cmd) { 924 DRM_ERROR("Message needed before other commands are send!\n"); 925 return -EINVAL; 926 } 927 928 return 0; 929 } 930 931 /** 932 * amdgpu_uvd_cs_reg - parse register writes 933 * 934 * @ctx: UVD parser context 935 * @cb: callback function 936 * 937 * Parse the register writes, call cb on each complete command. 938 */ 939 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 940 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 941 { 942 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 943 int i, r; 944 945 ctx->idx++; 946 for (i = 0; i <= ctx->count; ++i) { 947 unsigned reg = ctx->reg + i; 948 949 if (ctx->idx >= ib->length_dw) { 950 DRM_ERROR("Register command after end of CS!\n"); 951 return -EINVAL; 952 } 953 954 switch (reg) { 955 case mmUVD_GPCOM_VCPU_DATA0: 956 ctx->data0 = ctx->idx; 957 break; 958 case mmUVD_GPCOM_VCPU_DATA1: 959 ctx->data1 = ctx->idx; 960 break; 961 case mmUVD_GPCOM_VCPU_CMD: 962 r = cb(ctx); 963 if (r) 964 return r; 965 break; 966 case mmUVD_ENGINE_CNTL: 967 case mmUVD_NO_OP: 968 break; 969 default: 970 DRM_ERROR("Invalid reg 0x%X!\n", reg); 971 return -EINVAL; 972 } 973 ctx->idx++; 974 } 975 return 0; 976 } 977 978 /** 979 * amdgpu_uvd_cs_packets - parse UVD packets 980 * 981 * @ctx: UVD parser context 982 * @cb: callback function 983 * 984 * Parse the command stream packets. 985 */ 986 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 987 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 988 { 989 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 990 int r; 991 992 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 993 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 994 unsigned type = CP_PACKET_GET_TYPE(cmd); 995 switch (type) { 996 case PACKET_TYPE0: 997 ctx->reg = CP_PACKET0_GET_REG(cmd); 998 ctx->count = CP_PACKET_GET_COUNT(cmd); 999 r = amdgpu_uvd_cs_reg(ctx, cb); 1000 if (r) 1001 return r; 1002 break; 1003 case PACKET_TYPE2: 1004 ++ctx->idx; 1005 break; 1006 default: 1007 DRM_ERROR("Unknown packet type %d !\n", type); 1008 return -EINVAL; 1009 } 1010 } 1011 return 0; 1012 } 1013 1014 /** 1015 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 1016 * 1017 * @parser: Command submission parser context 1018 * @ib_idx: Which indirect buffer to use 1019 * 1020 * Parse the command stream, patch in addresses as necessary. 1021 */ 1022 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 1023 { 1024 struct amdgpu_uvd_cs_ctx ctx = {}; 1025 unsigned buf_sizes[] = { 1026 [0x00000000] = 2048, 1027 [0x00000001] = 0xFFFFFFFF, 1028 [0x00000002] = 0xFFFFFFFF, 1029 [0x00000003] = 2048, 1030 [0x00000004] = 0xFFFFFFFF, 1031 }; 1032 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 1033 int r; 1034 1035 parser->job->vm = NULL; 1036 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 1037 1038 if (ib->length_dw % 16) { 1039 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1040 ib->length_dw); 1041 return -EINVAL; 1042 } 1043 1044 ctx.parser = parser; 1045 ctx.buf_sizes = buf_sizes; 1046 ctx.ib_idx = ib_idx; 1047 1048 /* first round only required on chips without UVD 64 bit address support */ 1049 if (!parser->adev->uvd.address_64_bit) { 1050 /* first round, make sure the buffers are actually in the UVD segment */ 1051 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1052 if (r) 1053 return r; 1054 } 1055 1056 /* second round, patch buffer addresses into the command stream */ 1057 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1058 if (r) 1059 return r; 1060 1061 if (!ctx.has_msg_cmd) { 1062 DRM_ERROR("UVD-IBs need a msg command!\n"); 1063 return -EINVAL; 1064 } 1065 1066 return 0; 1067 } 1068 1069 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1070 bool direct, struct dma_fence **fence) 1071 { 1072 struct amdgpu_device *adev = ring->adev; 1073 struct dma_fence *f = NULL; 1074 struct amdgpu_job *job; 1075 struct amdgpu_ib *ib; 1076 uint32_t data[4]; 1077 uint64_t addr; 1078 long r; 1079 int i; 1080 unsigned offset_idx = 0; 1081 unsigned offset[3] = { UVD_BASE_SI, 0, 0 }; 1082 1083 amdgpu_bo_kunmap(bo); 1084 amdgpu_bo_unpin(bo); 1085 1086 if (!ring->adev->uvd.address_64_bit) { 1087 struct ttm_operation_ctx ctx = { true, false }; 1088 1089 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 1090 amdgpu_uvd_force_into_uvd_segment(bo); 1091 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1092 if (r) 1093 goto err; 1094 } 1095 1096 r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT : 1097 AMDGPU_IB_POOL_DELAYED, &job); 1098 if (r) 1099 goto err; 1100 1101 if (adev->asic_type >= CHIP_VEGA10) { 1102 offset_idx = 1 + ring->me; 1103 offset[1] = adev->reg_offset[UVD_HWIP][0][1]; 1104 offset[2] = adev->reg_offset[UVD_HWIP][1][1]; 1105 } 1106 1107 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0); 1108 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0); 1109 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0); 1110 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); 1111 1112 ib = &job->ibs[0]; 1113 addr = amdgpu_bo_gpu_offset(bo); 1114 ib->ptr[0] = data[0]; 1115 ib->ptr[1] = addr; 1116 ib->ptr[2] = data[1]; 1117 ib->ptr[3] = addr >> 32; 1118 ib->ptr[4] = data[2]; 1119 ib->ptr[5] = 0; 1120 for (i = 6; i < 16; i += 2) { 1121 ib->ptr[i] = data[3]; 1122 ib->ptr[i+1] = 0; 1123 } 1124 ib->length_dw = 16; 1125 1126 if (direct) { 1127 r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false, 1128 msecs_to_jiffies(10)); 1129 if (r == 0) 1130 r = -ETIMEDOUT; 1131 if (r < 0) 1132 goto err_free; 1133 1134 r = amdgpu_job_submit_direct(job, ring, &f); 1135 if (r) 1136 goto err_free; 1137 } else { 1138 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv, 1139 AMDGPU_SYNC_ALWAYS, 1140 AMDGPU_FENCE_OWNER_UNDEFINED); 1141 if (r) 1142 goto err_free; 1143 1144 r = amdgpu_job_submit(job, &adev->uvd.entity, 1145 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1146 if (r) 1147 goto err_free; 1148 } 1149 1150 amdgpu_bo_fence(bo, f, false); 1151 amdgpu_bo_unreserve(bo); 1152 amdgpu_bo_unref(&bo); 1153 1154 if (fence) 1155 *fence = dma_fence_get(f); 1156 dma_fence_put(f); 1157 1158 return 0; 1159 1160 err_free: 1161 amdgpu_job_free(job); 1162 1163 err: 1164 amdgpu_bo_unreserve(bo); 1165 amdgpu_bo_unref(&bo); 1166 return r; 1167 } 1168 1169 /* multiple fence commands without any stream commands in between can 1170 crash the vcpu so just try to emmit a dummy create/destroy msg to 1171 avoid this */ 1172 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1173 struct dma_fence **fence) 1174 { 1175 struct amdgpu_device *adev = ring->adev; 1176 struct amdgpu_bo *bo = NULL; 1177 uint32_t *msg; 1178 int r, i; 1179 1180 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1181 AMDGPU_GEM_DOMAIN_GTT, 1182 &bo, NULL, (void **)&msg); 1183 if (r) 1184 return r; 1185 1186 /* stitch together an UVD create msg */ 1187 msg[0] = cpu_to_le32(0x00000de4); 1188 msg[1] = cpu_to_le32(0x00000000); 1189 msg[2] = cpu_to_le32(handle); 1190 msg[3] = cpu_to_le32(0x00000000); 1191 msg[4] = cpu_to_le32(0x00000000); 1192 msg[5] = cpu_to_le32(0x00000000); 1193 msg[6] = cpu_to_le32(0x00000000); 1194 msg[7] = cpu_to_le32(0x00000780); 1195 msg[8] = cpu_to_le32(0x00000440); 1196 msg[9] = cpu_to_le32(0x00000000); 1197 msg[10] = cpu_to_le32(0x01b37000); 1198 for (i = 11; i < 1024; ++i) 1199 msg[i] = cpu_to_le32(0x0); 1200 1201 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1202 } 1203 1204 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1205 bool direct, struct dma_fence **fence) 1206 { 1207 struct amdgpu_device *adev = ring->adev; 1208 struct amdgpu_bo *bo = NULL; 1209 uint32_t *msg; 1210 int r, i; 1211 1212 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1213 AMDGPU_GEM_DOMAIN_GTT, 1214 &bo, NULL, (void **)&msg); 1215 if (r) 1216 return r; 1217 1218 /* stitch together an UVD destroy msg */ 1219 msg[0] = cpu_to_le32(0x00000de4); 1220 msg[1] = cpu_to_le32(0x00000002); 1221 msg[2] = cpu_to_le32(handle); 1222 msg[3] = cpu_to_le32(0x00000000); 1223 for (i = 4; i < 1024; ++i) 1224 msg[i] = cpu_to_le32(0x0); 1225 1226 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1227 } 1228 1229 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1230 { 1231 struct amdgpu_device *adev = 1232 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1233 unsigned fences = 0, i, j; 1234 1235 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1236 if (adev->uvd.harvest_config & (1 << i)) 1237 continue; 1238 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1239 for (j = 0; j < adev->uvd.num_enc_rings; ++j) { 1240 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1241 } 1242 } 1243 1244 if (fences == 0) { 1245 if (adev->pm.dpm_enabled) { 1246 amdgpu_dpm_enable_uvd(adev, false); 1247 } else { 1248 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1249 /* shutdown the UVD block */ 1250 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1251 AMD_PG_STATE_GATE); 1252 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1253 AMD_CG_STATE_GATE); 1254 } 1255 } else { 1256 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1257 } 1258 } 1259 1260 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1261 { 1262 struct amdgpu_device *adev = ring->adev; 1263 bool set_clocks; 1264 1265 if (amdgpu_sriov_vf(adev)) 1266 return; 1267 1268 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1269 if (set_clocks) { 1270 if (adev->pm.dpm_enabled) { 1271 amdgpu_dpm_enable_uvd(adev, true); 1272 } else { 1273 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1274 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1275 AMD_CG_STATE_UNGATE); 1276 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1277 AMD_PG_STATE_UNGATE); 1278 } 1279 } 1280 } 1281 1282 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1283 { 1284 if (!amdgpu_sriov_vf(ring->adev)) 1285 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1286 } 1287 1288 /** 1289 * amdgpu_uvd_ring_test_ib - test ib execution 1290 * 1291 * @ring: amdgpu_ring pointer 1292 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1293 * 1294 * Test if we can successfully execute an IB 1295 */ 1296 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1297 { 1298 struct dma_fence *fence; 1299 long r; 1300 1301 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1302 if (r) 1303 goto error; 1304 1305 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1306 if (r) 1307 goto error; 1308 1309 r = dma_fence_wait_timeout(fence, false, timeout); 1310 if (r == 0) 1311 r = -ETIMEDOUT; 1312 else if (r > 0) 1313 r = 0; 1314 1315 dma_fence_put(fence); 1316 1317 error: 1318 return r; 1319 } 1320 1321 /** 1322 * amdgpu_uvd_used_handles - returns used UVD handles 1323 * 1324 * @adev: amdgpu_device pointer 1325 * 1326 * Returns the number of UVD handles in use 1327 */ 1328 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1329 { 1330 unsigned i; 1331 uint32_t used_handles = 0; 1332 1333 for (i = 0; i < adev->uvd.max_handles; ++i) { 1334 /* 1335 * Handles can be freed in any order, and not 1336 * necessarily linear. So we need to count 1337 * all non-zero handles. 1338 */ 1339 if (atomic_read(&adev->uvd.handles[i])) 1340 used_handles++; 1341 } 1342 1343 return used_handles; 1344 } 1345