1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Christian König <deathsimple@vodafone.de>
29  */
30 
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 
34 #include <drm/drm.h>
35 
36 #include "amdgpu.h"
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
39 #include "cikd.h"
40 #include "uvd/uvd_4_2_d.h"
41 
42 #include "amdgpu_ras.h"
43 
44 /* 1 second timeout */
45 #define UVD_IDLE_TIMEOUT	msecs_to_jiffies(1000)
46 
47 /* Firmware versions for VI */
48 #define FW_1_65_10	((1 << 24) | (65 << 16) | (10 << 8))
49 #define FW_1_87_11	((1 << 24) | (87 << 16) | (11 << 8))
50 #define FW_1_87_12	((1 << 24) | (87 << 16) | (12 << 8))
51 #define FW_1_37_15	((1 << 24) | (37 << 16) | (15 << 8))
52 
53 /* Polaris10/11 firmware version */
54 #define FW_1_66_16	((1 << 24) | (66 << 16) | (16 << 8))
55 
56 /* Firmware Names */
57 #ifdef CONFIG_DRM_AMDGPU_SI
58 #define FIRMWARE_TAHITI		"amdgpu/tahiti_uvd.bin"
59 #define FIRMWARE_VERDE		"amdgpu/verde_uvd.bin"
60 #define FIRMWARE_PITCAIRN	"amdgpu/pitcairn_uvd.bin"
61 #define FIRMWARE_OLAND		"amdgpu/oland_uvd.bin"
62 #endif
63 #ifdef CONFIG_DRM_AMDGPU_CIK
64 #define FIRMWARE_BONAIRE	"amdgpu/bonaire_uvd.bin"
65 #define FIRMWARE_KABINI	"amdgpu/kabini_uvd.bin"
66 #define FIRMWARE_KAVERI	"amdgpu/kaveri_uvd.bin"
67 #define FIRMWARE_HAWAII	"amdgpu/hawaii_uvd.bin"
68 #define FIRMWARE_MULLINS	"amdgpu/mullins_uvd.bin"
69 #endif
70 #define FIRMWARE_TONGA		"amdgpu/tonga_uvd.bin"
71 #define FIRMWARE_CARRIZO	"amdgpu/carrizo_uvd.bin"
72 #define FIRMWARE_FIJI		"amdgpu/fiji_uvd.bin"
73 #define FIRMWARE_STONEY		"amdgpu/stoney_uvd.bin"
74 #define FIRMWARE_POLARIS10	"amdgpu/polaris10_uvd.bin"
75 #define FIRMWARE_POLARIS11	"amdgpu/polaris11_uvd.bin"
76 #define FIRMWARE_POLARIS12	"amdgpu/polaris12_uvd.bin"
77 #define FIRMWARE_VEGAM		"amdgpu/vegam_uvd.bin"
78 
79 #define FIRMWARE_VEGA10		"amdgpu/vega10_uvd.bin"
80 #define FIRMWARE_VEGA12		"amdgpu/vega12_uvd.bin"
81 #define FIRMWARE_VEGA20		"amdgpu/vega20_uvd.bin"
82 
83 /* These are common relative offsets for all asics, from uvd_7_0_offset.h,  */
84 #define UVD_GPCOM_VCPU_CMD		0x03c3
85 #define UVD_GPCOM_VCPU_DATA0	0x03c4
86 #define UVD_GPCOM_VCPU_DATA1	0x03c5
87 #define UVD_NO_OP				0x03ff
88 #define UVD_BASE_SI				0x3800
89 
90 /*
91  * amdgpu_uvd_cs_ctx - Command submission parser context
92  *
93  * Used for emulating virtual memory support on UVD 4.2.
94  */
95 struct amdgpu_uvd_cs_ctx {
96 	struct amdgpu_cs_parser *parser;
97 	unsigned reg, count;
98 	unsigned data0, data1;
99 	unsigned idx;
100 	unsigned ib_idx;
101 
102 	/* does the IB has a msg command */
103 	bool has_msg_cmd;
104 
105 	/* minimum buffer sizes */
106 	unsigned *buf_sizes;
107 };
108 
109 #ifdef CONFIG_DRM_AMDGPU_SI
110 MODULE_FIRMWARE(FIRMWARE_TAHITI);
111 MODULE_FIRMWARE(FIRMWARE_VERDE);
112 MODULE_FIRMWARE(FIRMWARE_PITCAIRN);
113 MODULE_FIRMWARE(FIRMWARE_OLAND);
114 #endif
115 #ifdef CONFIG_DRM_AMDGPU_CIK
116 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
117 MODULE_FIRMWARE(FIRMWARE_KABINI);
118 MODULE_FIRMWARE(FIRMWARE_KAVERI);
119 MODULE_FIRMWARE(FIRMWARE_HAWAII);
120 MODULE_FIRMWARE(FIRMWARE_MULLINS);
121 #endif
122 MODULE_FIRMWARE(FIRMWARE_TONGA);
123 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
124 MODULE_FIRMWARE(FIRMWARE_FIJI);
125 MODULE_FIRMWARE(FIRMWARE_STONEY);
126 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
127 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
128 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
129 MODULE_FIRMWARE(FIRMWARE_VEGAM);
130 
131 MODULE_FIRMWARE(FIRMWARE_VEGA10);
132 MODULE_FIRMWARE(FIRMWARE_VEGA12);
133 MODULE_FIRMWARE(FIRMWARE_VEGA20);
134 
135 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
136 
137 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
138 {
139 	unsigned long bo_size;
140 	const char *fw_name;
141 	const struct common_firmware_header *hdr;
142 	unsigned family_id;
143 	int i, j, r;
144 
145 	INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
146 
147 	switch (adev->asic_type) {
148 #ifdef CONFIG_DRM_AMDGPU_SI
149 	case CHIP_TAHITI:
150 		fw_name = FIRMWARE_TAHITI;
151 		break;
152 	case CHIP_VERDE:
153 		fw_name = FIRMWARE_VERDE;
154 		break;
155 	case CHIP_PITCAIRN:
156 		fw_name = FIRMWARE_PITCAIRN;
157 		break;
158 	case CHIP_OLAND:
159 		fw_name = FIRMWARE_OLAND;
160 		break;
161 #endif
162 #ifdef CONFIG_DRM_AMDGPU_CIK
163 	case CHIP_BONAIRE:
164 		fw_name = FIRMWARE_BONAIRE;
165 		break;
166 	case CHIP_KABINI:
167 		fw_name = FIRMWARE_KABINI;
168 		break;
169 	case CHIP_KAVERI:
170 		fw_name = FIRMWARE_KAVERI;
171 		break;
172 	case CHIP_HAWAII:
173 		fw_name = FIRMWARE_HAWAII;
174 		break;
175 	case CHIP_MULLINS:
176 		fw_name = FIRMWARE_MULLINS;
177 		break;
178 #endif
179 	case CHIP_TONGA:
180 		fw_name = FIRMWARE_TONGA;
181 		break;
182 	case CHIP_FIJI:
183 		fw_name = FIRMWARE_FIJI;
184 		break;
185 	case CHIP_CARRIZO:
186 		fw_name = FIRMWARE_CARRIZO;
187 		break;
188 	case CHIP_STONEY:
189 		fw_name = FIRMWARE_STONEY;
190 		break;
191 	case CHIP_POLARIS10:
192 		fw_name = FIRMWARE_POLARIS10;
193 		break;
194 	case CHIP_POLARIS11:
195 		fw_name = FIRMWARE_POLARIS11;
196 		break;
197 	case CHIP_POLARIS12:
198 		fw_name = FIRMWARE_POLARIS12;
199 		break;
200 	case CHIP_VEGA10:
201 		fw_name = FIRMWARE_VEGA10;
202 		break;
203 	case CHIP_VEGA12:
204 		fw_name = FIRMWARE_VEGA12;
205 		break;
206 	case CHIP_VEGAM:
207 		fw_name = FIRMWARE_VEGAM;
208 		break;
209 	case CHIP_VEGA20:
210 		fw_name = FIRMWARE_VEGA20;
211 		break;
212 	default:
213 		return -EINVAL;
214 	}
215 
216 	r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
217 	if (r) {
218 		dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
219 			fw_name);
220 		return r;
221 	}
222 
223 	r = amdgpu_ucode_validate(adev->uvd.fw);
224 	if (r) {
225 		dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
226 			fw_name);
227 		release_firmware(adev->uvd.fw);
228 		adev->uvd.fw = NULL;
229 		return r;
230 	}
231 
232 	/* Set the default UVD handles that the firmware can handle */
233 	adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
234 
235 	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
236 	family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
237 
238 	if (adev->asic_type < CHIP_VEGA20) {
239 		unsigned version_major, version_minor;
240 
241 		version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
242 		version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
243 		DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n",
244 			version_major, version_minor, family_id);
245 
246 		/*
247 		 * Limit the number of UVD handles depending on microcode major
248 		 * and minor versions. The firmware version which has 40 UVD
249 		 * instances support is 1.80. So all subsequent versions should
250 		 * also have the same support.
251 		 */
252 		if ((version_major > 0x01) ||
253 		    ((version_major == 0x01) && (version_minor >= 0x50)))
254 			adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
255 
256 		adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
257 					(family_id << 8));
258 
259 		if ((adev->asic_type == CHIP_POLARIS10 ||
260 		     adev->asic_type == CHIP_POLARIS11) &&
261 		    (adev->uvd.fw_version < FW_1_66_16))
262 			DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n",
263 				  version_major, version_minor);
264 	} else {
265 		unsigned int enc_major, enc_minor, dec_minor;
266 
267 		dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
268 		enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
269 		enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
270 		DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n",
271 			enc_major, enc_minor, dec_minor, family_id);
272 
273 		adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
274 
275 		adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
276 	}
277 
278 	bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
279 		  +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
280 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
281 		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
282 
283 	for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
284 		if (adev->uvd.harvest_config & (1 << j))
285 			continue;
286 		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
287 					    AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
288 					    &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
289 		if (r) {
290 			dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
291 			return r;
292 		}
293 	}
294 
295 	for (i = 0; i < adev->uvd.max_handles; ++i) {
296 		atomic_set(&adev->uvd.handles[i], 0);
297 		adev->uvd.filp[i] = NULL;
298 	}
299 
300 	/* from uvd v5.0 HW addressing capacity increased to 64 bits */
301 	if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
302 		adev->uvd.address_64_bit = true;
303 
304 	switch (adev->asic_type) {
305 	case CHIP_TONGA:
306 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
307 		break;
308 	case CHIP_CARRIZO:
309 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
310 		break;
311 	case CHIP_FIJI:
312 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
313 		break;
314 	case CHIP_STONEY:
315 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
316 		break;
317 	default:
318 		adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
319 	}
320 
321 	return 0;
322 }
323 
324 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
325 {
326 	int i, j;
327 
328 	cancel_delayed_work_sync(&adev->uvd.idle_work);
329 	drm_sched_entity_destroy(&adev->uvd.entity);
330 
331 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
332 		if (adev->uvd.harvest_config & (1 << j))
333 			continue;
334 		kvfree(adev->uvd.inst[j].saved_bo);
335 
336 		amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
337 				      &adev->uvd.inst[j].gpu_addr,
338 				      (void **)&adev->uvd.inst[j].cpu_addr);
339 
340 		amdgpu_ring_fini(&adev->uvd.inst[j].ring);
341 
342 		for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
343 			amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
344 	}
345 	release_firmware(adev->uvd.fw);
346 
347 	return 0;
348 }
349 
350 /**
351  * amdgpu_uvd_entity_init - init entity
352  *
353  * @adev: amdgpu_device pointer
354  *
355  */
356 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
357 {
358 	struct amdgpu_ring *ring;
359 	struct drm_gpu_scheduler *sched;
360 	int r;
361 
362 	ring = &adev->uvd.inst[0].ring;
363 	sched = &ring->sched;
364 	r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
365 				  &sched, 1, NULL);
366 	if (r) {
367 		DRM_ERROR("Failed setting up UVD kernel entity.\n");
368 		return r;
369 	}
370 
371 	return 0;
372 }
373 
374 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
375 {
376 	unsigned size;
377 	void *ptr;
378 	int i, j;
379 	bool in_ras_intr = amdgpu_ras_intr_triggered();
380 
381 	cancel_delayed_work_sync(&adev->uvd.idle_work);
382 
383 	/* only valid for physical mode */
384 	if (adev->asic_type < CHIP_POLARIS10) {
385 		for (i = 0; i < adev->uvd.max_handles; ++i)
386 			if (atomic_read(&adev->uvd.handles[i]))
387 				break;
388 
389 		if (i == adev->uvd.max_handles)
390 			return 0;
391 	}
392 
393 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
394 		if (adev->uvd.harvest_config & (1 << j))
395 			continue;
396 		if (adev->uvd.inst[j].vcpu_bo == NULL)
397 			continue;
398 
399 		size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
400 		ptr = adev->uvd.inst[j].cpu_addr;
401 
402 		adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);
403 		if (!adev->uvd.inst[j].saved_bo)
404 			return -ENOMEM;
405 
406 		/* re-write 0 since err_event_athub will corrupt VCPU buffer */
407 		if (in_ras_intr)
408 			memset(adev->uvd.inst[j].saved_bo, 0, size);
409 		else
410 			memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
411 	}
412 
413 	if (in_ras_intr)
414 		DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
415 
416 	return 0;
417 }
418 
419 int amdgpu_uvd_resume(struct amdgpu_device *adev)
420 {
421 	unsigned size;
422 	void *ptr;
423 	int i;
424 
425 	for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
426 		if (adev->uvd.harvest_config & (1 << i))
427 			continue;
428 		if (adev->uvd.inst[i].vcpu_bo == NULL)
429 			return -EINVAL;
430 
431 		size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
432 		ptr = adev->uvd.inst[i].cpu_addr;
433 
434 		if (adev->uvd.inst[i].saved_bo != NULL) {
435 			memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
436 			kvfree(adev->uvd.inst[i].saved_bo);
437 			adev->uvd.inst[i].saved_bo = NULL;
438 		} else {
439 			const struct common_firmware_header *hdr;
440 			unsigned offset;
441 
442 			hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
443 			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
444 				offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
445 				memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
446 					    le32_to_cpu(hdr->ucode_size_bytes));
447 				size -= le32_to_cpu(hdr->ucode_size_bytes);
448 				ptr += le32_to_cpu(hdr->ucode_size_bytes);
449 			}
450 			memset_io(ptr, 0, size);
451 			/* to restore uvd fence seq */
452 			amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
453 		}
454 	}
455 	return 0;
456 }
457 
458 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
459 {
460 	struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
461 	int i, r;
462 
463 	for (i = 0; i < adev->uvd.max_handles; ++i) {
464 		uint32_t handle = atomic_read(&adev->uvd.handles[i]);
465 
466 		if (handle != 0 && adev->uvd.filp[i] == filp) {
467 			struct dma_fence *fence;
468 
469 			r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
470 						       &fence);
471 			if (r) {
472 				DRM_ERROR("Error destroying UVD %d!\n", r);
473 				continue;
474 			}
475 
476 			dma_fence_wait(fence, false);
477 			dma_fence_put(fence);
478 
479 			adev->uvd.filp[i] = NULL;
480 			atomic_set(&adev->uvd.handles[i], 0);
481 		}
482 	}
483 }
484 
485 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
486 {
487 	int i;
488 	for (i = 0; i < abo->placement.num_placement; ++i) {
489 		abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
490 		abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
491 	}
492 }
493 
494 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
495 {
496 	uint32_t lo, hi;
497 	uint64_t addr;
498 
499 	lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
500 	hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
501 	addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
502 
503 	return addr;
504 }
505 
506 /**
507  * amdgpu_uvd_cs_pass1 - first parsing round
508  *
509  * @ctx: UVD parser context
510  *
511  * Make sure UVD message and feedback buffers are in VRAM and
512  * nobody is violating an 256MB boundary.
513  */
514 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
515 {
516 	struct ttm_operation_ctx tctx = { false, false };
517 	struct amdgpu_bo_va_mapping *mapping;
518 	struct amdgpu_bo *bo;
519 	uint32_t cmd;
520 	uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
521 	int r = 0;
522 
523 	r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
524 	if (r) {
525 		DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
526 		return r;
527 	}
528 
529 	if (!ctx->parser->adev->uvd.address_64_bit) {
530 		/* check if it's a message or feedback command */
531 		cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
532 		if (cmd == 0x0 || cmd == 0x3) {
533 			/* yes, force it into VRAM */
534 			uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
535 			amdgpu_bo_placement_from_domain(bo, domain);
536 		}
537 		amdgpu_uvd_force_into_uvd_segment(bo);
538 
539 		r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
540 	}
541 
542 	return r;
543 }
544 
545 /**
546  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
547  *
548  * @adev: amdgpu_device pointer
549  * @msg: pointer to message structure
550  * @buf_sizes: placeholder to put the different buffer lengths
551  *
552  * Peek into the decode message and calculate the necessary buffer sizes.
553  */
554 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
555 	unsigned buf_sizes[])
556 {
557 	unsigned stream_type = msg[4];
558 	unsigned width = msg[6];
559 	unsigned height = msg[7];
560 	unsigned dpb_size = msg[9];
561 	unsigned pitch = msg[28];
562 	unsigned level = msg[57];
563 
564 	unsigned width_in_mb = width / 16;
565 	unsigned height_in_mb = ALIGN(height / 16, 2);
566 	unsigned fs_in_mb = width_in_mb * height_in_mb;
567 
568 	unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
569 	unsigned min_ctx_size = ~0;
570 
571 	image_size = width * height;
572 	image_size += image_size / 2;
573 	image_size = ALIGN(image_size, 1024);
574 
575 	switch (stream_type) {
576 	case 0: /* H264 */
577 		switch(level) {
578 		case 30:
579 			num_dpb_buffer = 8100 / fs_in_mb;
580 			break;
581 		case 31:
582 			num_dpb_buffer = 18000 / fs_in_mb;
583 			break;
584 		case 32:
585 			num_dpb_buffer = 20480 / fs_in_mb;
586 			break;
587 		case 41:
588 			num_dpb_buffer = 32768 / fs_in_mb;
589 			break;
590 		case 42:
591 			num_dpb_buffer = 34816 / fs_in_mb;
592 			break;
593 		case 50:
594 			num_dpb_buffer = 110400 / fs_in_mb;
595 			break;
596 		case 51:
597 			num_dpb_buffer = 184320 / fs_in_mb;
598 			break;
599 		default:
600 			num_dpb_buffer = 184320 / fs_in_mb;
601 			break;
602 		}
603 		num_dpb_buffer++;
604 		if (num_dpb_buffer > 17)
605 			num_dpb_buffer = 17;
606 
607 		/* reference picture buffer */
608 		min_dpb_size = image_size * num_dpb_buffer;
609 
610 		/* macroblock context buffer */
611 		min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
612 
613 		/* IT surface buffer */
614 		min_dpb_size += width_in_mb * height_in_mb * 32;
615 		break;
616 
617 	case 1: /* VC1 */
618 
619 		/* reference picture buffer */
620 		min_dpb_size = image_size * 3;
621 
622 		/* CONTEXT_BUFFER */
623 		min_dpb_size += width_in_mb * height_in_mb * 128;
624 
625 		/* IT surface buffer */
626 		min_dpb_size += width_in_mb * 64;
627 
628 		/* DB surface buffer */
629 		min_dpb_size += width_in_mb * 128;
630 
631 		/* BP */
632 		tmp = max(width_in_mb, height_in_mb);
633 		min_dpb_size += ALIGN(tmp * 7 * 16, 64);
634 		break;
635 
636 	case 3: /* MPEG2 */
637 
638 		/* reference picture buffer */
639 		min_dpb_size = image_size * 3;
640 		break;
641 
642 	case 4: /* MPEG4 */
643 
644 		/* reference picture buffer */
645 		min_dpb_size = image_size * 3;
646 
647 		/* CM */
648 		min_dpb_size += width_in_mb * height_in_mb * 64;
649 
650 		/* IT surface buffer */
651 		min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
652 		break;
653 
654 	case 7: /* H264 Perf */
655 		switch(level) {
656 		case 30:
657 			num_dpb_buffer = 8100 / fs_in_mb;
658 			break;
659 		case 31:
660 			num_dpb_buffer = 18000 / fs_in_mb;
661 			break;
662 		case 32:
663 			num_dpb_buffer = 20480 / fs_in_mb;
664 			break;
665 		case 41:
666 			num_dpb_buffer = 32768 / fs_in_mb;
667 			break;
668 		case 42:
669 			num_dpb_buffer = 34816 / fs_in_mb;
670 			break;
671 		case 50:
672 			num_dpb_buffer = 110400 / fs_in_mb;
673 			break;
674 		case 51:
675 			num_dpb_buffer = 184320 / fs_in_mb;
676 			break;
677 		default:
678 			num_dpb_buffer = 184320 / fs_in_mb;
679 			break;
680 		}
681 		num_dpb_buffer++;
682 		if (num_dpb_buffer > 17)
683 			num_dpb_buffer = 17;
684 
685 		/* reference picture buffer */
686 		min_dpb_size = image_size * num_dpb_buffer;
687 
688 		if (!adev->uvd.use_ctx_buf){
689 			/* macroblock context buffer */
690 			min_dpb_size +=
691 				width_in_mb * height_in_mb * num_dpb_buffer * 192;
692 
693 			/* IT surface buffer */
694 			min_dpb_size += width_in_mb * height_in_mb * 32;
695 		} else {
696 			/* macroblock context buffer */
697 			min_ctx_size =
698 				width_in_mb * height_in_mb * num_dpb_buffer * 192;
699 		}
700 		break;
701 
702 	case 8: /* MJPEG */
703 		min_dpb_size = 0;
704 		break;
705 
706 	case 16: /* H265 */
707 		image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
708 		image_size = ALIGN(image_size, 256);
709 
710 		num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
711 		min_dpb_size = image_size * num_dpb_buffer;
712 		min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
713 					   * 16 * num_dpb_buffer + 52 * 1024;
714 		break;
715 
716 	default:
717 		DRM_ERROR("UVD codec not handled %d!\n", stream_type);
718 		return -EINVAL;
719 	}
720 
721 	if (width > pitch) {
722 		DRM_ERROR("Invalid UVD decoding target pitch!\n");
723 		return -EINVAL;
724 	}
725 
726 	if (dpb_size < min_dpb_size) {
727 		DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
728 			  dpb_size, min_dpb_size);
729 		return -EINVAL;
730 	}
731 
732 	buf_sizes[0x1] = dpb_size;
733 	buf_sizes[0x2] = image_size;
734 	buf_sizes[0x4] = min_ctx_size;
735 	/* store image width to adjust nb memory pstate */
736 	adev->uvd.decode_image_width = width;
737 	return 0;
738 }
739 
740 /**
741  * amdgpu_uvd_cs_msg - handle UVD message
742  *
743  * @ctx: UVD parser context
744  * @bo: buffer object containing the message
745  * @offset: offset into the buffer object
746  *
747  * Peek into the UVD message and extract the session id.
748  * Make sure that we don't open up to many sessions.
749  */
750 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
751 			     struct amdgpu_bo *bo, unsigned offset)
752 {
753 	struct amdgpu_device *adev = ctx->parser->adev;
754 	int32_t *msg, msg_type, handle;
755 	void *ptr;
756 	long r;
757 	int i;
758 
759 	if (offset & 0x3F) {
760 		DRM_ERROR("UVD messages must be 64 byte aligned!\n");
761 		return -EINVAL;
762 	}
763 
764 	r = amdgpu_bo_kmap(bo, &ptr);
765 	if (r) {
766 		DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
767 		return r;
768 	}
769 
770 	msg = ptr + offset;
771 
772 	msg_type = msg[1];
773 	handle = msg[2];
774 
775 	if (handle == 0) {
776 		DRM_ERROR("Invalid UVD handle!\n");
777 		return -EINVAL;
778 	}
779 
780 	switch (msg_type) {
781 	case 0:
782 		/* it's a create msg, calc image size (width * height) */
783 		amdgpu_bo_kunmap(bo);
784 
785 		/* try to alloc a new handle */
786 		for (i = 0; i < adev->uvd.max_handles; ++i) {
787 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
788 				DRM_ERROR(")Handle 0x%x already in use!\n",
789 					  handle);
790 				return -EINVAL;
791 			}
792 
793 			if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
794 				adev->uvd.filp[i] = ctx->parser->filp;
795 				return 0;
796 			}
797 		}
798 
799 		DRM_ERROR("No more free UVD handles!\n");
800 		return -ENOSPC;
801 
802 	case 1:
803 		/* it's a decode msg, calc buffer sizes */
804 		r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
805 		amdgpu_bo_kunmap(bo);
806 		if (r)
807 			return r;
808 
809 		/* validate the handle */
810 		for (i = 0; i < adev->uvd.max_handles; ++i) {
811 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
812 				if (adev->uvd.filp[i] != ctx->parser->filp) {
813 					DRM_ERROR("UVD handle collision detected!\n");
814 					return -EINVAL;
815 				}
816 				return 0;
817 			}
818 		}
819 
820 		DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
821 		return -ENOENT;
822 
823 	case 2:
824 		/* it's a destroy msg, free the handle */
825 		for (i = 0; i < adev->uvd.max_handles; ++i)
826 			atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
827 		amdgpu_bo_kunmap(bo);
828 		return 0;
829 
830 	default:
831 		DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
832 		return -EINVAL;
833 	}
834 	BUG();
835 	return -EINVAL;
836 }
837 
838 /**
839  * amdgpu_uvd_cs_pass2 - second parsing round
840  *
841  * @ctx: UVD parser context
842  *
843  * Patch buffer addresses, make sure buffer sizes are correct.
844  */
845 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
846 {
847 	struct amdgpu_bo_va_mapping *mapping;
848 	struct amdgpu_bo *bo;
849 	uint32_t cmd;
850 	uint64_t start, end;
851 	uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
852 	int r;
853 
854 	r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
855 	if (r) {
856 		DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
857 		return r;
858 	}
859 
860 	start = amdgpu_bo_gpu_offset(bo);
861 
862 	end = (mapping->last + 1 - mapping->start);
863 	end = end * AMDGPU_GPU_PAGE_SIZE + start;
864 
865 	addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
866 	start += addr;
867 
868 	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
869 			    lower_32_bits(start));
870 	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
871 			    upper_32_bits(start));
872 
873 	cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
874 	if (cmd < 0x4) {
875 		if ((end - start) < ctx->buf_sizes[cmd]) {
876 			DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
877 				  (unsigned)(end - start),
878 				  ctx->buf_sizes[cmd]);
879 			return -EINVAL;
880 		}
881 
882 	} else if (cmd == 0x206) {
883 		if ((end - start) < ctx->buf_sizes[4]) {
884 			DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
885 					  (unsigned)(end - start),
886 					  ctx->buf_sizes[4]);
887 			return -EINVAL;
888 		}
889 	} else if ((cmd != 0x100) && (cmd != 0x204)) {
890 		DRM_ERROR("invalid UVD command %X!\n", cmd);
891 		return -EINVAL;
892 	}
893 
894 	if (!ctx->parser->adev->uvd.address_64_bit) {
895 		if ((start >> 28) != ((end - 1) >> 28)) {
896 			DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
897 				  start, end);
898 			return -EINVAL;
899 		}
900 
901 		if ((cmd == 0 || cmd == 0x3) &&
902 		    (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
903 			DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
904 				  start, end);
905 			return -EINVAL;
906 		}
907 	}
908 
909 	if (cmd == 0) {
910 		ctx->has_msg_cmd = true;
911 		r = amdgpu_uvd_cs_msg(ctx, bo, addr);
912 		if (r)
913 			return r;
914 	} else if (!ctx->has_msg_cmd) {
915 		DRM_ERROR("Message needed before other commands are send!\n");
916 		return -EINVAL;
917 	}
918 
919 	return 0;
920 }
921 
922 /**
923  * amdgpu_uvd_cs_reg - parse register writes
924  *
925  * @ctx: UVD parser context
926  * @cb: callback function
927  *
928  * Parse the register writes, call cb on each complete command.
929  */
930 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
931 			     int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
932 {
933 	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
934 	int i, r;
935 
936 	ctx->idx++;
937 	for (i = 0; i <= ctx->count; ++i) {
938 		unsigned reg = ctx->reg + i;
939 
940 		if (ctx->idx >= ib->length_dw) {
941 			DRM_ERROR("Register command after end of CS!\n");
942 			return -EINVAL;
943 		}
944 
945 		switch (reg) {
946 		case mmUVD_GPCOM_VCPU_DATA0:
947 			ctx->data0 = ctx->idx;
948 			break;
949 		case mmUVD_GPCOM_VCPU_DATA1:
950 			ctx->data1 = ctx->idx;
951 			break;
952 		case mmUVD_GPCOM_VCPU_CMD:
953 			r = cb(ctx);
954 			if (r)
955 				return r;
956 			break;
957 		case mmUVD_ENGINE_CNTL:
958 		case mmUVD_NO_OP:
959 			break;
960 		default:
961 			DRM_ERROR("Invalid reg 0x%X!\n", reg);
962 			return -EINVAL;
963 		}
964 		ctx->idx++;
965 	}
966 	return 0;
967 }
968 
969 /**
970  * amdgpu_uvd_cs_packets - parse UVD packets
971  *
972  * @ctx: UVD parser context
973  * @cb: callback function
974  *
975  * Parse the command stream packets.
976  */
977 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
978 				 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
979 {
980 	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
981 	int r;
982 
983 	for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
984 		uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
985 		unsigned type = CP_PACKET_GET_TYPE(cmd);
986 		switch (type) {
987 		case PACKET_TYPE0:
988 			ctx->reg = CP_PACKET0_GET_REG(cmd);
989 			ctx->count = CP_PACKET_GET_COUNT(cmd);
990 			r = amdgpu_uvd_cs_reg(ctx, cb);
991 			if (r)
992 				return r;
993 			break;
994 		case PACKET_TYPE2:
995 			++ctx->idx;
996 			break;
997 		default:
998 			DRM_ERROR("Unknown packet type %d !\n", type);
999 			return -EINVAL;
1000 		}
1001 	}
1002 	return 0;
1003 }
1004 
1005 /**
1006  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
1007  *
1008  * @parser: Command submission parser context
1009  * @ib_idx: Which indirect buffer to use
1010  *
1011  * Parse the command stream, patch in addresses as necessary.
1012  */
1013 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
1014 {
1015 	struct amdgpu_uvd_cs_ctx ctx = {};
1016 	unsigned buf_sizes[] = {
1017 		[0x00000000]	=	2048,
1018 		[0x00000001]	=	0xFFFFFFFF,
1019 		[0x00000002]	=	0xFFFFFFFF,
1020 		[0x00000003]	=	2048,
1021 		[0x00000004]	=	0xFFFFFFFF,
1022 	};
1023 	struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
1024 	int r;
1025 
1026 	parser->job->vm = NULL;
1027 	ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
1028 
1029 	if (ib->length_dw % 16) {
1030 		DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
1031 			  ib->length_dw);
1032 		return -EINVAL;
1033 	}
1034 
1035 	ctx.parser = parser;
1036 	ctx.buf_sizes = buf_sizes;
1037 	ctx.ib_idx = ib_idx;
1038 
1039 	/* first round only required on chips without UVD 64 bit address support */
1040 	if (!parser->adev->uvd.address_64_bit) {
1041 		/* first round, make sure the buffers are actually in the UVD segment */
1042 		r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
1043 		if (r)
1044 			return r;
1045 	}
1046 
1047 	/* second round, patch buffer addresses into the command stream */
1048 	r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
1049 	if (r)
1050 		return r;
1051 
1052 	if (!ctx.has_msg_cmd) {
1053 		DRM_ERROR("UVD-IBs need a msg command!\n");
1054 		return -EINVAL;
1055 	}
1056 
1057 	return 0;
1058 }
1059 
1060 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
1061 			       bool direct, struct dma_fence **fence)
1062 {
1063 	struct amdgpu_device *adev = ring->adev;
1064 	struct dma_fence *f = NULL;
1065 	struct amdgpu_job *job;
1066 	struct amdgpu_ib *ib;
1067 	uint32_t data[4];
1068 	uint64_t addr;
1069 	long r;
1070 	int i;
1071 	unsigned offset_idx = 0;
1072 	unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
1073 
1074 	amdgpu_bo_kunmap(bo);
1075 	amdgpu_bo_unpin(bo);
1076 
1077 	if (!ring->adev->uvd.address_64_bit) {
1078 		struct ttm_operation_ctx ctx = { true, false };
1079 
1080 		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
1081 		amdgpu_uvd_force_into_uvd_segment(bo);
1082 		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1083 		if (r)
1084 			goto err;
1085 	}
1086 
1087 	r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT :
1088 				     AMDGPU_IB_POOL_DELAYED, &job);
1089 	if (r)
1090 		goto err;
1091 
1092 	if (adev->asic_type >= CHIP_VEGA10) {
1093 		offset_idx = 1 + ring->me;
1094 		offset[1] = adev->reg_offset[UVD_HWIP][0][1];
1095 		offset[2] = adev->reg_offset[UVD_HWIP][1][1];
1096 	}
1097 
1098 	data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1099 	data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1100 	data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1101 	data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
1102 
1103 	ib = &job->ibs[0];
1104 	addr = amdgpu_bo_gpu_offset(bo);
1105 	ib->ptr[0] = data[0];
1106 	ib->ptr[1] = addr;
1107 	ib->ptr[2] = data[1];
1108 	ib->ptr[3] = addr >> 32;
1109 	ib->ptr[4] = data[2];
1110 	ib->ptr[5] = 0;
1111 	for (i = 6; i < 16; i += 2) {
1112 		ib->ptr[i] = data[3];
1113 		ib->ptr[i+1] = 0;
1114 	}
1115 	ib->length_dw = 16;
1116 
1117 	if (direct) {
1118 		r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv,
1119 							true, false,
1120 							msecs_to_jiffies(10));
1121 		if (r == 0)
1122 			r = -ETIMEDOUT;
1123 		if (r < 0)
1124 			goto err_free;
1125 
1126 		r = amdgpu_job_submit_direct(job, ring, &f);
1127 		if (r)
1128 			goto err_free;
1129 	} else {
1130 		r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv,
1131 				     AMDGPU_SYNC_ALWAYS,
1132 				     AMDGPU_FENCE_OWNER_UNDEFINED);
1133 		if (r)
1134 			goto err_free;
1135 
1136 		r = amdgpu_job_submit(job, &adev->uvd.entity,
1137 				      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
1138 		if (r)
1139 			goto err_free;
1140 	}
1141 
1142 	amdgpu_bo_fence(bo, f, false);
1143 	amdgpu_bo_unreserve(bo);
1144 	amdgpu_bo_unref(&bo);
1145 
1146 	if (fence)
1147 		*fence = dma_fence_get(f);
1148 	dma_fence_put(f);
1149 
1150 	return 0;
1151 
1152 err_free:
1153 	amdgpu_job_free(job);
1154 
1155 err:
1156 	amdgpu_bo_unreserve(bo);
1157 	amdgpu_bo_unref(&bo);
1158 	return r;
1159 }
1160 
1161 /* multiple fence commands without any stream commands in between can
1162    crash the vcpu so just try to emmit a dummy create/destroy msg to
1163    avoid this */
1164 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1165 			      struct dma_fence **fence)
1166 {
1167 	struct amdgpu_device *adev = ring->adev;
1168 	struct amdgpu_bo *bo = NULL;
1169 	uint32_t *msg;
1170 	int r, i;
1171 
1172 	r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1173 				      AMDGPU_GEM_DOMAIN_GTT,
1174 				      &bo, NULL, (void **)&msg);
1175 	if (r)
1176 		return r;
1177 
1178 	/* stitch together an UVD create msg */
1179 	msg[0] = cpu_to_le32(0x00000de4);
1180 	msg[1] = cpu_to_le32(0x00000000);
1181 	msg[2] = cpu_to_le32(handle);
1182 	msg[3] = cpu_to_le32(0x00000000);
1183 	msg[4] = cpu_to_le32(0x00000000);
1184 	msg[5] = cpu_to_le32(0x00000000);
1185 	msg[6] = cpu_to_le32(0x00000000);
1186 	msg[7] = cpu_to_le32(0x00000780);
1187 	msg[8] = cpu_to_le32(0x00000440);
1188 	msg[9] = cpu_to_le32(0x00000000);
1189 	msg[10] = cpu_to_le32(0x01b37000);
1190 	for (i = 11; i < 1024; ++i)
1191 		msg[i] = cpu_to_le32(0x0);
1192 
1193 	return amdgpu_uvd_send_msg(ring, bo, true, fence);
1194 }
1195 
1196 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1197 			       bool direct, struct dma_fence **fence)
1198 {
1199 	struct amdgpu_device *adev = ring->adev;
1200 	struct amdgpu_bo *bo = NULL;
1201 	uint32_t *msg;
1202 	int r, i;
1203 
1204 	r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1205 				      AMDGPU_GEM_DOMAIN_GTT,
1206 				      &bo, NULL, (void **)&msg);
1207 	if (r)
1208 		return r;
1209 
1210 	/* stitch together an UVD destroy msg */
1211 	msg[0] = cpu_to_le32(0x00000de4);
1212 	msg[1] = cpu_to_le32(0x00000002);
1213 	msg[2] = cpu_to_le32(handle);
1214 	msg[3] = cpu_to_le32(0x00000000);
1215 	for (i = 4; i < 1024; ++i)
1216 		msg[i] = cpu_to_le32(0x0);
1217 
1218 	return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1219 }
1220 
1221 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1222 {
1223 	struct amdgpu_device *adev =
1224 		container_of(work, struct amdgpu_device, uvd.idle_work.work);
1225 	unsigned fences = 0, i, j;
1226 
1227 	for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1228 		if (adev->uvd.harvest_config & (1 << i))
1229 			continue;
1230 		fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1231 		for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
1232 			fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1233 		}
1234 	}
1235 
1236 	if (fences == 0) {
1237 		if (adev->pm.dpm_enabled) {
1238 			amdgpu_dpm_enable_uvd(adev, false);
1239 		} else {
1240 			amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1241 			/* shutdown the UVD block */
1242 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1243 							       AMD_PG_STATE_GATE);
1244 			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1245 							       AMD_CG_STATE_GATE);
1246 		}
1247 	} else {
1248 		schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1249 	}
1250 }
1251 
1252 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1253 {
1254 	struct amdgpu_device *adev = ring->adev;
1255 	bool set_clocks;
1256 
1257 	if (amdgpu_sriov_vf(adev))
1258 		return;
1259 
1260 	set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1261 	if (set_clocks) {
1262 		if (adev->pm.dpm_enabled) {
1263 			amdgpu_dpm_enable_uvd(adev, true);
1264 		} else {
1265 			amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1266 			amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1267 							       AMD_CG_STATE_UNGATE);
1268 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1269 							       AMD_PG_STATE_UNGATE);
1270 		}
1271 	}
1272 }
1273 
1274 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1275 {
1276 	if (!amdgpu_sriov_vf(ring->adev))
1277 		schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1278 }
1279 
1280 /**
1281  * amdgpu_uvd_ring_test_ib - test ib execution
1282  *
1283  * @ring: amdgpu_ring pointer
1284  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1285  *
1286  * Test if we can successfully execute an IB
1287  */
1288 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1289 {
1290 	struct dma_fence *fence;
1291 	long r;
1292 
1293 	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1294 	if (r)
1295 		goto error;
1296 
1297 	r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1298 	if (r)
1299 		goto error;
1300 
1301 	r = dma_fence_wait_timeout(fence, false, timeout);
1302 	if (r == 0)
1303 		r = -ETIMEDOUT;
1304 	else if (r > 0)
1305 		r = 0;
1306 
1307 	dma_fence_put(fence);
1308 
1309 error:
1310 	return r;
1311 }
1312 
1313 /**
1314  * amdgpu_uvd_used_handles - returns used UVD handles
1315  *
1316  * @adev: amdgpu_device pointer
1317  *
1318  * Returns the number of UVD handles in use
1319  */
1320 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1321 {
1322 	unsigned i;
1323 	uint32_t used_handles = 0;
1324 
1325 	for (i = 0; i < adev->uvd.max_handles; ++i) {
1326 		/*
1327 		 * Handles can be freed in any order, and not
1328 		 * necessarily linear. So we need to count
1329 		 * all non-zero handles.
1330 		 */
1331 		if (atomic_read(&adev->uvd.handles[i]))
1332 			used_handles++;
1333 	}
1334 
1335 	return used_handles;
1336 }
1337