1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 /* 1 second timeout */ 43 #define UVD_IDLE_TIMEOUT_MS 1000 44 45 /* Firmware Names */ 46 #ifdef CONFIG_DRM_AMDGPU_CIK 47 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 48 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" 49 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" 50 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" 51 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" 52 #endif 53 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 54 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 55 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 56 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 57 58 /** 59 * amdgpu_uvd_cs_ctx - Command submission parser context 60 * 61 * Used for emulating virtual memory support on UVD 4.2. 62 */ 63 struct amdgpu_uvd_cs_ctx { 64 struct amdgpu_cs_parser *parser; 65 unsigned reg, count; 66 unsigned data0, data1; 67 unsigned idx; 68 unsigned ib_idx; 69 70 /* does the IB has a msg command */ 71 bool has_msg_cmd; 72 73 /* minimum buffer sizes */ 74 unsigned *buf_sizes; 75 }; 76 77 #ifdef CONFIG_DRM_AMDGPU_CIK 78 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 79 MODULE_FIRMWARE(FIRMWARE_KABINI); 80 MODULE_FIRMWARE(FIRMWARE_KAVERI); 81 MODULE_FIRMWARE(FIRMWARE_HAWAII); 82 MODULE_FIRMWARE(FIRMWARE_MULLINS); 83 #endif 84 MODULE_FIRMWARE(FIRMWARE_TONGA); 85 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 86 MODULE_FIRMWARE(FIRMWARE_FIJI); 87 MODULE_FIRMWARE(FIRMWARE_STONEY); 88 89 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); 90 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 91 92 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 93 { 94 struct amdgpu_ring *ring; 95 struct amd_sched_rq *rq; 96 unsigned long bo_size; 97 const char *fw_name; 98 const struct common_firmware_header *hdr; 99 unsigned version_major, version_minor, family_id; 100 int i, r; 101 102 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 103 104 switch (adev->asic_type) { 105 #ifdef CONFIG_DRM_AMDGPU_CIK 106 case CHIP_BONAIRE: 107 fw_name = FIRMWARE_BONAIRE; 108 break; 109 case CHIP_KABINI: 110 fw_name = FIRMWARE_KABINI; 111 break; 112 case CHIP_KAVERI: 113 fw_name = FIRMWARE_KAVERI; 114 break; 115 case CHIP_HAWAII: 116 fw_name = FIRMWARE_HAWAII; 117 break; 118 case CHIP_MULLINS: 119 fw_name = FIRMWARE_MULLINS; 120 break; 121 #endif 122 case CHIP_TONGA: 123 fw_name = FIRMWARE_TONGA; 124 break; 125 case CHIP_FIJI: 126 fw_name = FIRMWARE_FIJI; 127 break; 128 case CHIP_CARRIZO: 129 fw_name = FIRMWARE_CARRIZO; 130 break; 131 case CHIP_STONEY: 132 fw_name = FIRMWARE_STONEY; 133 break; 134 default: 135 return -EINVAL; 136 } 137 138 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 139 if (r) { 140 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 141 fw_name); 142 return r; 143 } 144 145 r = amdgpu_ucode_validate(adev->uvd.fw); 146 if (r) { 147 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 148 fw_name); 149 release_firmware(adev->uvd.fw); 150 adev->uvd.fw = NULL; 151 return r; 152 } 153 154 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 155 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 156 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 157 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 158 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 159 version_major, version_minor, family_id); 160 161 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) 162 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE; 163 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, 164 AMDGPU_GEM_DOMAIN_VRAM, 165 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 166 NULL, NULL, &adev->uvd.vcpu_bo); 167 if (r) { 168 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 169 return r; 170 } 171 172 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 173 if (r) { 174 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 175 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r); 176 return r; 177 } 178 179 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, 180 &adev->uvd.gpu_addr); 181 if (r) { 182 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 183 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 184 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r); 185 return r; 186 } 187 188 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr); 189 if (r) { 190 dev_err(adev->dev, "(%d) UVD map failed\n", r); 191 return r; 192 } 193 194 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 195 196 ring = &adev->uvd.ring; 197 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; 198 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, 199 rq, amdgpu_sched_jobs); 200 if (r != 0) { 201 DRM_ERROR("Failed setting up UVD run queue.\n"); 202 return r; 203 } 204 205 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 206 atomic_set(&adev->uvd.handles[i], 0); 207 adev->uvd.filp[i] = NULL; 208 } 209 210 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 211 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 212 adev->uvd.address_64_bit = true; 213 214 return 0; 215 } 216 217 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 218 { 219 int r; 220 221 if (adev->uvd.vcpu_bo == NULL) 222 return 0; 223 224 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); 225 226 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 227 if (!r) { 228 amdgpu_bo_kunmap(adev->uvd.vcpu_bo); 229 amdgpu_bo_unpin(adev->uvd.vcpu_bo); 230 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 231 } 232 233 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 234 235 amdgpu_ring_fini(&adev->uvd.ring); 236 237 release_firmware(adev->uvd.fw); 238 239 return 0; 240 } 241 242 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 243 { 244 struct amdgpu_ring *ring = &adev->uvd.ring; 245 int i, r; 246 247 if (adev->uvd.vcpu_bo == NULL) 248 return 0; 249 250 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 251 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 252 if (handle != 0) { 253 struct fence *fence; 254 255 amdgpu_uvd_note_usage(adev); 256 257 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, &fence); 258 if (r) { 259 DRM_ERROR("Error destroying UVD (%d)!\n", r); 260 continue; 261 } 262 263 fence_wait(fence, false); 264 fence_put(fence); 265 266 adev->uvd.filp[i] = NULL; 267 atomic_set(&adev->uvd.handles[i], 0); 268 } 269 } 270 271 return 0; 272 } 273 274 int amdgpu_uvd_resume(struct amdgpu_device *adev) 275 { 276 unsigned size; 277 void *ptr; 278 const struct common_firmware_header *hdr; 279 unsigned offset; 280 281 if (adev->uvd.vcpu_bo == NULL) 282 return -EINVAL; 283 284 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 285 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 286 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, 287 (adev->uvd.fw->size) - offset); 288 289 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 290 size -= le32_to_cpu(hdr->ucode_size_bytes); 291 ptr = adev->uvd.cpu_addr; 292 ptr += le32_to_cpu(hdr->ucode_size_bytes); 293 294 memset(ptr, 0, size); 295 296 return 0; 297 } 298 299 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 300 { 301 struct amdgpu_ring *ring = &adev->uvd.ring; 302 int i, r; 303 304 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 305 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 306 if (handle != 0 && adev->uvd.filp[i] == filp) { 307 struct fence *fence; 308 309 amdgpu_uvd_note_usage(adev); 310 311 r = amdgpu_uvd_get_destroy_msg(ring, handle, 312 false, &fence); 313 if (r) { 314 DRM_ERROR("Error destroying UVD (%d)!\n", r); 315 continue; 316 } 317 318 fence_wait(fence, false); 319 fence_put(fence); 320 321 adev->uvd.filp[i] = NULL; 322 atomic_set(&adev->uvd.handles[i], 0); 323 } 324 } 325 } 326 327 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) 328 { 329 int i; 330 for (i = 0; i < rbo->placement.num_placement; ++i) { 331 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; 332 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 333 } 334 } 335 336 /** 337 * amdgpu_uvd_cs_pass1 - first parsing round 338 * 339 * @ctx: UVD parser context 340 * 341 * Make sure UVD message and feedback buffers are in VRAM and 342 * nobody is violating an 256MB boundary. 343 */ 344 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 345 { 346 struct amdgpu_bo_va_mapping *mapping; 347 struct amdgpu_bo *bo; 348 uint32_t cmd, lo, hi; 349 uint64_t addr; 350 int r = 0; 351 352 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 353 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 354 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 355 356 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 357 if (mapping == NULL) { 358 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 359 return -EINVAL; 360 } 361 362 if (!ctx->parser->adev->uvd.address_64_bit) { 363 /* check if it's a message or feedback command */ 364 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 365 if (cmd == 0x0 || cmd == 0x3) { 366 /* yes, force it into VRAM */ 367 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 368 amdgpu_ttm_placement_from_domain(bo, domain); 369 } 370 amdgpu_uvd_force_into_uvd_segment(bo); 371 372 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 373 } 374 375 return r; 376 } 377 378 /** 379 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 380 * 381 * @msg: pointer to message structure 382 * @buf_sizes: returned buffer sizes 383 * 384 * Peek into the decode message and calculate the necessary buffer sizes. 385 */ 386 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 387 { 388 unsigned stream_type = msg[4]; 389 unsigned width = msg[6]; 390 unsigned height = msg[7]; 391 unsigned dpb_size = msg[9]; 392 unsigned pitch = msg[28]; 393 unsigned level = msg[57]; 394 395 unsigned width_in_mb = width / 16; 396 unsigned height_in_mb = ALIGN(height / 16, 2); 397 unsigned fs_in_mb = width_in_mb * height_in_mb; 398 399 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 400 unsigned min_ctx_size = 0; 401 402 image_size = width * height; 403 image_size += image_size / 2; 404 image_size = ALIGN(image_size, 1024); 405 406 switch (stream_type) { 407 case 0: /* H264 */ 408 case 7: /* H264 Perf */ 409 switch(level) { 410 case 30: 411 num_dpb_buffer = 8100 / fs_in_mb; 412 break; 413 case 31: 414 num_dpb_buffer = 18000 / fs_in_mb; 415 break; 416 case 32: 417 num_dpb_buffer = 20480 / fs_in_mb; 418 break; 419 case 41: 420 num_dpb_buffer = 32768 / fs_in_mb; 421 break; 422 case 42: 423 num_dpb_buffer = 34816 / fs_in_mb; 424 break; 425 case 50: 426 num_dpb_buffer = 110400 / fs_in_mb; 427 break; 428 case 51: 429 num_dpb_buffer = 184320 / fs_in_mb; 430 break; 431 default: 432 num_dpb_buffer = 184320 / fs_in_mb; 433 break; 434 } 435 num_dpb_buffer++; 436 if (num_dpb_buffer > 17) 437 num_dpb_buffer = 17; 438 439 /* reference picture buffer */ 440 min_dpb_size = image_size * num_dpb_buffer; 441 442 /* macroblock context buffer */ 443 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 444 445 /* IT surface buffer */ 446 min_dpb_size += width_in_mb * height_in_mb * 32; 447 break; 448 449 case 1: /* VC1 */ 450 451 /* reference picture buffer */ 452 min_dpb_size = image_size * 3; 453 454 /* CONTEXT_BUFFER */ 455 min_dpb_size += width_in_mb * height_in_mb * 128; 456 457 /* IT surface buffer */ 458 min_dpb_size += width_in_mb * 64; 459 460 /* DB surface buffer */ 461 min_dpb_size += width_in_mb * 128; 462 463 /* BP */ 464 tmp = max(width_in_mb, height_in_mb); 465 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 466 break; 467 468 case 3: /* MPEG2 */ 469 470 /* reference picture buffer */ 471 min_dpb_size = image_size * 3; 472 break; 473 474 case 4: /* MPEG4 */ 475 476 /* reference picture buffer */ 477 min_dpb_size = image_size * 3; 478 479 /* CM */ 480 min_dpb_size += width_in_mb * height_in_mb * 64; 481 482 /* IT surface buffer */ 483 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 484 break; 485 486 case 16: /* H265 */ 487 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 488 image_size = ALIGN(image_size, 256); 489 490 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 491 min_dpb_size = image_size * num_dpb_buffer; 492 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 493 * 16 * num_dpb_buffer + 52 * 1024; 494 break; 495 496 default: 497 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 498 return -EINVAL; 499 } 500 501 if (width > pitch) { 502 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 503 return -EINVAL; 504 } 505 506 if (dpb_size < min_dpb_size) { 507 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 508 dpb_size, min_dpb_size); 509 return -EINVAL; 510 } 511 512 buf_sizes[0x1] = dpb_size; 513 buf_sizes[0x2] = image_size; 514 buf_sizes[0x4] = min_ctx_size; 515 return 0; 516 } 517 518 /** 519 * amdgpu_uvd_cs_msg - handle UVD message 520 * 521 * @ctx: UVD parser context 522 * @bo: buffer object containing the message 523 * @offset: offset into the buffer object 524 * 525 * Peek into the UVD message and extract the session id. 526 * Make sure that we don't open up to many sessions. 527 */ 528 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 529 struct amdgpu_bo *bo, unsigned offset) 530 { 531 struct amdgpu_device *adev = ctx->parser->adev; 532 int32_t *msg, msg_type, handle; 533 void *ptr; 534 long r; 535 int i; 536 537 if (offset & 0x3F) { 538 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 539 return -EINVAL; 540 } 541 542 r = amdgpu_bo_kmap(bo, &ptr); 543 if (r) { 544 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); 545 return r; 546 } 547 548 msg = ptr + offset; 549 550 msg_type = msg[1]; 551 handle = msg[2]; 552 553 if (handle == 0) { 554 DRM_ERROR("Invalid UVD handle!\n"); 555 return -EINVAL; 556 } 557 558 switch (msg_type) { 559 case 0: 560 /* it's a create msg, calc image size (width * height) */ 561 amdgpu_bo_kunmap(bo); 562 563 /* try to alloc a new handle */ 564 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 565 if (atomic_read(&adev->uvd.handles[i]) == handle) { 566 DRM_ERROR("Handle 0x%x already in use!\n", handle); 567 return -EINVAL; 568 } 569 570 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 571 adev->uvd.filp[i] = ctx->parser->filp; 572 return 0; 573 } 574 } 575 576 DRM_ERROR("No more free UVD handles!\n"); 577 return -EINVAL; 578 579 case 1: 580 /* it's a decode msg, calc buffer sizes */ 581 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes); 582 amdgpu_bo_kunmap(bo); 583 if (r) 584 return r; 585 586 /* validate the handle */ 587 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 588 if (atomic_read(&adev->uvd.handles[i]) == handle) { 589 if (adev->uvd.filp[i] != ctx->parser->filp) { 590 DRM_ERROR("UVD handle collision detected!\n"); 591 return -EINVAL; 592 } 593 return 0; 594 } 595 } 596 597 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 598 return -ENOENT; 599 600 case 2: 601 /* it's a destroy msg, free the handle */ 602 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 603 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 604 amdgpu_bo_kunmap(bo); 605 return 0; 606 607 default: 608 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 609 return -EINVAL; 610 } 611 BUG(); 612 return -EINVAL; 613 } 614 615 /** 616 * amdgpu_uvd_cs_pass2 - second parsing round 617 * 618 * @ctx: UVD parser context 619 * 620 * Patch buffer addresses, make sure buffer sizes are correct. 621 */ 622 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 623 { 624 struct amdgpu_bo_va_mapping *mapping; 625 struct amdgpu_bo *bo; 626 uint32_t cmd, lo, hi; 627 uint64_t start, end; 628 uint64_t addr; 629 int r; 630 631 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 632 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 633 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 634 635 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 636 if (mapping == NULL) 637 return -EINVAL; 638 639 start = amdgpu_bo_gpu_offset(bo); 640 641 end = (mapping->it.last + 1 - mapping->it.start); 642 end = end * AMDGPU_GPU_PAGE_SIZE + start; 643 644 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; 645 start += addr; 646 647 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 648 lower_32_bits(start)); 649 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 650 upper_32_bits(start)); 651 652 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 653 if (cmd < 0x4) { 654 if ((end - start) < ctx->buf_sizes[cmd]) { 655 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 656 (unsigned)(end - start), 657 ctx->buf_sizes[cmd]); 658 return -EINVAL; 659 } 660 661 } else if (cmd == 0x206) { 662 if ((end - start) < ctx->buf_sizes[4]) { 663 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 664 (unsigned)(end - start), 665 ctx->buf_sizes[4]); 666 return -EINVAL; 667 } 668 } else if ((cmd != 0x100) && (cmd != 0x204)) { 669 DRM_ERROR("invalid UVD command %X!\n", cmd); 670 return -EINVAL; 671 } 672 673 if (!ctx->parser->adev->uvd.address_64_bit) { 674 if ((start >> 28) != ((end - 1) >> 28)) { 675 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 676 start, end); 677 return -EINVAL; 678 } 679 680 if ((cmd == 0 || cmd == 0x3) && 681 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { 682 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 683 start, end); 684 return -EINVAL; 685 } 686 } 687 688 if (cmd == 0) { 689 ctx->has_msg_cmd = true; 690 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 691 if (r) 692 return r; 693 } else if (!ctx->has_msg_cmd) { 694 DRM_ERROR("Message needed before other commands are send!\n"); 695 return -EINVAL; 696 } 697 698 return 0; 699 } 700 701 /** 702 * amdgpu_uvd_cs_reg - parse register writes 703 * 704 * @ctx: UVD parser context 705 * @cb: callback function 706 * 707 * Parse the register writes, call cb on each complete command. 708 */ 709 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 710 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 711 { 712 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 713 int i, r; 714 715 ctx->idx++; 716 for (i = 0; i <= ctx->count; ++i) { 717 unsigned reg = ctx->reg + i; 718 719 if (ctx->idx >= ib->length_dw) { 720 DRM_ERROR("Register command after end of CS!\n"); 721 return -EINVAL; 722 } 723 724 switch (reg) { 725 case mmUVD_GPCOM_VCPU_DATA0: 726 ctx->data0 = ctx->idx; 727 break; 728 case mmUVD_GPCOM_VCPU_DATA1: 729 ctx->data1 = ctx->idx; 730 break; 731 case mmUVD_GPCOM_VCPU_CMD: 732 r = cb(ctx); 733 if (r) 734 return r; 735 break; 736 case mmUVD_ENGINE_CNTL: 737 break; 738 default: 739 DRM_ERROR("Invalid reg 0x%X!\n", reg); 740 return -EINVAL; 741 } 742 ctx->idx++; 743 } 744 return 0; 745 } 746 747 /** 748 * amdgpu_uvd_cs_packets - parse UVD packets 749 * 750 * @ctx: UVD parser context 751 * @cb: callback function 752 * 753 * Parse the command stream packets. 754 */ 755 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 756 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 757 { 758 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 759 int r; 760 761 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 762 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 763 unsigned type = CP_PACKET_GET_TYPE(cmd); 764 switch (type) { 765 case PACKET_TYPE0: 766 ctx->reg = CP_PACKET0_GET_REG(cmd); 767 ctx->count = CP_PACKET_GET_COUNT(cmd); 768 r = amdgpu_uvd_cs_reg(ctx, cb); 769 if (r) 770 return r; 771 break; 772 case PACKET_TYPE2: 773 ++ctx->idx; 774 break; 775 default: 776 DRM_ERROR("Unknown packet type %d !\n", type); 777 return -EINVAL; 778 } 779 } 780 return 0; 781 } 782 783 /** 784 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 785 * 786 * @parser: Command submission parser context 787 * 788 * Parse the command stream, patch in addresses as necessary. 789 */ 790 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 791 { 792 struct amdgpu_uvd_cs_ctx ctx = {}; 793 unsigned buf_sizes[] = { 794 [0x00000000] = 2048, 795 [0x00000001] = 0xFFFFFFFF, 796 [0x00000002] = 0xFFFFFFFF, 797 [0x00000003] = 2048, 798 [0x00000004] = 0xFFFFFFFF, 799 }; 800 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 801 int r; 802 803 if (ib->length_dw % 16) { 804 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 805 ib->length_dw); 806 return -EINVAL; 807 } 808 809 ctx.parser = parser; 810 ctx.buf_sizes = buf_sizes; 811 ctx.ib_idx = ib_idx; 812 813 /* first round, make sure the buffers are actually in the UVD segment */ 814 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 815 if (r) 816 return r; 817 818 /* second round, patch buffer addresses into the command stream */ 819 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 820 if (r) 821 return r; 822 823 if (!ctx.has_msg_cmd) { 824 DRM_ERROR("UVD-IBs need a msg command!\n"); 825 return -EINVAL; 826 } 827 828 amdgpu_uvd_note_usage(ctx.parser->adev); 829 830 return 0; 831 } 832 833 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 834 bool direct, struct fence **fence) 835 { 836 struct ttm_validate_buffer tv; 837 struct ww_acquire_ctx ticket; 838 struct list_head head; 839 struct amdgpu_job *job; 840 struct amdgpu_ib *ib; 841 struct fence *f = NULL; 842 struct amdgpu_device *adev = ring->adev; 843 uint64_t addr; 844 int i, r; 845 846 memset(&tv, 0, sizeof(tv)); 847 tv.bo = &bo->tbo; 848 849 INIT_LIST_HEAD(&head); 850 list_add(&tv.head, &head); 851 852 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); 853 if (r) 854 return r; 855 856 if (!bo->adev->uvd.address_64_bit) { 857 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 858 amdgpu_uvd_force_into_uvd_segment(bo); 859 } 860 861 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 862 if (r) 863 goto err; 864 865 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 866 if (r) 867 goto err; 868 869 ib = &job->ibs[0]; 870 addr = amdgpu_bo_gpu_offset(bo); 871 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); 872 ib->ptr[1] = addr; 873 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); 874 ib->ptr[3] = addr >> 32; 875 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 876 ib->ptr[5] = 0; 877 for (i = 6; i < 16; ++i) 878 ib->ptr[i] = PACKET2(0); 879 ib->length_dw = 16; 880 881 if (direct) { 882 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 883 job->fence = f; 884 if (r) 885 goto err_free; 886 887 amdgpu_job_free(job); 888 } else { 889 r = amdgpu_job_submit(job, ring, &adev->uvd.entity, 890 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 891 if (r) 892 goto err_free; 893 } 894 895 ttm_eu_fence_buffer_objects(&ticket, &head, f); 896 897 if (fence) 898 *fence = fence_get(f); 899 amdgpu_bo_unref(&bo); 900 fence_put(f); 901 902 return 0; 903 904 err_free: 905 amdgpu_job_free(job); 906 907 err: 908 ttm_eu_backoff_reservation(&ticket, &head); 909 return r; 910 } 911 912 /* multiple fence commands without any stream commands in between can 913 crash the vcpu so just try to emmit a dummy create/destroy msg to 914 avoid this */ 915 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 916 struct fence **fence) 917 { 918 struct amdgpu_device *adev = ring->adev; 919 struct amdgpu_bo *bo; 920 uint32_t *msg; 921 int r, i; 922 923 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 924 AMDGPU_GEM_DOMAIN_VRAM, 925 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 926 NULL, NULL, &bo); 927 if (r) 928 return r; 929 930 r = amdgpu_bo_reserve(bo, false); 931 if (r) { 932 amdgpu_bo_unref(&bo); 933 return r; 934 } 935 936 r = amdgpu_bo_kmap(bo, (void **)&msg); 937 if (r) { 938 amdgpu_bo_unreserve(bo); 939 amdgpu_bo_unref(&bo); 940 return r; 941 } 942 943 /* stitch together an UVD create msg */ 944 msg[0] = cpu_to_le32(0x00000de4); 945 msg[1] = cpu_to_le32(0x00000000); 946 msg[2] = cpu_to_le32(handle); 947 msg[3] = cpu_to_le32(0x00000000); 948 msg[4] = cpu_to_le32(0x00000000); 949 msg[5] = cpu_to_le32(0x00000000); 950 msg[6] = cpu_to_le32(0x00000000); 951 msg[7] = cpu_to_le32(0x00000780); 952 msg[8] = cpu_to_le32(0x00000440); 953 msg[9] = cpu_to_le32(0x00000000); 954 msg[10] = cpu_to_le32(0x01b37000); 955 for (i = 11; i < 1024; ++i) 956 msg[i] = cpu_to_le32(0x0); 957 958 amdgpu_bo_kunmap(bo); 959 amdgpu_bo_unreserve(bo); 960 961 return amdgpu_uvd_send_msg(ring, bo, true, fence); 962 } 963 964 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 965 bool direct, struct fence **fence) 966 { 967 struct amdgpu_device *adev = ring->adev; 968 struct amdgpu_bo *bo; 969 uint32_t *msg; 970 int r, i; 971 972 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 973 AMDGPU_GEM_DOMAIN_VRAM, 974 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 975 NULL, NULL, &bo); 976 if (r) 977 return r; 978 979 r = amdgpu_bo_reserve(bo, false); 980 if (r) { 981 amdgpu_bo_unref(&bo); 982 return r; 983 } 984 985 r = amdgpu_bo_kmap(bo, (void **)&msg); 986 if (r) { 987 amdgpu_bo_unreserve(bo); 988 amdgpu_bo_unref(&bo); 989 return r; 990 } 991 992 /* stitch together an UVD destroy msg */ 993 msg[0] = cpu_to_le32(0x00000de4); 994 msg[1] = cpu_to_le32(0x00000002); 995 msg[2] = cpu_to_le32(handle); 996 msg[3] = cpu_to_le32(0x00000000); 997 for (i = 4; i < 1024; ++i) 998 msg[i] = cpu_to_le32(0x0); 999 1000 amdgpu_bo_kunmap(bo); 1001 amdgpu_bo_unreserve(bo); 1002 1003 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1004 } 1005 1006 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1007 { 1008 struct amdgpu_device *adev = 1009 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1010 unsigned i, fences, handles = 0; 1011 1012 fences = amdgpu_fence_count_emitted(&adev->uvd.ring); 1013 1014 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 1015 if (atomic_read(&adev->uvd.handles[i])) 1016 ++handles; 1017 1018 if (fences == 0 && handles == 0) { 1019 if (adev->pm.dpm_enabled) { 1020 amdgpu_dpm_enable_uvd(adev, false); 1021 } else { 1022 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1023 } 1024 } else { 1025 schedule_delayed_work(&adev->uvd.idle_work, 1026 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 1027 } 1028 } 1029 1030 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev) 1031 { 1032 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1033 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work, 1034 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 1035 1036 if (set_clocks) { 1037 if (adev->pm.dpm_enabled) { 1038 amdgpu_dpm_enable_uvd(adev, true); 1039 } else { 1040 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1041 } 1042 } 1043 } 1044