1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 /* 1 second timeout */ 43 #define UVD_IDLE_TIMEOUT_MS 1000 44 45 /* Firmware Names */ 46 #ifdef CONFIG_DRM_AMDGPU_CIK 47 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 48 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" 49 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" 50 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" 51 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" 52 #endif 53 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 54 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 55 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 56 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 57 58 /** 59 * amdgpu_uvd_cs_ctx - Command submission parser context 60 * 61 * Used for emulating virtual memory support on UVD 4.2. 62 */ 63 struct amdgpu_uvd_cs_ctx { 64 struct amdgpu_cs_parser *parser; 65 unsigned reg, count; 66 unsigned data0, data1; 67 unsigned idx; 68 unsigned ib_idx; 69 70 /* does the IB has a msg command */ 71 bool has_msg_cmd; 72 73 /* minimum buffer sizes */ 74 unsigned *buf_sizes; 75 }; 76 77 #ifdef CONFIG_DRM_AMDGPU_CIK 78 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 79 MODULE_FIRMWARE(FIRMWARE_KABINI); 80 MODULE_FIRMWARE(FIRMWARE_KAVERI); 81 MODULE_FIRMWARE(FIRMWARE_HAWAII); 82 MODULE_FIRMWARE(FIRMWARE_MULLINS); 83 #endif 84 MODULE_FIRMWARE(FIRMWARE_TONGA); 85 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 86 MODULE_FIRMWARE(FIRMWARE_FIJI); 87 MODULE_FIRMWARE(FIRMWARE_STONEY); 88 89 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); 90 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 91 92 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 93 { 94 struct amdgpu_ring *ring; 95 struct amd_sched_rq *rq; 96 unsigned long bo_size; 97 const char *fw_name; 98 const struct common_firmware_header *hdr; 99 unsigned version_major, version_minor, family_id; 100 int i, r; 101 102 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 103 104 switch (adev->asic_type) { 105 #ifdef CONFIG_DRM_AMDGPU_CIK 106 case CHIP_BONAIRE: 107 fw_name = FIRMWARE_BONAIRE; 108 break; 109 case CHIP_KABINI: 110 fw_name = FIRMWARE_KABINI; 111 break; 112 case CHIP_KAVERI: 113 fw_name = FIRMWARE_KAVERI; 114 break; 115 case CHIP_HAWAII: 116 fw_name = FIRMWARE_HAWAII; 117 break; 118 case CHIP_MULLINS: 119 fw_name = FIRMWARE_MULLINS; 120 break; 121 #endif 122 case CHIP_TONGA: 123 fw_name = FIRMWARE_TONGA; 124 break; 125 case CHIP_FIJI: 126 fw_name = FIRMWARE_FIJI; 127 break; 128 case CHIP_CARRIZO: 129 fw_name = FIRMWARE_CARRIZO; 130 break; 131 case CHIP_STONEY: 132 fw_name = FIRMWARE_STONEY; 133 break; 134 default: 135 return -EINVAL; 136 } 137 138 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 139 if (r) { 140 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 141 fw_name); 142 return r; 143 } 144 145 r = amdgpu_ucode_validate(adev->uvd.fw); 146 if (r) { 147 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 148 fw_name); 149 release_firmware(adev->uvd.fw); 150 adev->uvd.fw = NULL; 151 return r; 152 } 153 154 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 155 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 156 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 157 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 158 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 159 version_major, version_minor, family_id); 160 161 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 162 (family_id << 8)); 163 164 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) 165 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE; 166 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, 167 AMDGPU_GEM_DOMAIN_VRAM, 168 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 169 NULL, NULL, &adev->uvd.vcpu_bo); 170 if (r) { 171 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 172 return r; 173 } 174 175 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 176 if (r) { 177 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 178 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r); 179 return r; 180 } 181 182 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, 183 &adev->uvd.gpu_addr); 184 if (r) { 185 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 186 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 187 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r); 188 return r; 189 } 190 191 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr); 192 if (r) { 193 dev_err(adev->dev, "(%d) UVD map failed\n", r); 194 return r; 195 } 196 197 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 198 199 ring = &adev->uvd.ring; 200 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; 201 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, 202 rq, amdgpu_sched_jobs); 203 if (r != 0) { 204 DRM_ERROR("Failed setting up UVD run queue.\n"); 205 return r; 206 } 207 208 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 209 atomic_set(&adev->uvd.handles[i], 0); 210 adev->uvd.filp[i] = NULL; 211 } 212 213 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 214 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 215 adev->uvd.address_64_bit = true; 216 217 return 0; 218 } 219 220 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 221 { 222 int r; 223 224 if (adev->uvd.vcpu_bo == NULL) 225 return 0; 226 227 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); 228 229 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); 230 if (!r) { 231 amdgpu_bo_kunmap(adev->uvd.vcpu_bo); 232 amdgpu_bo_unpin(adev->uvd.vcpu_bo); 233 amdgpu_bo_unreserve(adev->uvd.vcpu_bo); 234 } 235 236 amdgpu_bo_unref(&adev->uvd.vcpu_bo); 237 238 amdgpu_ring_fini(&adev->uvd.ring); 239 240 release_firmware(adev->uvd.fw); 241 242 return 0; 243 } 244 245 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 246 { 247 unsigned size; 248 void *ptr; 249 int i; 250 251 if (adev->uvd.vcpu_bo == NULL) 252 return 0; 253 254 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 255 if (atomic_read(&adev->uvd.handles[i])) 256 break; 257 258 if (i == AMDGPU_MAX_UVD_HANDLES) 259 return 0; 260 261 cancel_delayed_work_sync(&adev->uvd.idle_work); 262 263 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 264 ptr = adev->uvd.cpu_addr; 265 266 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 267 if (!adev->uvd.saved_bo) 268 return -ENOMEM; 269 270 memcpy(adev->uvd.saved_bo, ptr, size); 271 272 return 0; 273 } 274 275 int amdgpu_uvd_resume(struct amdgpu_device *adev) 276 { 277 unsigned size; 278 void *ptr; 279 280 if (adev->uvd.vcpu_bo == NULL) 281 return -EINVAL; 282 283 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 284 ptr = adev->uvd.cpu_addr; 285 286 if (adev->uvd.saved_bo != NULL) { 287 memcpy(ptr, adev->uvd.saved_bo, size); 288 kfree(adev->uvd.saved_bo); 289 adev->uvd.saved_bo = NULL; 290 } else { 291 const struct common_firmware_header *hdr; 292 unsigned offset; 293 294 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 295 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 296 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, 297 (adev->uvd.fw->size) - offset); 298 size -= le32_to_cpu(hdr->ucode_size_bytes); 299 ptr += le32_to_cpu(hdr->ucode_size_bytes); 300 memset(ptr, 0, size); 301 } 302 303 return 0; 304 } 305 306 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 307 { 308 struct amdgpu_ring *ring = &adev->uvd.ring; 309 int i, r; 310 311 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 312 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 313 if (handle != 0 && adev->uvd.filp[i] == filp) { 314 struct fence *fence; 315 316 amdgpu_uvd_note_usage(adev); 317 318 r = amdgpu_uvd_get_destroy_msg(ring, handle, 319 false, &fence); 320 if (r) { 321 DRM_ERROR("Error destroying UVD (%d)!\n", r); 322 continue; 323 } 324 325 fence_wait(fence, false); 326 fence_put(fence); 327 328 adev->uvd.filp[i] = NULL; 329 atomic_set(&adev->uvd.handles[i], 0); 330 } 331 } 332 } 333 334 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) 335 { 336 int i; 337 for (i = 0; i < rbo->placement.num_placement; ++i) { 338 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; 339 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 340 } 341 } 342 343 /** 344 * amdgpu_uvd_cs_pass1 - first parsing round 345 * 346 * @ctx: UVD parser context 347 * 348 * Make sure UVD message and feedback buffers are in VRAM and 349 * nobody is violating an 256MB boundary. 350 */ 351 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 352 { 353 struct amdgpu_bo_va_mapping *mapping; 354 struct amdgpu_bo *bo; 355 uint32_t cmd, lo, hi; 356 uint64_t addr; 357 int r = 0; 358 359 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 360 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 361 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 362 363 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 364 if (mapping == NULL) { 365 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 366 return -EINVAL; 367 } 368 369 if (!ctx->parser->adev->uvd.address_64_bit) { 370 /* check if it's a message or feedback command */ 371 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 372 if (cmd == 0x0 || cmd == 0x3) { 373 /* yes, force it into VRAM */ 374 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 375 amdgpu_ttm_placement_from_domain(bo, domain); 376 } 377 amdgpu_uvd_force_into_uvd_segment(bo); 378 379 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 380 } 381 382 return r; 383 } 384 385 /** 386 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 387 * 388 * @msg: pointer to message structure 389 * @buf_sizes: returned buffer sizes 390 * 391 * Peek into the decode message and calculate the necessary buffer sizes. 392 */ 393 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 394 { 395 unsigned stream_type = msg[4]; 396 unsigned width = msg[6]; 397 unsigned height = msg[7]; 398 unsigned dpb_size = msg[9]; 399 unsigned pitch = msg[28]; 400 unsigned level = msg[57]; 401 402 unsigned width_in_mb = width / 16; 403 unsigned height_in_mb = ALIGN(height / 16, 2); 404 unsigned fs_in_mb = width_in_mb * height_in_mb; 405 406 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 407 unsigned min_ctx_size = 0; 408 409 image_size = width * height; 410 image_size += image_size / 2; 411 image_size = ALIGN(image_size, 1024); 412 413 switch (stream_type) { 414 case 0: /* H264 */ 415 case 7: /* H264 Perf */ 416 switch(level) { 417 case 30: 418 num_dpb_buffer = 8100 / fs_in_mb; 419 break; 420 case 31: 421 num_dpb_buffer = 18000 / fs_in_mb; 422 break; 423 case 32: 424 num_dpb_buffer = 20480 / fs_in_mb; 425 break; 426 case 41: 427 num_dpb_buffer = 32768 / fs_in_mb; 428 break; 429 case 42: 430 num_dpb_buffer = 34816 / fs_in_mb; 431 break; 432 case 50: 433 num_dpb_buffer = 110400 / fs_in_mb; 434 break; 435 case 51: 436 num_dpb_buffer = 184320 / fs_in_mb; 437 break; 438 default: 439 num_dpb_buffer = 184320 / fs_in_mb; 440 break; 441 } 442 num_dpb_buffer++; 443 if (num_dpb_buffer > 17) 444 num_dpb_buffer = 17; 445 446 /* reference picture buffer */ 447 min_dpb_size = image_size * num_dpb_buffer; 448 449 /* macroblock context buffer */ 450 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 451 452 /* IT surface buffer */ 453 min_dpb_size += width_in_mb * height_in_mb * 32; 454 break; 455 456 case 1: /* VC1 */ 457 458 /* reference picture buffer */ 459 min_dpb_size = image_size * 3; 460 461 /* CONTEXT_BUFFER */ 462 min_dpb_size += width_in_mb * height_in_mb * 128; 463 464 /* IT surface buffer */ 465 min_dpb_size += width_in_mb * 64; 466 467 /* DB surface buffer */ 468 min_dpb_size += width_in_mb * 128; 469 470 /* BP */ 471 tmp = max(width_in_mb, height_in_mb); 472 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 473 break; 474 475 case 3: /* MPEG2 */ 476 477 /* reference picture buffer */ 478 min_dpb_size = image_size * 3; 479 break; 480 481 case 4: /* MPEG4 */ 482 483 /* reference picture buffer */ 484 min_dpb_size = image_size * 3; 485 486 /* CM */ 487 min_dpb_size += width_in_mb * height_in_mb * 64; 488 489 /* IT surface buffer */ 490 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 491 break; 492 493 case 16: /* H265 */ 494 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 495 image_size = ALIGN(image_size, 256); 496 497 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 498 min_dpb_size = image_size * num_dpb_buffer; 499 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 500 * 16 * num_dpb_buffer + 52 * 1024; 501 break; 502 503 default: 504 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 505 return -EINVAL; 506 } 507 508 if (width > pitch) { 509 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 510 return -EINVAL; 511 } 512 513 if (dpb_size < min_dpb_size) { 514 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 515 dpb_size, min_dpb_size); 516 return -EINVAL; 517 } 518 519 buf_sizes[0x1] = dpb_size; 520 buf_sizes[0x2] = image_size; 521 buf_sizes[0x4] = min_ctx_size; 522 return 0; 523 } 524 525 /** 526 * amdgpu_uvd_cs_msg - handle UVD message 527 * 528 * @ctx: UVD parser context 529 * @bo: buffer object containing the message 530 * @offset: offset into the buffer object 531 * 532 * Peek into the UVD message and extract the session id. 533 * Make sure that we don't open up to many sessions. 534 */ 535 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 536 struct amdgpu_bo *bo, unsigned offset) 537 { 538 struct amdgpu_device *adev = ctx->parser->adev; 539 int32_t *msg, msg_type, handle; 540 void *ptr; 541 long r; 542 int i; 543 544 if (offset & 0x3F) { 545 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 546 return -EINVAL; 547 } 548 549 r = amdgpu_bo_kmap(bo, &ptr); 550 if (r) { 551 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); 552 return r; 553 } 554 555 msg = ptr + offset; 556 557 msg_type = msg[1]; 558 handle = msg[2]; 559 560 if (handle == 0) { 561 DRM_ERROR("Invalid UVD handle!\n"); 562 return -EINVAL; 563 } 564 565 switch (msg_type) { 566 case 0: 567 /* it's a create msg, calc image size (width * height) */ 568 amdgpu_bo_kunmap(bo); 569 570 /* try to alloc a new handle */ 571 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 572 if (atomic_read(&adev->uvd.handles[i]) == handle) { 573 DRM_ERROR("Handle 0x%x already in use!\n", handle); 574 return -EINVAL; 575 } 576 577 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 578 adev->uvd.filp[i] = ctx->parser->filp; 579 return 0; 580 } 581 } 582 583 DRM_ERROR("No more free UVD handles!\n"); 584 return -EINVAL; 585 586 case 1: 587 /* it's a decode msg, calc buffer sizes */ 588 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes); 589 amdgpu_bo_kunmap(bo); 590 if (r) 591 return r; 592 593 /* validate the handle */ 594 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 595 if (atomic_read(&adev->uvd.handles[i]) == handle) { 596 if (adev->uvd.filp[i] != ctx->parser->filp) { 597 DRM_ERROR("UVD handle collision detected!\n"); 598 return -EINVAL; 599 } 600 return 0; 601 } 602 } 603 604 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 605 return -ENOENT; 606 607 case 2: 608 /* it's a destroy msg, free the handle */ 609 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 610 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 611 amdgpu_bo_kunmap(bo); 612 return 0; 613 614 default: 615 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 616 return -EINVAL; 617 } 618 BUG(); 619 return -EINVAL; 620 } 621 622 /** 623 * amdgpu_uvd_cs_pass2 - second parsing round 624 * 625 * @ctx: UVD parser context 626 * 627 * Patch buffer addresses, make sure buffer sizes are correct. 628 */ 629 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 630 { 631 struct amdgpu_bo_va_mapping *mapping; 632 struct amdgpu_bo *bo; 633 uint32_t cmd, lo, hi; 634 uint64_t start, end; 635 uint64_t addr; 636 int r; 637 638 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 639 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 640 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 641 642 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 643 if (mapping == NULL) 644 return -EINVAL; 645 646 start = amdgpu_bo_gpu_offset(bo); 647 648 end = (mapping->it.last + 1 - mapping->it.start); 649 end = end * AMDGPU_GPU_PAGE_SIZE + start; 650 651 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; 652 start += addr; 653 654 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 655 lower_32_bits(start)); 656 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 657 upper_32_bits(start)); 658 659 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 660 if (cmd < 0x4) { 661 if ((end - start) < ctx->buf_sizes[cmd]) { 662 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 663 (unsigned)(end - start), 664 ctx->buf_sizes[cmd]); 665 return -EINVAL; 666 } 667 668 } else if (cmd == 0x206) { 669 if ((end - start) < ctx->buf_sizes[4]) { 670 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 671 (unsigned)(end - start), 672 ctx->buf_sizes[4]); 673 return -EINVAL; 674 } 675 } else if ((cmd != 0x100) && (cmd != 0x204)) { 676 DRM_ERROR("invalid UVD command %X!\n", cmd); 677 return -EINVAL; 678 } 679 680 if (!ctx->parser->adev->uvd.address_64_bit) { 681 if ((start >> 28) != ((end - 1) >> 28)) { 682 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 683 start, end); 684 return -EINVAL; 685 } 686 687 if ((cmd == 0 || cmd == 0x3) && 688 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { 689 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 690 start, end); 691 return -EINVAL; 692 } 693 } 694 695 if (cmd == 0) { 696 ctx->has_msg_cmd = true; 697 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 698 if (r) 699 return r; 700 } else if (!ctx->has_msg_cmd) { 701 DRM_ERROR("Message needed before other commands are send!\n"); 702 return -EINVAL; 703 } 704 705 return 0; 706 } 707 708 /** 709 * amdgpu_uvd_cs_reg - parse register writes 710 * 711 * @ctx: UVD parser context 712 * @cb: callback function 713 * 714 * Parse the register writes, call cb on each complete command. 715 */ 716 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 717 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 718 { 719 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 720 int i, r; 721 722 ctx->idx++; 723 for (i = 0; i <= ctx->count; ++i) { 724 unsigned reg = ctx->reg + i; 725 726 if (ctx->idx >= ib->length_dw) { 727 DRM_ERROR("Register command after end of CS!\n"); 728 return -EINVAL; 729 } 730 731 switch (reg) { 732 case mmUVD_GPCOM_VCPU_DATA0: 733 ctx->data0 = ctx->idx; 734 break; 735 case mmUVD_GPCOM_VCPU_DATA1: 736 ctx->data1 = ctx->idx; 737 break; 738 case mmUVD_GPCOM_VCPU_CMD: 739 r = cb(ctx); 740 if (r) 741 return r; 742 break; 743 case mmUVD_ENGINE_CNTL: 744 break; 745 default: 746 DRM_ERROR("Invalid reg 0x%X!\n", reg); 747 return -EINVAL; 748 } 749 ctx->idx++; 750 } 751 return 0; 752 } 753 754 /** 755 * amdgpu_uvd_cs_packets - parse UVD packets 756 * 757 * @ctx: UVD parser context 758 * @cb: callback function 759 * 760 * Parse the command stream packets. 761 */ 762 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 763 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 764 { 765 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 766 int r; 767 768 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 769 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 770 unsigned type = CP_PACKET_GET_TYPE(cmd); 771 switch (type) { 772 case PACKET_TYPE0: 773 ctx->reg = CP_PACKET0_GET_REG(cmd); 774 ctx->count = CP_PACKET_GET_COUNT(cmd); 775 r = amdgpu_uvd_cs_reg(ctx, cb); 776 if (r) 777 return r; 778 break; 779 case PACKET_TYPE2: 780 ++ctx->idx; 781 break; 782 default: 783 DRM_ERROR("Unknown packet type %d !\n", type); 784 return -EINVAL; 785 } 786 } 787 return 0; 788 } 789 790 /** 791 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 792 * 793 * @parser: Command submission parser context 794 * 795 * Parse the command stream, patch in addresses as necessary. 796 */ 797 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 798 { 799 struct amdgpu_uvd_cs_ctx ctx = {}; 800 unsigned buf_sizes[] = { 801 [0x00000000] = 2048, 802 [0x00000001] = 0xFFFFFFFF, 803 [0x00000002] = 0xFFFFFFFF, 804 [0x00000003] = 2048, 805 [0x00000004] = 0xFFFFFFFF, 806 }; 807 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 808 int r; 809 810 if (ib->length_dw % 16) { 811 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 812 ib->length_dw); 813 return -EINVAL; 814 } 815 816 ctx.parser = parser; 817 ctx.buf_sizes = buf_sizes; 818 ctx.ib_idx = ib_idx; 819 820 /* first round, make sure the buffers are actually in the UVD segment */ 821 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 822 if (r) 823 return r; 824 825 /* second round, patch buffer addresses into the command stream */ 826 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 827 if (r) 828 return r; 829 830 if (!ctx.has_msg_cmd) { 831 DRM_ERROR("UVD-IBs need a msg command!\n"); 832 return -EINVAL; 833 } 834 835 amdgpu_uvd_note_usage(ctx.parser->adev); 836 837 return 0; 838 } 839 840 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 841 bool direct, struct fence **fence) 842 { 843 struct ttm_validate_buffer tv; 844 struct ww_acquire_ctx ticket; 845 struct list_head head; 846 struct amdgpu_job *job; 847 struct amdgpu_ib *ib; 848 struct fence *f = NULL; 849 struct amdgpu_device *adev = ring->adev; 850 uint64_t addr; 851 int i, r; 852 853 memset(&tv, 0, sizeof(tv)); 854 tv.bo = &bo->tbo; 855 856 INIT_LIST_HEAD(&head); 857 list_add(&tv.head, &head); 858 859 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); 860 if (r) 861 return r; 862 863 if (!bo->adev->uvd.address_64_bit) { 864 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 865 amdgpu_uvd_force_into_uvd_segment(bo); 866 } 867 868 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 869 if (r) 870 goto err; 871 872 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 873 if (r) 874 goto err; 875 876 ib = &job->ibs[0]; 877 addr = amdgpu_bo_gpu_offset(bo); 878 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); 879 ib->ptr[1] = addr; 880 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); 881 ib->ptr[3] = addr >> 32; 882 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 883 ib->ptr[5] = 0; 884 for (i = 6; i < 16; ++i) 885 ib->ptr[i] = PACKET2(0); 886 ib->length_dw = 16; 887 888 if (direct) { 889 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 890 job->fence = f; 891 if (r) 892 goto err_free; 893 894 amdgpu_job_free(job); 895 } else { 896 r = amdgpu_job_submit(job, ring, &adev->uvd.entity, 897 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 898 if (r) 899 goto err_free; 900 } 901 902 ttm_eu_fence_buffer_objects(&ticket, &head, f); 903 904 if (fence) 905 *fence = fence_get(f); 906 amdgpu_bo_unref(&bo); 907 fence_put(f); 908 909 return 0; 910 911 err_free: 912 amdgpu_job_free(job); 913 914 err: 915 ttm_eu_backoff_reservation(&ticket, &head); 916 return r; 917 } 918 919 /* multiple fence commands without any stream commands in between can 920 crash the vcpu so just try to emmit a dummy create/destroy msg to 921 avoid this */ 922 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 923 struct fence **fence) 924 { 925 struct amdgpu_device *adev = ring->adev; 926 struct amdgpu_bo *bo; 927 uint32_t *msg; 928 int r, i; 929 930 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 931 AMDGPU_GEM_DOMAIN_VRAM, 932 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 933 NULL, NULL, &bo); 934 if (r) 935 return r; 936 937 r = amdgpu_bo_reserve(bo, false); 938 if (r) { 939 amdgpu_bo_unref(&bo); 940 return r; 941 } 942 943 r = amdgpu_bo_kmap(bo, (void **)&msg); 944 if (r) { 945 amdgpu_bo_unreserve(bo); 946 amdgpu_bo_unref(&bo); 947 return r; 948 } 949 950 /* stitch together an UVD create msg */ 951 msg[0] = cpu_to_le32(0x00000de4); 952 msg[1] = cpu_to_le32(0x00000000); 953 msg[2] = cpu_to_le32(handle); 954 msg[3] = cpu_to_le32(0x00000000); 955 msg[4] = cpu_to_le32(0x00000000); 956 msg[5] = cpu_to_le32(0x00000000); 957 msg[6] = cpu_to_le32(0x00000000); 958 msg[7] = cpu_to_le32(0x00000780); 959 msg[8] = cpu_to_le32(0x00000440); 960 msg[9] = cpu_to_le32(0x00000000); 961 msg[10] = cpu_to_le32(0x01b37000); 962 for (i = 11; i < 1024; ++i) 963 msg[i] = cpu_to_le32(0x0); 964 965 amdgpu_bo_kunmap(bo); 966 amdgpu_bo_unreserve(bo); 967 968 return amdgpu_uvd_send_msg(ring, bo, true, fence); 969 } 970 971 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 972 bool direct, struct fence **fence) 973 { 974 struct amdgpu_device *adev = ring->adev; 975 struct amdgpu_bo *bo; 976 uint32_t *msg; 977 int r, i; 978 979 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, 980 AMDGPU_GEM_DOMAIN_VRAM, 981 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 982 NULL, NULL, &bo); 983 if (r) 984 return r; 985 986 r = amdgpu_bo_reserve(bo, false); 987 if (r) { 988 amdgpu_bo_unref(&bo); 989 return r; 990 } 991 992 r = amdgpu_bo_kmap(bo, (void **)&msg); 993 if (r) { 994 amdgpu_bo_unreserve(bo); 995 amdgpu_bo_unref(&bo); 996 return r; 997 } 998 999 /* stitch together an UVD destroy msg */ 1000 msg[0] = cpu_to_le32(0x00000de4); 1001 msg[1] = cpu_to_le32(0x00000002); 1002 msg[2] = cpu_to_le32(handle); 1003 msg[3] = cpu_to_le32(0x00000000); 1004 for (i = 4; i < 1024; ++i) 1005 msg[i] = cpu_to_le32(0x0); 1006 1007 amdgpu_bo_kunmap(bo); 1008 amdgpu_bo_unreserve(bo); 1009 1010 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1011 } 1012 1013 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1014 { 1015 struct amdgpu_device *adev = 1016 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1017 unsigned i, fences, handles = 0; 1018 1019 fences = amdgpu_fence_count_emitted(&adev->uvd.ring); 1020 1021 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 1022 if (atomic_read(&adev->uvd.handles[i])) 1023 ++handles; 1024 1025 if (fences == 0 && handles == 0) { 1026 if (adev->pm.dpm_enabled) { 1027 amdgpu_dpm_enable_uvd(adev, false); 1028 } else { 1029 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1030 } 1031 } else { 1032 schedule_delayed_work(&adev->uvd.idle_work, 1033 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 1034 } 1035 } 1036 1037 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev) 1038 { 1039 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1040 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work, 1041 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 1042 1043 if (set_clocks) { 1044 if (adev->pm.dpm_enabled) { 1045 amdgpu_dpm_enable_uvd(adev, true); 1046 } else { 1047 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1048 } 1049 } 1050 } 1051