1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Christian König <deathsimple@vodafone.de>
29  */
30 
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <drm/drmP.h>
34 #include <drm/drm.h>
35 
36 #include "amdgpu.h"
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
39 #include "cikd.h"
40 #include "uvd/uvd_4_2_d.h"
41 
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT	msecs_to_jiffies(1000)
44 
45 /* Firmware versions for VI */
46 #define FW_1_65_10	((1 << 24) | (65 << 16) | (10 << 8))
47 #define FW_1_87_11	((1 << 24) | (87 << 16) | (11 << 8))
48 #define FW_1_87_12	((1 << 24) | (87 << 16) | (12 << 8))
49 #define FW_1_37_15	((1 << 24) | (37 << 16) | (15 << 8))
50 
51 /* Polaris10/11 firmware version */
52 #define FW_1_66_16	((1 << 24) | (66 << 16) | (16 << 8))
53 
54 /* Firmware Names */
55 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #define FIRMWARE_BONAIRE	"radeon/bonaire_uvd.bin"
57 #define FIRMWARE_KABINI	"radeon/kabini_uvd.bin"
58 #define FIRMWARE_KAVERI	"radeon/kaveri_uvd.bin"
59 #define FIRMWARE_HAWAII	"radeon/hawaii_uvd.bin"
60 #define FIRMWARE_MULLINS	"radeon/mullins_uvd.bin"
61 #endif
62 #define FIRMWARE_TONGA		"amdgpu/tonga_uvd.bin"
63 #define FIRMWARE_CARRIZO	"amdgpu/carrizo_uvd.bin"
64 #define FIRMWARE_FIJI		"amdgpu/fiji_uvd.bin"
65 #define FIRMWARE_STONEY		"amdgpu/stoney_uvd.bin"
66 #define FIRMWARE_POLARIS10	"amdgpu/polaris10_uvd.bin"
67 #define FIRMWARE_POLARIS11	"amdgpu/polaris11_uvd.bin"
68 
69 /**
70  * amdgpu_uvd_cs_ctx - Command submission parser context
71  *
72  * Used for emulating virtual memory support on UVD 4.2.
73  */
74 struct amdgpu_uvd_cs_ctx {
75 	struct amdgpu_cs_parser *parser;
76 	unsigned reg, count;
77 	unsigned data0, data1;
78 	unsigned idx;
79 	unsigned ib_idx;
80 
81 	/* does the IB has a msg command */
82 	bool has_msg_cmd;
83 
84 	/* minimum buffer sizes */
85 	unsigned *buf_sizes;
86 };
87 
88 #ifdef CONFIG_DRM_AMDGPU_CIK
89 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
90 MODULE_FIRMWARE(FIRMWARE_KABINI);
91 MODULE_FIRMWARE(FIRMWARE_KAVERI);
92 MODULE_FIRMWARE(FIRMWARE_HAWAII);
93 MODULE_FIRMWARE(FIRMWARE_MULLINS);
94 #endif
95 MODULE_FIRMWARE(FIRMWARE_TONGA);
96 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
97 MODULE_FIRMWARE(FIRMWARE_FIJI);
98 MODULE_FIRMWARE(FIRMWARE_STONEY);
99 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
100 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
101 
102 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
103 
104 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
105 {
106 	struct amdgpu_ring *ring;
107 	struct amd_sched_rq *rq;
108 	unsigned long bo_size;
109 	const char *fw_name;
110 	const struct common_firmware_header *hdr;
111 	unsigned version_major, version_minor, family_id;
112 	int i, r;
113 
114 	INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
115 
116 	switch (adev->asic_type) {
117 #ifdef CONFIG_DRM_AMDGPU_CIK
118 	case CHIP_BONAIRE:
119 		fw_name = FIRMWARE_BONAIRE;
120 		break;
121 	case CHIP_KABINI:
122 		fw_name = FIRMWARE_KABINI;
123 		break;
124 	case CHIP_KAVERI:
125 		fw_name = FIRMWARE_KAVERI;
126 		break;
127 	case CHIP_HAWAII:
128 		fw_name = FIRMWARE_HAWAII;
129 		break;
130 	case CHIP_MULLINS:
131 		fw_name = FIRMWARE_MULLINS;
132 		break;
133 #endif
134 	case CHIP_TONGA:
135 		fw_name = FIRMWARE_TONGA;
136 		break;
137 	case CHIP_FIJI:
138 		fw_name = FIRMWARE_FIJI;
139 		break;
140 	case CHIP_CARRIZO:
141 		fw_name = FIRMWARE_CARRIZO;
142 		break;
143 	case CHIP_STONEY:
144 		fw_name = FIRMWARE_STONEY;
145 		break;
146 	case CHIP_POLARIS10:
147 		fw_name = FIRMWARE_POLARIS10;
148 		break;
149 	case CHIP_POLARIS11:
150 		fw_name = FIRMWARE_POLARIS11;
151 		break;
152 	default:
153 		return -EINVAL;
154 	}
155 
156 	r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
157 	if (r) {
158 		dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
159 			fw_name);
160 		return r;
161 	}
162 
163 	r = amdgpu_ucode_validate(adev->uvd.fw);
164 	if (r) {
165 		dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
166 			fw_name);
167 		release_firmware(adev->uvd.fw);
168 		adev->uvd.fw = NULL;
169 		return r;
170 	}
171 
172 	/* Set the default UVD handles that the firmware can handle */
173 	adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
174 
175 	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
176 	family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
177 	version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
178 	version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
179 	DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
180 		version_major, version_minor, family_id);
181 
182 	/*
183 	 * Limit the number of UVD handles depending on microcode major
184 	 * and minor versions. The firmware version which has 40 UVD
185 	 * instances support is 1.80. So all subsequent versions should
186 	 * also have the same support.
187 	 */
188 	if ((version_major > 0x01) ||
189 	    ((version_major == 0x01) && (version_minor >= 0x50)))
190 		adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
191 
192 	adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
193 				(family_id << 8));
194 
195 	if ((adev->asic_type == CHIP_POLARIS10 ||
196 	     adev->asic_type == CHIP_POLARIS11) &&
197 	    (adev->uvd.fw_version < FW_1_66_16))
198 		DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
199 			  version_major, version_minor);
200 
201 	bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
202 		  +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
203 		  +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
204 	r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
205 				    AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo,
206 				    &adev->uvd.gpu_addr, &adev->uvd.cpu_addr);
207 	if (r) {
208 		dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
209 		return r;
210 	}
211 
212 	ring = &adev->uvd.ring;
213 	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
214 	r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
215 				  rq, amdgpu_sched_jobs);
216 	if (r != 0) {
217 		DRM_ERROR("Failed setting up UVD run queue.\n");
218 		return r;
219 	}
220 
221 	for (i = 0; i < adev->uvd.max_handles; ++i) {
222 		atomic_set(&adev->uvd.handles[i], 0);
223 		adev->uvd.filp[i] = NULL;
224 	}
225 
226 	/* from uvd v5.0 HW addressing capacity increased to 64 bits */
227 	if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
228 		adev->uvd.address_64_bit = true;
229 
230 	switch (adev->asic_type) {
231 	case CHIP_TONGA:
232 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
233 		break;
234 	case CHIP_CARRIZO:
235 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
236 		break;
237 	case CHIP_FIJI:
238 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
239 		break;
240 	case CHIP_STONEY:
241 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
242 		break;
243 	default:
244 		adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
245 	}
246 
247 	return 0;
248 }
249 
250 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
251 {
252 	kfree(adev->uvd.saved_bo);
253 
254 	amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
255 
256 	amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo,
257 			      &adev->uvd.gpu_addr,
258 			      (void **)&adev->uvd.cpu_addr);
259 
260 	amdgpu_ring_fini(&adev->uvd.ring);
261 
262 	release_firmware(adev->uvd.fw);
263 
264 	return 0;
265 }
266 
267 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
268 {
269 	unsigned size;
270 	void *ptr;
271 	int i;
272 
273 	if (adev->uvd.vcpu_bo == NULL)
274 		return 0;
275 
276 	for (i = 0; i < adev->uvd.max_handles; ++i)
277 		if (atomic_read(&adev->uvd.handles[i]))
278 			break;
279 
280 	if (i == AMDGPU_MAX_UVD_HANDLES)
281 		return 0;
282 
283 	cancel_delayed_work_sync(&adev->uvd.idle_work);
284 
285 	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
286 	ptr = adev->uvd.cpu_addr;
287 
288 	adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
289 	if (!adev->uvd.saved_bo)
290 		return -ENOMEM;
291 
292 	memcpy_fromio(adev->uvd.saved_bo, ptr, size);
293 
294 	return 0;
295 }
296 
297 int amdgpu_uvd_resume(struct amdgpu_device *adev)
298 {
299 	unsigned size;
300 	void *ptr;
301 
302 	if (adev->uvd.vcpu_bo == NULL)
303 		return -EINVAL;
304 
305 	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
306 	ptr = adev->uvd.cpu_addr;
307 
308 	if (adev->uvd.saved_bo != NULL) {
309 		memcpy_toio(ptr, adev->uvd.saved_bo, size);
310 		kfree(adev->uvd.saved_bo);
311 		adev->uvd.saved_bo = NULL;
312 	} else {
313 		const struct common_firmware_header *hdr;
314 		unsigned offset;
315 
316 		hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
317 		offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
318 		memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset,
319 			    le32_to_cpu(hdr->ucode_size_bytes));
320 		size -= le32_to_cpu(hdr->ucode_size_bytes);
321 		ptr += le32_to_cpu(hdr->ucode_size_bytes);
322 		memset_io(ptr, 0, size);
323 	}
324 
325 	return 0;
326 }
327 
328 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
329 {
330 	struct amdgpu_ring *ring = &adev->uvd.ring;
331 	int i, r;
332 
333 	for (i = 0; i < adev->uvd.max_handles; ++i) {
334 		uint32_t handle = atomic_read(&adev->uvd.handles[i]);
335 		if (handle != 0 && adev->uvd.filp[i] == filp) {
336 			struct fence *fence;
337 
338 			r = amdgpu_uvd_get_destroy_msg(ring, handle,
339 						       false, &fence);
340 			if (r) {
341 				DRM_ERROR("Error destroying UVD (%d)!\n", r);
342 				continue;
343 			}
344 
345 			fence_wait(fence, false);
346 			fence_put(fence);
347 
348 			adev->uvd.filp[i] = NULL;
349 			atomic_set(&adev->uvd.handles[i], 0);
350 		}
351 	}
352 }
353 
354 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
355 {
356 	int i;
357 	for (i = 0; i < abo->placement.num_placement; ++i) {
358 		abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
359 		abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
360 	}
361 }
362 
363 /**
364  * amdgpu_uvd_cs_pass1 - first parsing round
365  *
366  * @ctx: UVD parser context
367  *
368  * Make sure UVD message and feedback buffers are in VRAM and
369  * nobody is violating an 256MB boundary.
370  */
371 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
372 {
373 	struct amdgpu_bo_va_mapping *mapping;
374 	struct amdgpu_bo *bo;
375 	uint32_t cmd, lo, hi;
376 	uint64_t addr;
377 	int r = 0;
378 
379 	lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
380 	hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
381 	addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
382 
383 	mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
384 	if (mapping == NULL) {
385 		DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
386 		return -EINVAL;
387 	}
388 
389 	if (!ctx->parser->adev->uvd.address_64_bit) {
390 		/* check if it's a message or feedback command */
391 		cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
392 		if (cmd == 0x0 || cmd == 0x3) {
393 			/* yes, force it into VRAM */
394 			uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
395 			amdgpu_ttm_placement_from_domain(bo, domain);
396 		}
397 		amdgpu_uvd_force_into_uvd_segment(bo);
398 
399 		r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
400 	}
401 
402 	return r;
403 }
404 
405 /**
406  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
407  *
408  * @msg: pointer to message structure
409  * @buf_sizes: returned buffer sizes
410  *
411  * Peek into the decode message and calculate the necessary buffer sizes.
412  */
413 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
414 	unsigned buf_sizes[])
415 {
416 	unsigned stream_type = msg[4];
417 	unsigned width = msg[6];
418 	unsigned height = msg[7];
419 	unsigned dpb_size = msg[9];
420 	unsigned pitch = msg[28];
421 	unsigned level = msg[57];
422 
423 	unsigned width_in_mb = width / 16;
424 	unsigned height_in_mb = ALIGN(height / 16, 2);
425 	unsigned fs_in_mb = width_in_mb * height_in_mb;
426 
427 	unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
428 	unsigned min_ctx_size = ~0;
429 
430 	image_size = width * height;
431 	image_size += image_size / 2;
432 	image_size = ALIGN(image_size, 1024);
433 
434 	switch (stream_type) {
435 	case 0: /* H264 */
436 		switch(level) {
437 		case 30:
438 			num_dpb_buffer = 8100 / fs_in_mb;
439 			break;
440 		case 31:
441 			num_dpb_buffer = 18000 / fs_in_mb;
442 			break;
443 		case 32:
444 			num_dpb_buffer = 20480 / fs_in_mb;
445 			break;
446 		case 41:
447 			num_dpb_buffer = 32768 / fs_in_mb;
448 			break;
449 		case 42:
450 			num_dpb_buffer = 34816 / fs_in_mb;
451 			break;
452 		case 50:
453 			num_dpb_buffer = 110400 / fs_in_mb;
454 			break;
455 		case 51:
456 			num_dpb_buffer = 184320 / fs_in_mb;
457 			break;
458 		default:
459 			num_dpb_buffer = 184320 / fs_in_mb;
460 			break;
461 		}
462 		num_dpb_buffer++;
463 		if (num_dpb_buffer > 17)
464 			num_dpb_buffer = 17;
465 
466 		/* reference picture buffer */
467 		min_dpb_size = image_size * num_dpb_buffer;
468 
469 		/* macroblock context buffer */
470 		min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
471 
472 		/* IT surface buffer */
473 		min_dpb_size += width_in_mb * height_in_mb * 32;
474 		break;
475 
476 	case 1: /* VC1 */
477 
478 		/* reference picture buffer */
479 		min_dpb_size = image_size * 3;
480 
481 		/* CONTEXT_BUFFER */
482 		min_dpb_size += width_in_mb * height_in_mb * 128;
483 
484 		/* IT surface buffer */
485 		min_dpb_size += width_in_mb * 64;
486 
487 		/* DB surface buffer */
488 		min_dpb_size += width_in_mb * 128;
489 
490 		/* BP */
491 		tmp = max(width_in_mb, height_in_mb);
492 		min_dpb_size += ALIGN(tmp * 7 * 16, 64);
493 		break;
494 
495 	case 3: /* MPEG2 */
496 
497 		/* reference picture buffer */
498 		min_dpb_size = image_size * 3;
499 		break;
500 
501 	case 4: /* MPEG4 */
502 
503 		/* reference picture buffer */
504 		min_dpb_size = image_size * 3;
505 
506 		/* CM */
507 		min_dpb_size += width_in_mb * height_in_mb * 64;
508 
509 		/* IT surface buffer */
510 		min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
511 		break;
512 
513 	case 7: /* H264 Perf */
514 		switch(level) {
515 		case 30:
516 			num_dpb_buffer = 8100 / fs_in_mb;
517 			break;
518 		case 31:
519 			num_dpb_buffer = 18000 / fs_in_mb;
520 			break;
521 		case 32:
522 			num_dpb_buffer = 20480 / fs_in_mb;
523 			break;
524 		case 41:
525 			num_dpb_buffer = 32768 / fs_in_mb;
526 			break;
527 		case 42:
528 			num_dpb_buffer = 34816 / fs_in_mb;
529 			break;
530 		case 50:
531 			num_dpb_buffer = 110400 / fs_in_mb;
532 			break;
533 		case 51:
534 			num_dpb_buffer = 184320 / fs_in_mb;
535 			break;
536 		default:
537 			num_dpb_buffer = 184320 / fs_in_mb;
538 			break;
539 		}
540 		num_dpb_buffer++;
541 		if (num_dpb_buffer > 17)
542 			num_dpb_buffer = 17;
543 
544 		/* reference picture buffer */
545 		min_dpb_size = image_size * num_dpb_buffer;
546 
547 		if (!adev->uvd.use_ctx_buf){
548 			/* macroblock context buffer */
549 			min_dpb_size +=
550 				width_in_mb * height_in_mb * num_dpb_buffer * 192;
551 
552 			/* IT surface buffer */
553 			min_dpb_size += width_in_mb * height_in_mb * 32;
554 		} else {
555 			/* macroblock context buffer */
556 			min_ctx_size =
557 				width_in_mb * height_in_mb * num_dpb_buffer * 192;
558 		}
559 		break;
560 
561 	case 16: /* H265 */
562 		image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
563 		image_size = ALIGN(image_size, 256);
564 
565 		num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
566 		min_dpb_size = image_size * num_dpb_buffer;
567 		min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
568 					   * 16 * num_dpb_buffer + 52 * 1024;
569 		break;
570 
571 	default:
572 		DRM_ERROR("UVD codec not handled %d!\n", stream_type);
573 		return -EINVAL;
574 	}
575 
576 	if (width > pitch) {
577 		DRM_ERROR("Invalid UVD decoding target pitch!\n");
578 		return -EINVAL;
579 	}
580 
581 	if (dpb_size < min_dpb_size) {
582 		DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
583 			  dpb_size, min_dpb_size);
584 		return -EINVAL;
585 	}
586 
587 	buf_sizes[0x1] = dpb_size;
588 	buf_sizes[0x2] = image_size;
589 	buf_sizes[0x4] = min_ctx_size;
590 	return 0;
591 }
592 
593 /**
594  * amdgpu_uvd_cs_msg - handle UVD message
595  *
596  * @ctx: UVD parser context
597  * @bo: buffer object containing the message
598  * @offset: offset into the buffer object
599  *
600  * Peek into the UVD message and extract the session id.
601  * Make sure that we don't open up to many sessions.
602  */
603 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
604 			     struct amdgpu_bo *bo, unsigned offset)
605 {
606 	struct amdgpu_device *adev = ctx->parser->adev;
607 	int32_t *msg, msg_type, handle;
608 	void *ptr;
609 	long r;
610 	int i;
611 
612 	if (offset & 0x3F) {
613 		DRM_ERROR("UVD messages must be 64 byte aligned!\n");
614 		return -EINVAL;
615 	}
616 
617 	r = amdgpu_bo_kmap(bo, &ptr);
618 	if (r) {
619 		DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
620 		return r;
621 	}
622 
623 	msg = ptr + offset;
624 
625 	msg_type = msg[1];
626 	handle = msg[2];
627 
628 	if (handle == 0) {
629 		DRM_ERROR("Invalid UVD handle!\n");
630 		return -EINVAL;
631 	}
632 
633 	switch (msg_type) {
634 	case 0:
635 		/* it's a create msg, calc image size (width * height) */
636 		amdgpu_bo_kunmap(bo);
637 
638 		/* try to alloc a new handle */
639 		for (i = 0; i < adev->uvd.max_handles; ++i) {
640 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
641 				DRM_ERROR("Handle 0x%x already in use!\n", handle);
642 				return -EINVAL;
643 			}
644 
645 			if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
646 				adev->uvd.filp[i] = ctx->parser->filp;
647 				return 0;
648 			}
649 		}
650 
651 		DRM_ERROR("No more free UVD handles!\n");
652 		return -ENOSPC;
653 
654 	case 1:
655 		/* it's a decode msg, calc buffer sizes */
656 		r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
657 		amdgpu_bo_kunmap(bo);
658 		if (r)
659 			return r;
660 
661 		/* validate the handle */
662 		for (i = 0; i < adev->uvd.max_handles; ++i) {
663 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
664 				if (adev->uvd.filp[i] != ctx->parser->filp) {
665 					DRM_ERROR("UVD handle collision detected!\n");
666 					return -EINVAL;
667 				}
668 				return 0;
669 			}
670 		}
671 
672 		DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
673 		return -ENOENT;
674 
675 	case 2:
676 		/* it's a destroy msg, free the handle */
677 		for (i = 0; i < adev->uvd.max_handles; ++i)
678 			atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
679 		amdgpu_bo_kunmap(bo);
680 		return 0;
681 
682 	default:
683 		DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
684 		return -EINVAL;
685 	}
686 	BUG();
687 	return -EINVAL;
688 }
689 
690 /**
691  * amdgpu_uvd_cs_pass2 - second parsing round
692  *
693  * @ctx: UVD parser context
694  *
695  * Patch buffer addresses, make sure buffer sizes are correct.
696  */
697 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
698 {
699 	struct amdgpu_bo_va_mapping *mapping;
700 	struct amdgpu_bo *bo;
701 	uint32_t cmd, lo, hi;
702 	uint64_t start, end;
703 	uint64_t addr;
704 	int r;
705 
706 	lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
707 	hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
708 	addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
709 
710 	mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
711 	if (mapping == NULL)
712 		return -EINVAL;
713 
714 	start = amdgpu_bo_gpu_offset(bo);
715 
716 	end = (mapping->it.last + 1 - mapping->it.start);
717 	end = end * AMDGPU_GPU_PAGE_SIZE + start;
718 
719 	addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
720 	start += addr;
721 
722 	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
723 			    lower_32_bits(start));
724 	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
725 			    upper_32_bits(start));
726 
727 	cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
728 	if (cmd < 0x4) {
729 		if ((end - start) < ctx->buf_sizes[cmd]) {
730 			DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
731 				  (unsigned)(end - start),
732 				  ctx->buf_sizes[cmd]);
733 			return -EINVAL;
734 		}
735 
736 	} else if (cmd == 0x206) {
737 		if ((end - start) < ctx->buf_sizes[4]) {
738 			DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
739 					  (unsigned)(end - start),
740 					  ctx->buf_sizes[4]);
741 			return -EINVAL;
742 		}
743 	} else if ((cmd != 0x100) && (cmd != 0x204)) {
744 		DRM_ERROR("invalid UVD command %X!\n", cmd);
745 		return -EINVAL;
746 	}
747 
748 	if (!ctx->parser->adev->uvd.address_64_bit) {
749 		if ((start >> 28) != ((end - 1) >> 28)) {
750 			DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
751 				  start, end);
752 			return -EINVAL;
753 		}
754 
755 		if ((cmd == 0 || cmd == 0x3) &&
756 		    (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
757 			DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
758 				  start, end);
759 			return -EINVAL;
760 		}
761 	}
762 
763 	if (cmd == 0) {
764 		ctx->has_msg_cmd = true;
765 		r = amdgpu_uvd_cs_msg(ctx, bo, addr);
766 		if (r)
767 			return r;
768 	} else if (!ctx->has_msg_cmd) {
769 		DRM_ERROR("Message needed before other commands are send!\n");
770 		return -EINVAL;
771 	}
772 
773 	return 0;
774 }
775 
776 /**
777  * amdgpu_uvd_cs_reg - parse register writes
778  *
779  * @ctx: UVD parser context
780  * @cb: callback function
781  *
782  * Parse the register writes, call cb on each complete command.
783  */
784 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
785 			     int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
786 {
787 	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
788 	int i, r;
789 
790 	ctx->idx++;
791 	for (i = 0; i <= ctx->count; ++i) {
792 		unsigned reg = ctx->reg + i;
793 
794 		if (ctx->idx >= ib->length_dw) {
795 			DRM_ERROR("Register command after end of CS!\n");
796 			return -EINVAL;
797 		}
798 
799 		switch (reg) {
800 		case mmUVD_GPCOM_VCPU_DATA0:
801 			ctx->data0 = ctx->idx;
802 			break;
803 		case mmUVD_GPCOM_VCPU_DATA1:
804 			ctx->data1 = ctx->idx;
805 			break;
806 		case mmUVD_GPCOM_VCPU_CMD:
807 			r = cb(ctx);
808 			if (r)
809 				return r;
810 			break;
811 		case mmUVD_ENGINE_CNTL:
812 		case mmUVD_NO_OP:
813 			break;
814 		default:
815 			DRM_ERROR("Invalid reg 0x%X!\n", reg);
816 			return -EINVAL;
817 		}
818 		ctx->idx++;
819 	}
820 	return 0;
821 }
822 
823 /**
824  * amdgpu_uvd_cs_packets - parse UVD packets
825  *
826  * @ctx: UVD parser context
827  * @cb: callback function
828  *
829  * Parse the command stream packets.
830  */
831 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
832 				 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
833 {
834 	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
835 	int r;
836 
837 	for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
838 		uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
839 		unsigned type = CP_PACKET_GET_TYPE(cmd);
840 		switch (type) {
841 		case PACKET_TYPE0:
842 			ctx->reg = CP_PACKET0_GET_REG(cmd);
843 			ctx->count = CP_PACKET_GET_COUNT(cmd);
844 			r = amdgpu_uvd_cs_reg(ctx, cb);
845 			if (r)
846 				return r;
847 			break;
848 		case PACKET_TYPE2:
849 			++ctx->idx;
850 			break;
851 		default:
852 			DRM_ERROR("Unknown packet type %d !\n", type);
853 			return -EINVAL;
854 		}
855 	}
856 	return 0;
857 }
858 
859 /**
860  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
861  *
862  * @parser: Command submission parser context
863  *
864  * Parse the command stream, patch in addresses as necessary.
865  */
866 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
867 {
868 	struct amdgpu_uvd_cs_ctx ctx = {};
869 	unsigned buf_sizes[] = {
870 		[0x00000000]	=	2048,
871 		[0x00000001]	=	0xFFFFFFFF,
872 		[0x00000002]	=	0xFFFFFFFF,
873 		[0x00000003]	=	2048,
874 		[0x00000004]	=	0xFFFFFFFF,
875 	};
876 	struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
877 	int r;
878 
879 	if (ib->length_dw % 16) {
880 		DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
881 			  ib->length_dw);
882 		return -EINVAL;
883 	}
884 
885 	r = amdgpu_cs_sysvm_access_required(parser);
886 	if (r)
887 		return r;
888 
889 	ctx.parser = parser;
890 	ctx.buf_sizes = buf_sizes;
891 	ctx.ib_idx = ib_idx;
892 
893 	/* first round, make sure the buffers are actually in the UVD segment */
894 	r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
895 	if (r)
896 		return r;
897 
898 	/* second round, patch buffer addresses into the command stream */
899 	r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
900 	if (r)
901 		return r;
902 
903 	if (!ctx.has_msg_cmd) {
904 		DRM_ERROR("UVD-IBs need a msg command!\n");
905 		return -EINVAL;
906 	}
907 
908 	return 0;
909 }
910 
911 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
912 			       bool direct, struct fence **fence)
913 {
914 	struct ttm_validate_buffer tv;
915 	struct ww_acquire_ctx ticket;
916 	struct list_head head;
917 	struct amdgpu_job *job;
918 	struct amdgpu_ib *ib;
919 	struct fence *f = NULL;
920 	struct amdgpu_device *adev = ring->adev;
921 	uint64_t addr;
922 	int i, r;
923 
924 	memset(&tv, 0, sizeof(tv));
925 	tv.bo = &bo->tbo;
926 
927 	INIT_LIST_HEAD(&head);
928 	list_add(&tv.head, &head);
929 
930 	r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
931 	if (r)
932 		return r;
933 
934 	if (!bo->adev->uvd.address_64_bit) {
935 		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
936 		amdgpu_uvd_force_into_uvd_segment(bo);
937 	}
938 
939 	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
940 	if (r)
941 		goto err;
942 
943 	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
944 	if (r)
945 		goto err;
946 
947 	ib = &job->ibs[0];
948 	addr = amdgpu_bo_gpu_offset(bo);
949 	ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
950 	ib->ptr[1] = addr;
951 	ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
952 	ib->ptr[3] = addr >> 32;
953 	ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
954 	ib->ptr[5] = 0;
955 	for (i = 6; i < 16; i += 2) {
956 		ib->ptr[i] = PACKET0(mmUVD_NO_OP, 0);
957 		ib->ptr[i+1] = 0;
958 	}
959 	ib->length_dw = 16;
960 
961 	if (direct) {
962 		r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
963 		job->fence = fence_get(f);
964 		if (r)
965 			goto err_free;
966 
967 		amdgpu_job_free(job);
968 	} else {
969 		r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
970 				      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
971 		if (r)
972 			goto err_free;
973 	}
974 
975 	ttm_eu_fence_buffer_objects(&ticket, &head, f);
976 
977 	if (fence)
978 		*fence = fence_get(f);
979 	amdgpu_bo_unref(&bo);
980 	fence_put(f);
981 
982 	return 0;
983 
984 err_free:
985 	amdgpu_job_free(job);
986 
987 err:
988 	ttm_eu_backoff_reservation(&ticket, &head);
989 	return r;
990 }
991 
992 /* multiple fence commands without any stream commands in between can
993    crash the vcpu so just try to emmit a dummy create/destroy msg to
994    avoid this */
995 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
996 			      struct fence **fence)
997 {
998 	struct amdgpu_device *adev = ring->adev;
999 	struct amdgpu_bo *bo;
1000 	uint32_t *msg;
1001 	int r, i;
1002 
1003 	r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1004 			     AMDGPU_GEM_DOMAIN_VRAM,
1005 			     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1006 			     NULL, NULL, &bo);
1007 	if (r)
1008 		return r;
1009 
1010 	r = amdgpu_bo_reserve(bo, false);
1011 	if (r) {
1012 		amdgpu_bo_unref(&bo);
1013 		return r;
1014 	}
1015 
1016 	r = amdgpu_bo_kmap(bo, (void **)&msg);
1017 	if (r) {
1018 		amdgpu_bo_unreserve(bo);
1019 		amdgpu_bo_unref(&bo);
1020 		return r;
1021 	}
1022 
1023 	/* stitch together an UVD create msg */
1024 	msg[0] = cpu_to_le32(0x00000de4);
1025 	msg[1] = cpu_to_le32(0x00000000);
1026 	msg[2] = cpu_to_le32(handle);
1027 	msg[3] = cpu_to_le32(0x00000000);
1028 	msg[4] = cpu_to_le32(0x00000000);
1029 	msg[5] = cpu_to_le32(0x00000000);
1030 	msg[6] = cpu_to_le32(0x00000000);
1031 	msg[7] = cpu_to_le32(0x00000780);
1032 	msg[8] = cpu_to_le32(0x00000440);
1033 	msg[9] = cpu_to_le32(0x00000000);
1034 	msg[10] = cpu_to_le32(0x01b37000);
1035 	for (i = 11; i < 1024; ++i)
1036 		msg[i] = cpu_to_le32(0x0);
1037 
1038 	amdgpu_bo_kunmap(bo);
1039 	amdgpu_bo_unreserve(bo);
1040 
1041 	return amdgpu_uvd_send_msg(ring, bo, true, fence);
1042 }
1043 
1044 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1045 			       bool direct, struct fence **fence)
1046 {
1047 	struct amdgpu_device *adev = ring->adev;
1048 	struct amdgpu_bo *bo;
1049 	uint32_t *msg;
1050 	int r, i;
1051 
1052 	r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1053 			     AMDGPU_GEM_DOMAIN_VRAM,
1054 			     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1055 			     NULL, NULL, &bo);
1056 	if (r)
1057 		return r;
1058 
1059 	r = amdgpu_bo_reserve(bo, false);
1060 	if (r) {
1061 		amdgpu_bo_unref(&bo);
1062 		return r;
1063 	}
1064 
1065 	r = amdgpu_bo_kmap(bo, (void **)&msg);
1066 	if (r) {
1067 		amdgpu_bo_unreserve(bo);
1068 		amdgpu_bo_unref(&bo);
1069 		return r;
1070 	}
1071 
1072 	/* stitch together an UVD destroy msg */
1073 	msg[0] = cpu_to_le32(0x00000de4);
1074 	msg[1] = cpu_to_le32(0x00000002);
1075 	msg[2] = cpu_to_le32(handle);
1076 	msg[3] = cpu_to_le32(0x00000000);
1077 	for (i = 4; i < 1024; ++i)
1078 		msg[i] = cpu_to_le32(0x0);
1079 
1080 	amdgpu_bo_kunmap(bo);
1081 	amdgpu_bo_unreserve(bo);
1082 
1083 	return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1084 }
1085 
1086 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1087 {
1088 	struct amdgpu_device *adev =
1089 		container_of(work, struct amdgpu_device, uvd.idle_work.work);
1090 	unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1091 
1092 	if (fences == 0) {
1093 		if (adev->pm.dpm_enabled) {
1094 			amdgpu_dpm_enable_uvd(adev, false);
1095 		} else {
1096 			amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1097 		}
1098 	} else {
1099 		schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1100 	}
1101 }
1102 
1103 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1104 {
1105 	struct amdgpu_device *adev = ring->adev;
1106 	bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1107 
1108 	if (set_clocks) {
1109 		if (adev->pm.dpm_enabled) {
1110 			amdgpu_dpm_enable_uvd(adev, true);
1111 		} else {
1112 			amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1113 		}
1114 	}
1115 }
1116 
1117 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1118 {
1119 	schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1120 }
1121 
1122 /**
1123  * amdgpu_uvd_ring_test_ib - test ib execution
1124  *
1125  * @ring: amdgpu_ring pointer
1126  *
1127  * Test if we can successfully execute an IB
1128  */
1129 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1130 {
1131 	struct fence *fence;
1132 	long r;
1133 
1134 	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1135 	if (r) {
1136 		DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1137 		goto error;
1138 	}
1139 
1140 	r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1141 	if (r) {
1142 		DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1143 		goto error;
1144 	}
1145 
1146 	r = fence_wait_timeout(fence, false, timeout);
1147 	if (r == 0) {
1148 		DRM_ERROR("amdgpu: IB test timed out.\n");
1149 		r = -ETIMEDOUT;
1150 	} else if (r < 0) {
1151 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1152 	} else {
1153 		DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
1154 		r = 0;
1155 	}
1156 
1157 	fence_put(fence);
1158 
1159 error:
1160 	return r;
1161 }
1162