1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 #include <drm/drm_drv.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_pm.h" 39 #include "amdgpu_uvd.h" 40 #include "cikd.h" 41 #include "uvd/uvd_4_2_d.h" 42 43 #include "amdgpu_ras.h" 44 45 /* 1 second timeout */ 46 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 47 48 /* Firmware versions for VI */ 49 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 50 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 51 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 52 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 53 54 /* Polaris10/11 firmware version */ 55 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 56 57 /* Firmware Names */ 58 #ifdef CONFIG_DRM_AMDGPU_SI 59 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin" 60 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin" 61 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin" 62 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin" 63 #endif 64 #ifdef CONFIG_DRM_AMDGPU_CIK 65 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 66 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 67 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 68 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 69 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 70 #endif 71 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 72 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 73 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 74 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 75 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 76 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 77 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 78 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 79 80 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 81 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 82 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 83 84 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 85 #define UVD_GPCOM_VCPU_CMD 0x03c3 86 #define UVD_GPCOM_VCPU_DATA0 0x03c4 87 #define UVD_GPCOM_VCPU_DATA1 0x03c5 88 #define UVD_NO_OP 0x03ff 89 #define UVD_BASE_SI 0x3800 90 91 /* 92 * amdgpu_uvd_cs_ctx - Command submission parser context 93 * 94 * Used for emulating virtual memory support on UVD 4.2. 95 */ 96 struct amdgpu_uvd_cs_ctx { 97 struct amdgpu_cs_parser *parser; 98 unsigned reg, count; 99 unsigned data0, data1; 100 unsigned idx; 101 unsigned ib_idx; 102 103 /* does the IB has a msg command */ 104 bool has_msg_cmd; 105 106 /* minimum buffer sizes */ 107 unsigned *buf_sizes; 108 }; 109 110 #ifdef CONFIG_DRM_AMDGPU_SI 111 MODULE_FIRMWARE(FIRMWARE_TAHITI); 112 MODULE_FIRMWARE(FIRMWARE_VERDE); 113 MODULE_FIRMWARE(FIRMWARE_PITCAIRN); 114 MODULE_FIRMWARE(FIRMWARE_OLAND); 115 #endif 116 #ifdef CONFIG_DRM_AMDGPU_CIK 117 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 118 MODULE_FIRMWARE(FIRMWARE_KABINI); 119 MODULE_FIRMWARE(FIRMWARE_KAVERI); 120 MODULE_FIRMWARE(FIRMWARE_HAWAII); 121 MODULE_FIRMWARE(FIRMWARE_MULLINS); 122 #endif 123 MODULE_FIRMWARE(FIRMWARE_TONGA); 124 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 125 MODULE_FIRMWARE(FIRMWARE_FIJI); 126 MODULE_FIRMWARE(FIRMWARE_STONEY); 127 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 128 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 129 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 130 MODULE_FIRMWARE(FIRMWARE_VEGAM); 131 132 MODULE_FIRMWARE(FIRMWARE_VEGA10); 133 MODULE_FIRMWARE(FIRMWARE_VEGA12); 134 MODULE_FIRMWARE(FIRMWARE_VEGA20); 135 136 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 137 138 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 139 { 140 unsigned long bo_size; 141 const char *fw_name; 142 const struct common_firmware_header *hdr; 143 unsigned family_id; 144 int i, j, r; 145 146 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 147 148 switch (adev->asic_type) { 149 #ifdef CONFIG_DRM_AMDGPU_SI 150 case CHIP_TAHITI: 151 fw_name = FIRMWARE_TAHITI; 152 break; 153 case CHIP_VERDE: 154 fw_name = FIRMWARE_VERDE; 155 break; 156 case CHIP_PITCAIRN: 157 fw_name = FIRMWARE_PITCAIRN; 158 break; 159 case CHIP_OLAND: 160 fw_name = FIRMWARE_OLAND; 161 break; 162 #endif 163 #ifdef CONFIG_DRM_AMDGPU_CIK 164 case CHIP_BONAIRE: 165 fw_name = FIRMWARE_BONAIRE; 166 break; 167 case CHIP_KABINI: 168 fw_name = FIRMWARE_KABINI; 169 break; 170 case CHIP_KAVERI: 171 fw_name = FIRMWARE_KAVERI; 172 break; 173 case CHIP_HAWAII: 174 fw_name = FIRMWARE_HAWAII; 175 break; 176 case CHIP_MULLINS: 177 fw_name = FIRMWARE_MULLINS; 178 break; 179 #endif 180 case CHIP_TONGA: 181 fw_name = FIRMWARE_TONGA; 182 break; 183 case CHIP_FIJI: 184 fw_name = FIRMWARE_FIJI; 185 break; 186 case CHIP_CARRIZO: 187 fw_name = FIRMWARE_CARRIZO; 188 break; 189 case CHIP_STONEY: 190 fw_name = FIRMWARE_STONEY; 191 break; 192 case CHIP_POLARIS10: 193 fw_name = FIRMWARE_POLARIS10; 194 break; 195 case CHIP_POLARIS11: 196 fw_name = FIRMWARE_POLARIS11; 197 break; 198 case CHIP_POLARIS12: 199 fw_name = FIRMWARE_POLARIS12; 200 break; 201 case CHIP_VEGA10: 202 fw_name = FIRMWARE_VEGA10; 203 break; 204 case CHIP_VEGA12: 205 fw_name = FIRMWARE_VEGA12; 206 break; 207 case CHIP_VEGAM: 208 fw_name = FIRMWARE_VEGAM; 209 break; 210 case CHIP_VEGA20: 211 fw_name = FIRMWARE_VEGA20; 212 break; 213 default: 214 return -EINVAL; 215 } 216 217 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 218 if (r) { 219 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 220 fw_name); 221 return r; 222 } 223 224 r = amdgpu_ucode_validate(adev->uvd.fw); 225 if (r) { 226 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 227 fw_name); 228 release_firmware(adev->uvd.fw); 229 adev->uvd.fw = NULL; 230 return r; 231 } 232 233 /* Set the default UVD handles that the firmware can handle */ 234 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 235 236 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 237 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 238 239 if (adev->asic_type < CHIP_VEGA20) { 240 unsigned version_major, version_minor; 241 242 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 243 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 244 DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n", 245 version_major, version_minor, family_id); 246 247 /* 248 * Limit the number of UVD handles depending on microcode major 249 * and minor versions. The firmware version which has 40 UVD 250 * instances support is 1.80. So all subsequent versions should 251 * also have the same support. 252 */ 253 if ((version_major > 0x01) || 254 ((version_major == 0x01) && (version_minor >= 0x50))) 255 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 256 257 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 258 (family_id << 8)); 259 260 if ((adev->asic_type == CHIP_POLARIS10 || 261 adev->asic_type == CHIP_POLARIS11) && 262 (adev->uvd.fw_version < FW_1_66_16)) 263 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n", 264 version_major, version_minor); 265 } else { 266 unsigned int enc_major, enc_minor, dec_minor; 267 268 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 269 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 270 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 271 DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", 272 enc_major, enc_minor, dec_minor, family_id); 273 274 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 275 276 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 277 } 278 279 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 280 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 281 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 282 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 283 284 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 285 if (adev->uvd.harvest_config & (1 << j)) 286 continue; 287 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 288 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo, 289 &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr); 290 if (r) { 291 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 292 return r; 293 } 294 } 295 296 for (i = 0; i < adev->uvd.max_handles; ++i) { 297 atomic_set(&adev->uvd.handles[i], 0); 298 adev->uvd.filp[i] = NULL; 299 } 300 301 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 302 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 303 adev->uvd.address_64_bit = true; 304 305 switch (adev->asic_type) { 306 case CHIP_TONGA: 307 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 308 break; 309 case CHIP_CARRIZO: 310 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 311 break; 312 case CHIP_FIJI: 313 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 314 break; 315 case CHIP_STONEY: 316 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 317 break; 318 default: 319 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 320 } 321 322 return 0; 323 } 324 325 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 326 { 327 int i, j; 328 329 cancel_delayed_work_sync(&adev->uvd.idle_work); 330 drm_sched_entity_destroy(&adev->uvd.entity); 331 332 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 333 if (adev->uvd.harvest_config & (1 << j)) 334 continue; 335 kvfree(adev->uvd.inst[j].saved_bo); 336 337 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 338 &adev->uvd.inst[j].gpu_addr, 339 (void **)&adev->uvd.inst[j].cpu_addr); 340 341 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 342 343 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 344 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 345 } 346 release_firmware(adev->uvd.fw); 347 348 return 0; 349 } 350 351 /** 352 * amdgpu_uvd_entity_init - init entity 353 * 354 * @adev: amdgpu_device pointer 355 * 356 */ 357 int amdgpu_uvd_entity_init(struct amdgpu_device *adev) 358 { 359 struct amdgpu_ring *ring; 360 struct drm_gpu_scheduler *sched; 361 int r; 362 363 ring = &adev->uvd.inst[0].ring; 364 sched = &ring->sched; 365 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 366 &sched, 1, NULL); 367 if (r) { 368 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 369 return r; 370 } 371 372 return 0; 373 } 374 375 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 376 { 377 unsigned size; 378 void *ptr; 379 int i, j, idx; 380 bool in_ras_intr = amdgpu_ras_intr_triggered(); 381 382 cancel_delayed_work_sync(&adev->uvd.idle_work); 383 384 /* only valid for physical mode */ 385 if (adev->asic_type < CHIP_POLARIS10) { 386 for (i = 0; i < adev->uvd.max_handles; ++i) 387 if (atomic_read(&adev->uvd.handles[i])) 388 break; 389 390 if (i == adev->uvd.max_handles) 391 return 0; 392 } 393 394 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 395 if (adev->uvd.harvest_config & (1 << j)) 396 continue; 397 if (adev->uvd.inst[j].vcpu_bo == NULL) 398 continue; 399 400 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 401 ptr = adev->uvd.inst[j].cpu_addr; 402 403 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 404 if (!adev->uvd.inst[j].saved_bo) 405 return -ENOMEM; 406 407 if (drm_dev_enter(&adev->ddev, &idx)) { 408 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 409 if (in_ras_intr) 410 memset(adev->uvd.inst[j].saved_bo, 0, size); 411 else 412 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 413 414 drm_dev_exit(idx); 415 } 416 } 417 418 if (in_ras_intr) 419 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 420 421 return 0; 422 } 423 424 int amdgpu_uvd_resume(struct amdgpu_device *adev) 425 { 426 unsigned size; 427 void *ptr; 428 int i, idx; 429 430 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 431 if (adev->uvd.harvest_config & (1 << i)) 432 continue; 433 if (adev->uvd.inst[i].vcpu_bo == NULL) 434 return -EINVAL; 435 436 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 437 ptr = adev->uvd.inst[i].cpu_addr; 438 439 if (adev->uvd.inst[i].saved_bo != NULL) { 440 if (drm_dev_enter(&adev->ddev, &idx)) { 441 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 442 drm_dev_exit(idx); 443 } 444 kvfree(adev->uvd.inst[i].saved_bo); 445 adev->uvd.inst[i].saved_bo = NULL; 446 } else { 447 const struct common_firmware_header *hdr; 448 unsigned offset; 449 450 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 451 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 452 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 453 if (drm_dev_enter(&adev->ddev, &idx)) { 454 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 455 le32_to_cpu(hdr->ucode_size_bytes)); 456 drm_dev_exit(idx); 457 } 458 size -= le32_to_cpu(hdr->ucode_size_bytes); 459 ptr += le32_to_cpu(hdr->ucode_size_bytes); 460 } 461 memset_io(ptr, 0, size); 462 /* to restore uvd fence seq */ 463 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); 464 } 465 } 466 return 0; 467 } 468 469 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 470 { 471 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 472 int i, r; 473 474 for (i = 0; i < adev->uvd.max_handles; ++i) { 475 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 476 477 if (handle != 0 && adev->uvd.filp[i] == filp) { 478 struct dma_fence *fence; 479 480 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 481 &fence); 482 if (r) { 483 DRM_ERROR("Error destroying UVD %d!\n", r); 484 continue; 485 } 486 487 dma_fence_wait(fence, false); 488 dma_fence_put(fence); 489 490 adev->uvd.filp[i] = NULL; 491 atomic_set(&adev->uvd.handles[i], 0); 492 } 493 } 494 } 495 496 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 497 { 498 int i; 499 for (i = 0; i < abo->placement.num_placement; ++i) { 500 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 501 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 502 } 503 } 504 505 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 506 { 507 uint32_t lo, hi; 508 uint64_t addr; 509 510 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 511 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 512 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 513 514 return addr; 515 } 516 517 /** 518 * amdgpu_uvd_cs_pass1 - first parsing round 519 * 520 * @ctx: UVD parser context 521 * 522 * Make sure UVD message and feedback buffers are in VRAM and 523 * nobody is violating an 256MB boundary. 524 */ 525 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 526 { 527 struct ttm_operation_ctx tctx = { false, false }; 528 struct amdgpu_bo_va_mapping *mapping; 529 struct amdgpu_bo *bo; 530 uint32_t cmd; 531 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 532 int r = 0; 533 534 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 535 if (r) { 536 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 537 return r; 538 } 539 540 if (!ctx->parser->adev->uvd.address_64_bit) { 541 /* check if it's a message or feedback command */ 542 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 543 if (cmd == 0x0 || cmd == 0x3) { 544 /* yes, force it into VRAM */ 545 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 546 amdgpu_bo_placement_from_domain(bo, domain); 547 } 548 amdgpu_uvd_force_into_uvd_segment(bo); 549 550 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 551 } 552 553 return r; 554 } 555 556 /** 557 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 558 * 559 * @adev: amdgpu_device pointer 560 * @msg: pointer to message structure 561 * @buf_sizes: placeholder to put the different buffer lengths 562 * 563 * Peek into the decode message and calculate the necessary buffer sizes. 564 */ 565 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 566 unsigned buf_sizes[]) 567 { 568 unsigned stream_type = msg[4]; 569 unsigned width = msg[6]; 570 unsigned height = msg[7]; 571 unsigned dpb_size = msg[9]; 572 unsigned pitch = msg[28]; 573 unsigned level = msg[57]; 574 575 unsigned width_in_mb = width / 16; 576 unsigned height_in_mb = ALIGN(height / 16, 2); 577 unsigned fs_in_mb = width_in_mb * height_in_mb; 578 579 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 580 unsigned min_ctx_size = ~0; 581 582 image_size = width * height; 583 image_size += image_size / 2; 584 image_size = ALIGN(image_size, 1024); 585 586 switch (stream_type) { 587 case 0: /* H264 */ 588 switch(level) { 589 case 30: 590 num_dpb_buffer = 8100 / fs_in_mb; 591 break; 592 case 31: 593 num_dpb_buffer = 18000 / fs_in_mb; 594 break; 595 case 32: 596 num_dpb_buffer = 20480 / fs_in_mb; 597 break; 598 case 41: 599 num_dpb_buffer = 32768 / fs_in_mb; 600 break; 601 case 42: 602 num_dpb_buffer = 34816 / fs_in_mb; 603 break; 604 case 50: 605 num_dpb_buffer = 110400 / fs_in_mb; 606 break; 607 case 51: 608 num_dpb_buffer = 184320 / fs_in_mb; 609 break; 610 default: 611 num_dpb_buffer = 184320 / fs_in_mb; 612 break; 613 } 614 num_dpb_buffer++; 615 if (num_dpb_buffer > 17) 616 num_dpb_buffer = 17; 617 618 /* reference picture buffer */ 619 min_dpb_size = image_size * num_dpb_buffer; 620 621 /* macroblock context buffer */ 622 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 623 624 /* IT surface buffer */ 625 min_dpb_size += width_in_mb * height_in_mb * 32; 626 break; 627 628 case 1: /* VC1 */ 629 630 /* reference picture buffer */ 631 min_dpb_size = image_size * 3; 632 633 /* CONTEXT_BUFFER */ 634 min_dpb_size += width_in_mb * height_in_mb * 128; 635 636 /* IT surface buffer */ 637 min_dpb_size += width_in_mb * 64; 638 639 /* DB surface buffer */ 640 min_dpb_size += width_in_mb * 128; 641 642 /* BP */ 643 tmp = max(width_in_mb, height_in_mb); 644 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 645 break; 646 647 case 3: /* MPEG2 */ 648 649 /* reference picture buffer */ 650 min_dpb_size = image_size * 3; 651 break; 652 653 case 4: /* MPEG4 */ 654 655 /* reference picture buffer */ 656 min_dpb_size = image_size * 3; 657 658 /* CM */ 659 min_dpb_size += width_in_mb * height_in_mb * 64; 660 661 /* IT surface buffer */ 662 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 663 break; 664 665 case 7: /* H264 Perf */ 666 switch(level) { 667 case 30: 668 num_dpb_buffer = 8100 / fs_in_mb; 669 break; 670 case 31: 671 num_dpb_buffer = 18000 / fs_in_mb; 672 break; 673 case 32: 674 num_dpb_buffer = 20480 / fs_in_mb; 675 break; 676 case 41: 677 num_dpb_buffer = 32768 / fs_in_mb; 678 break; 679 case 42: 680 num_dpb_buffer = 34816 / fs_in_mb; 681 break; 682 case 50: 683 num_dpb_buffer = 110400 / fs_in_mb; 684 break; 685 case 51: 686 num_dpb_buffer = 184320 / fs_in_mb; 687 break; 688 default: 689 num_dpb_buffer = 184320 / fs_in_mb; 690 break; 691 } 692 num_dpb_buffer++; 693 if (num_dpb_buffer > 17) 694 num_dpb_buffer = 17; 695 696 /* reference picture buffer */ 697 min_dpb_size = image_size * num_dpb_buffer; 698 699 if (!adev->uvd.use_ctx_buf){ 700 /* macroblock context buffer */ 701 min_dpb_size += 702 width_in_mb * height_in_mb * num_dpb_buffer * 192; 703 704 /* IT surface buffer */ 705 min_dpb_size += width_in_mb * height_in_mb * 32; 706 } else { 707 /* macroblock context buffer */ 708 min_ctx_size = 709 width_in_mb * height_in_mb * num_dpb_buffer * 192; 710 } 711 break; 712 713 case 8: /* MJPEG */ 714 min_dpb_size = 0; 715 break; 716 717 case 16: /* H265 */ 718 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 719 image_size = ALIGN(image_size, 256); 720 721 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 722 min_dpb_size = image_size * num_dpb_buffer; 723 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 724 * 16 * num_dpb_buffer + 52 * 1024; 725 break; 726 727 default: 728 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 729 return -EINVAL; 730 } 731 732 if (width > pitch) { 733 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 734 return -EINVAL; 735 } 736 737 if (dpb_size < min_dpb_size) { 738 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 739 dpb_size, min_dpb_size); 740 return -EINVAL; 741 } 742 743 buf_sizes[0x1] = dpb_size; 744 buf_sizes[0x2] = image_size; 745 buf_sizes[0x4] = min_ctx_size; 746 /* store image width to adjust nb memory pstate */ 747 adev->uvd.decode_image_width = width; 748 return 0; 749 } 750 751 /** 752 * amdgpu_uvd_cs_msg - handle UVD message 753 * 754 * @ctx: UVD parser context 755 * @bo: buffer object containing the message 756 * @offset: offset into the buffer object 757 * 758 * Peek into the UVD message and extract the session id. 759 * Make sure that we don't open up to many sessions. 760 */ 761 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 762 struct amdgpu_bo *bo, unsigned offset) 763 { 764 struct amdgpu_device *adev = ctx->parser->adev; 765 int32_t *msg, msg_type, handle; 766 void *ptr; 767 long r; 768 int i; 769 770 if (offset & 0x3F) { 771 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 772 return -EINVAL; 773 } 774 775 r = amdgpu_bo_kmap(bo, &ptr); 776 if (r) { 777 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 778 return r; 779 } 780 781 msg = ptr + offset; 782 783 msg_type = msg[1]; 784 handle = msg[2]; 785 786 if (handle == 0) { 787 DRM_ERROR("Invalid UVD handle!\n"); 788 return -EINVAL; 789 } 790 791 switch (msg_type) { 792 case 0: 793 /* it's a create msg, calc image size (width * height) */ 794 amdgpu_bo_kunmap(bo); 795 796 /* try to alloc a new handle */ 797 for (i = 0; i < adev->uvd.max_handles; ++i) { 798 if (atomic_read(&adev->uvd.handles[i]) == handle) { 799 DRM_ERROR(")Handle 0x%x already in use!\n", 800 handle); 801 return -EINVAL; 802 } 803 804 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 805 adev->uvd.filp[i] = ctx->parser->filp; 806 return 0; 807 } 808 } 809 810 DRM_ERROR("No more free UVD handles!\n"); 811 return -ENOSPC; 812 813 case 1: 814 /* it's a decode msg, calc buffer sizes */ 815 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 816 amdgpu_bo_kunmap(bo); 817 if (r) 818 return r; 819 820 /* validate the handle */ 821 for (i = 0; i < adev->uvd.max_handles; ++i) { 822 if (atomic_read(&adev->uvd.handles[i]) == handle) { 823 if (adev->uvd.filp[i] != ctx->parser->filp) { 824 DRM_ERROR("UVD handle collision detected!\n"); 825 return -EINVAL; 826 } 827 return 0; 828 } 829 } 830 831 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 832 return -ENOENT; 833 834 case 2: 835 /* it's a destroy msg, free the handle */ 836 for (i = 0; i < adev->uvd.max_handles; ++i) 837 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 838 amdgpu_bo_kunmap(bo); 839 return 0; 840 841 default: 842 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 843 } 844 845 return -EINVAL; 846 } 847 848 /** 849 * amdgpu_uvd_cs_pass2 - second parsing round 850 * 851 * @ctx: UVD parser context 852 * 853 * Patch buffer addresses, make sure buffer sizes are correct. 854 */ 855 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 856 { 857 struct amdgpu_bo_va_mapping *mapping; 858 struct amdgpu_bo *bo; 859 uint32_t cmd; 860 uint64_t start, end; 861 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 862 int r; 863 864 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 865 if (r) { 866 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 867 return r; 868 } 869 870 start = amdgpu_bo_gpu_offset(bo); 871 872 end = (mapping->last + 1 - mapping->start); 873 end = end * AMDGPU_GPU_PAGE_SIZE + start; 874 875 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 876 start += addr; 877 878 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 879 lower_32_bits(start)); 880 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 881 upper_32_bits(start)); 882 883 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 884 if (cmd < 0x4) { 885 if ((end - start) < ctx->buf_sizes[cmd]) { 886 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 887 (unsigned)(end - start), 888 ctx->buf_sizes[cmd]); 889 return -EINVAL; 890 } 891 892 } else if (cmd == 0x206) { 893 if ((end - start) < ctx->buf_sizes[4]) { 894 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 895 (unsigned)(end - start), 896 ctx->buf_sizes[4]); 897 return -EINVAL; 898 } 899 } else if ((cmd != 0x100) && (cmd != 0x204)) { 900 DRM_ERROR("invalid UVD command %X!\n", cmd); 901 return -EINVAL; 902 } 903 904 if (!ctx->parser->adev->uvd.address_64_bit) { 905 if ((start >> 28) != ((end - 1) >> 28)) { 906 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 907 start, end); 908 return -EINVAL; 909 } 910 911 if ((cmd == 0 || cmd == 0x3) && 912 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 913 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 914 start, end); 915 return -EINVAL; 916 } 917 } 918 919 if (cmd == 0) { 920 ctx->has_msg_cmd = true; 921 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 922 if (r) 923 return r; 924 } else if (!ctx->has_msg_cmd) { 925 DRM_ERROR("Message needed before other commands are send!\n"); 926 return -EINVAL; 927 } 928 929 return 0; 930 } 931 932 /** 933 * amdgpu_uvd_cs_reg - parse register writes 934 * 935 * @ctx: UVD parser context 936 * @cb: callback function 937 * 938 * Parse the register writes, call cb on each complete command. 939 */ 940 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 941 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 942 { 943 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 944 int i, r; 945 946 ctx->idx++; 947 for (i = 0; i <= ctx->count; ++i) { 948 unsigned reg = ctx->reg + i; 949 950 if (ctx->idx >= ib->length_dw) { 951 DRM_ERROR("Register command after end of CS!\n"); 952 return -EINVAL; 953 } 954 955 switch (reg) { 956 case mmUVD_GPCOM_VCPU_DATA0: 957 ctx->data0 = ctx->idx; 958 break; 959 case mmUVD_GPCOM_VCPU_DATA1: 960 ctx->data1 = ctx->idx; 961 break; 962 case mmUVD_GPCOM_VCPU_CMD: 963 r = cb(ctx); 964 if (r) 965 return r; 966 break; 967 case mmUVD_ENGINE_CNTL: 968 case mmUVD_NO_OP: 969 break; 970 default: 971 DRM_ERROR("Invalid reg 0x%X!\n", reg); 972 return -EINVAL; 973 } 974 ctx->idx++; 975 } 976 return 0; 977 } 978 979 /** 980 * amdgpu_uvd_cs_packets - parse UVD packets 981 * 982 * @ctx: UVD parser context 983 * @cb: callback function 984 * 985 * Parse the command stream packets. 986 */ 987 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 988 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 989 { 990 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 991 int r; 992 993 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 994 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 995 unsigned type = CP_PACKET_GET_TYPE(cmd); 996 switch (type) { 997 case PACKET_TYPE0: 998 ctx->reg = CP_PACKET0_GET_REG(cmd); 999 ctx->count = CP_PACKET_GET_COUNT(cmd); 1000 r = amdgpu_uvd_cs_reg(ctx, cb); 1001 if (r) 1002 return r; 1003 break; 1004 case PACKET_TYPE2: 1005 ++ctx->idx; 1006 break; 1007 default: 1008 DRM_ERROR("Unknown packet type %d !\n", type); 1009 return -EINVAL; 1010 } 1011 } 1012 return 0; 1013 } 1014 1015 /** 1016 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 1017 * 1018 * @parser: Command submission parser context 1019 * @ib_idx: Which indirect buffer to use 1020 * 1021 * Parse the command stream, patch in addresses as necessary. 1022 */ 1023 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 1024 { 1025 struct amdgpu_uvd_cs_ctx ctx = {}; 1026 unsigned buf_sizes[] = { 1027 [0x00000000] = 2048, 1028 [0x00000001] = 0xFFFFFFFF, 1029 [0x00000002] = 0xFFFFFFFF, 1030 [0x00000003] = 2048, 1031 [0x00000004] = 0xFFFFFFFF, 1032 }; 1033 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 1034 int r; 1035 1036 parser->job->vm = NULL; 1037 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 1038 1039 if (ib->length_dw % 16) { 1040 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1041 ib->length_dw); 1042 return -EINVAL; 1043 } 1044 1045 ctx.parser = parser; 1046 ctx.buf_sizes = buf_sizes; 1047 ctx.ib_idx = ib_idx; 1048 1049 /* first round only required on chips without UVD 64 bit address support */ 1050 if (!parser->adev->uvd.address_64_bit) { 1051 /* first round, make sure the buffers are actually in the UVD segment */ 1052 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1053 if (r) 1054 return r; 1055 } 1056 1057 /* second round, patch buffer addresses into the command stream */ 1058 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1059 if (r) 1060 return r; 1061 1062 if (!ctx.has_msg_cmd) { 1063 DRM_ERROR("UVD-IBs need a msg command!\n"); 1064 return -EINVAL; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1071 bool direct, struct dma_fence **fence) 1072 { 1073 struct amdgpu_device *adev = ring->adev; 1074 struct dma_fence *f = NULL; 1075 struct amdgpu_job *job; 1076 struct amdgpu_ib *ib; 1077 uint32_t data[4]; 1078 uint64_t addr; 1079 long r; 1080 int i; 1081 unsigned offset_idx = 0; 1082 unsigned offset[3] = { UVD_BASE_SI, 0, 0 }; 1083 1084 amdgpu_bo_kunmap(bo); 1085 amdgpu_bo_unpin(bo); 1086 1087 if (!ring->adev->uvd.address_64_bit) { 1088 struct ttm_operation_ctx ctx = { true, false }; 1089 1090 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 1091 amdgpu_uvd_force_into_uvd_segment(bo); 1092 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1093 if (r) 1094 goto err; 1095 } 1096 1097 r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT : 1098 AMDGPU_IB_POOL_DELAYED, &job); 1099 if (r) 1100 goto err; 1101 1102 if (adev->asic_type >= CHIP_VEGA10) { 1103 offset_idx = 1 + ring->me; 1104 offset[1] = adev->reg_offset[UVD_HWIP][0][1]; 1105 offset[2] = adev->reg_offset[UVD_HWIP][1][1]; 1106 } 1107 1108 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0); 1109 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0); 1110 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0); 1111 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); 1112 1113 ib = &job->ibs[0]; 1114 addr = amdgpu_bo_gpu_offset(bo); 1115 ib->ptr[0] = data[0]; 1116 ib->ptr[1] = addr; 1117 ib->ptr[2] = data[1]; 1118 ib->ptr[3] = addr >> 32; 1119 ib->ptr[4] = data[2]; 1120 ib->ptr[5] = 0; 1121 for (i = 6; i < 16; i += 2) { 1122 ib->ptr[i] = data[3]; 1123 ib->ptr[i+1] = 0; 1124 } 1125 ib->length_dw = 16; 1126 1127 if (direct) { 1128 r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false, 1129 msecs_to_jiffies(10)); 1130 if (r == 0) 1131 r = -ETIMEDOUT; 1132 if (r < 0) 1133 goto err_free; 1134 1135 r = amdgpu_job_submit_direct(job, ring, &f); 1136 if (r) 1137 goto err_free; 1138 } else { 1139 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv, 1140 AMDGPU_SYNC_ALWAYS, 1141 AMDGPU_FENCE_OWNER_UNDEFINED); 1142 if (r) 1143 goto err_free; 1144 1145 r = amdgpu_job_submit(job, &adev->uvd.entity, 1146 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1147 if (r) 1148 goto err_free; 1149 } 1150 1151 amdgpu_bo_fence(bo, f, false); 1152 amdgpu_bo_unreserve(bo); 1153 amdgpu_bo_unref(&bo); 1154 1155 if (fence) 1156 *fence = dma_fence_get(f); 1157 dma_fence_put(f); 1158 1159 return 0; 1160 1161 err_free: 1162 amdgpu_job_free(job); 1163 1164 err: 1165 amdgpu_bo_unreserve(bo); 1166 amdgpu_bo_unref(&bo); 1167 return r; 1168 } 1169 1170 /* multiple fence commands without any stream commands in between can 1171 crash the vcpu so just try to emmit a dummy create/destroy msg to 1172 avoid this */ 1173 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1174 struct dma_fence **fence) 1175 { 1176 struct amdgpu_device *adev = ring->adev; 1177 struct amdgpu_bo *bo = NULL; 1178 uint32_t *msg; 1179 int r, i; 1180 1181 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1182 AMDGPU_GEM_DOMAIN_GTT, 1183 &bo, NULL, (void **)&msg); 1184 if (r) 1185 return r; 1186 1187 /* stitch together an UVD create msg */ 1188 msg[0] = cpu_to_le32(0x00000de4); 1189 msg[1] = cpu_to_le32(0x00000000); 1190 msg[2] = cpu_to_le32(handle); 1191 msg[3] = cpu_to_le32(0x00000000); 1192 msg[4] = cpu_to_le32(0x00000000); 1193 msg[5] = cpu_to_le32(0x00000000); 1194 msg[6] = cpu_to_le32(0x00000000); 1195 msg[7] = cpu_to_le32(0x00000780); 1196 msg[8] = cpu_to_le32(0x00000440); 1197 msg[9] = cpu_to_le32(0x00000000); 1198 msg[10] = cpu_to_le32(0x01b37000); 1199 for (i = 11; i < 1024; ++i) 1200 msg[i] = cpu_to_le32(0x0); 1201 1202 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1203 } 1204 1205 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1206 bool direct, struct dma_fence **fence) 1207 { 1208 struct amdgpu_device *adev = ring->adev; 1209 struct amdgpu_bo *bo = NULL; 1210 uint32_t *msg; 1211 int r, i; 1212 1213 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1214 AMDGPU_GEM_DOMAIN_GTT, 1215 &bo, NULL, (void **)&msg); 1216 if (r) 1217 return r; 1218 1219 /* stitch together an UVD destroy msg */ 1220 msg[0] = cpu_to_le32(0x00000de4); 1221 msg[1] = cpu_to_le32(0x00000002); 1222 msg[2] = cpu_to_le32(handle); 1223 msg[3] = cpu_to_le32(0x00000000); 1224 for (i = 4; i < 1024; ++i) 1225 msg[i] = cpu_to_le32(0x0); 1226 1227 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1228 } 1229 1230 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1231 { 1232 struct amdgpu_device *adev = 1233 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1234 unsigned fences = 0, i, j; 1235 1236 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1237 if (adev->uvd.harvest_config & (1 << i)) 1238 continue; 1239 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1240 for (j = 0; j < adev->uvd.num_enc_rings; ++j) { 1241 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1242 } 1243 } 1244 1245 if (fences == 0) { 1246 if (adev->pm.dpm_enabled) { 1247 amdgpu_dpm_enable_uvd(adev, false); 1248 } else { 1249 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1250 /* shutdown the UVD block */ 1251 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1252 AMD_PG_STATE_GATE); 1253 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1254 AMD_CG_STATE_GATE); 1255 } 1256 } else { 1257 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1258 } 1259 } 1260 1261 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1262 { 1263 struct amdgpu_device *adev = ring->adev; 1264 bool set_clocks; 1265 1266 if (amdgpu_sriov_vf(adev)) 1267 return; 1268 1269 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1270 if (set_clocks) { 1271 if (adev->pm.dpm_enabled) { 1272 amdgpu_dpm_enable_uvd(adev, true); 1273 } else { 1274 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1275 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1276 AMD_CG_STATE_UNGATE); 1277 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1278 AMD_PG_STATE_UNGATE); 1279 } 1280 } 1281 } 1282 1283 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1284 { 1285 if (!amdgpu_sriov_vf(ring->adev)) 1286 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1287 } 1288 1289 /** 1290 * amdgpu_uvd_ring_test_ib - test ib execution 1291 * 1292 * @ring: amdgpu_ring pointer 1293 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1294 * 1295 * Test if we can successfully execute an IB 1296 */ 1297 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1298 { 1299 struct dma_fence *fence; 1300 long r; 1301 1302 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1303 if (r) 1304 goto error; 1305 1306 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1307 if (r) 1308 goto error; 1309 1310 r = dma_fence_wait_timeout(fence, false, timeout); 1311 if (r == 0) 1312 r = -ETIMEDOUT; 1313 else if (r > 0) 1314 r = 0; 1315 1316 dma_fence_put(fence); 1317 1318 error: 1319 return r; 1320 } 1321 1322 /** 1323 * amdgpu_uvd_used_handles - returns used UVD handles 1324 * 1325 * @adev: amdgpu_device pointer 1326 * 1327 * Returns the number of UVD handles in use 1328 */ 1329 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1330 { 1331 unsigned i; 1332 uint32_t used_handles = 0; 1333 1334 for (i = 0; i < adev->uvd.max_handles; ++i) { 1335 /* 1336 * Handles can be freed in any order, and not 1337 * necessarily linear. So we need to count 1338 * all non-zero handles. 1339 */ 1340 if (atomic_read(&adev->uvd.handles[i])) 1341 used_handles++; 1342 } 1343 1344 return used_handles; 1345 } 1346