1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 /* 1 second timeout */ 43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 44 45 /* Firmware versions for VI */ 46 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 47 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 48 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 49 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 50 51 /* Polaris10/11 firmware version */ 52 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 53 54 /* Firmware Names */ 55 #ifdef CONFIG_DRM_AMDGPU_CIK 56 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 57 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" 58 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" 59 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" 60 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" 61 #endif 62 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 63 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 64 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 65 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 66 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 67 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 68 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 69 70 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 71 72 #define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00) 73 #define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00) 74 #define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00) 75 #define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00) 76 #define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00) 77 78 /** 79 * amdgpu_uvd_cs_ctx - Command submission parser context 80 * 81 * Used for emulating virtual memory support on UVD 4.2. 82 */ 83 struct amdgpu_uvd_cs_ctx { 84 struct amdgpu_cs_parser *parser; 85 unsigned reg, count; 86 unsigned data0, data1; 87 unsigned idx; 88 unsigned ib_idx; 89 90 /* does the IB has a msg command */ 91 bool has_msg_cmd; 92 93 /* minimum buffer sizes */ 94 unsigned *buf_sizes; 95 }; 96 97 #ifdef CONFIG_DRM_AMDGPU_CIK 98 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 99 MODULE_FIRMWARE(FIRMWARE_KABINI); 100 MODULE_FIRMWARE(FIRMWARE_KAVERI); 101 MODULE_FIRMWARE(FIRMWARE_HAWAII); 102 MODULE_FIRMWARE(FIRMWARE_MULLINS); 103 #endif 104 MODULE_FIRMWARE(FIRMWARE_TONGA); 105 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 106 MODULE_FIRMWARE(FIRMWARE_FIJI); 107 MODULE_FIRMWARE(FIRMWARE_STONEY); 108 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 109 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 110 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 111 112 MODULE_FIRMWARE(FIRMWARE_VEGA10); 113 114 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 115 116 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 117 { 118 struct amdgpu_ring *ring; 119 struct drm_sched_rq *rq; 120 unsigned long bo_size; 121 const char *fw_name; 122 const struct common_firmware_header *hdr; 123 unsigned version_major, version_minor, family_id; 124 int i, r; 125 126 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 127 128 switch (adev->asic_type) { 129 #ifdef CONFIG_DRM_AMDGPU_CIK 130 case CHIP_BONAIRE: 131 fw_name = FIRMWARE_BONAIRE; 132 break; 133 case CHIP_KABINI: 134 fw_name = FIRMWARE_KABINI; 135 break; 136 case CHIP_KAVERI: 137 fw_name = FIRMWARE_KAVERI; 138 break; 139 case CHIP_HAWAII: 140 fw_name = FIRMWARE_HAWAII; 141 break; 142 case CHIP_MULLINS: 143 fw_name = FIRMWARE_MULLINS; 144 break; 145 #endif 146 case CHIP_TONGA: 147 fw_name = FIRMWARE_TONGA; 148 break; 149 case CHIP_FIJI: 150 fw_name = FIRMWARE_FIJI; 151 break; 152 case CHIP_CARRIZO: 153 fw_name = FIRMWARE_CARRIZO; 154 break; 155 case CHIP_STONEY: 156 fw_name = FIRMWARE_STONEY; 157 break; 158 case CHIP_POLARIS10: 159 fw_name = FIRMWARE_POLARIS10; 160 break; 161 case CHIP_POLARIS11: 162 fw_name = FIRMWARE_POLARIS11; 163 break; 164 case CHIP_VEGA10: 165 fw_name = FIRMWARE_VEGA10; 166 break; 167 case CHIP_POLARIS12: 168 fw_name = FIRMWARE_POLARIS12; 169 break; 170 default: 171 return -EINVAL; 172 } 173 174 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 175 if (r) { 176 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 177 fw_name); 178 return r; 179 } 180 181 r = amdgpu_ucode_validate(adev->uvd.fw); 182 if (r) { 183 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 184 fw_name); 185 release_firmware(adev->uvd.fw); 186 adev->uvd.fw = NULL; 187 return r; 188 } 189 190 /* Set the default UVD handles that the firmware can handle */ 191 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 192 193 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 194 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 195 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 196 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 197 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 198 version_major, version_minor, family_id); 199 200 /* 201 * Limit the number of UVD handles depending on microcode major 202 * and minor versions. The firmware version which has 40 UVD 203 * instances support is 1.80. So all subsequent versions should 204 * also have the same support. 205 */ 206 if ((version_major > 0x01) || 207 ((version_major == 0x01) && (version_minor >= 0x50))) 208 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 209 210 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 211 (family_id << 8)); 212 213 if ((adev->asic_type == CHIP_POLARIS10 || 214 adev->asic_type == CHIP_POLARIS11) && 215 (adev->uvd.fw_version < FW_1_66_16)) 216 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", 217 version_major, version_minor); 218 219 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 220 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 221 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 222 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 223 224 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 225 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo, 226 &adev->uvd.gpu_addr, &adev->uvd.cpu_addr); 227 if (r) { 228 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 229 return r; 230 } 231 232 ring = &adev->uvd.ring; 233 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; 234 r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity, 235 rq, amdgpu_sched_jobs, NULL); 236 if (r != 0) { 237 DRM_ERROR("Failed setting up UVD run queue.\n"); 238 return r; 239 } 240 241 for (i = 0; i < adev->uvd.max_handles; ++i) { 242 atomic_set(&adev->uvd.handles[i], 0); 243 adev->uvd.filp[i] = NULL; 244 } 245 246 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 247 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 248 adev->uvd.address_64_bit = true; 249 250 switch (adev->asic_type) { 251 case CHIP_TONGA: 252 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 253 break; 254 case CHIP_CARRIZO: 255 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 256 break; 257 case CHIP_FIJI: 258 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 259 break; 260 case CHIP_STONEY: 261 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 262 break; 263 default: 264 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 265 } 266 267 return 0; 268 } 269 270 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 271 { 272 int i; 273 kfree(adev->uvd.saved_bo); 274 275 drm_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); 276 277 amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo, 278 &adev->uvd.gpu_addr, 279 (void **)&adev->uvd.cpu_addr); 280 281 amdgpu_ring_fini(&adev->uvd.ring); 282 283 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 284 amdgpu_ring_fini(&adev->uvd.ring_enc[i]); 285 286 release_firmware(adev->uvd.fw); 287 288 return 0; 289 } 290 291 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 292 { 293 unsigned size; 294 void *ptr; 295 int i; 296 297 if (adev->uvd.vcpu_bo == NULL) 298 return 0; 299 300 cancel_delayed_work_sync(&adev->uvd.idle_work); 301 302 /* only valid for physical mode */ 303 if (adev->asic_type < CHIP_POLARIS10) { 304 for (i = 0; i < adev->uvd.max_handles; ++i) 305 if (atomic_read(&adev->uvd.handles[i])) 306 break; 307 308 if (i == adev->uvd.max_handles) 309 return 0; 310 } 311 312 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 313 ptr = adev->uvd.cpu_addr; 314 315 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 316 if (!adev->uvd.saved_bo) 317 return -ENOMEM; 318 319 memcpy_fromio(adev->uvd.saved_bo, ptr, size); 320 321 return 0; 322 } 323 324 int amdgpu_uvd_resume(struct amdgpu_device *adev) 325 { 326 unsigned size; 327 void *ptr; 328 329 if (adev->uvd.vcpu_bo == NULL) 330 return -EINVAL; 331 332 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 333 ptr = adev->uvd.cpu_addr; 334 335 if (adev->uvd.saved_bo != NULL) { 336 memcpy_toio(ptr, adev->uvd.saved_bo, size); 337 kfree(adev->uvd.saved_bo); 338 adev->uvd.saved_bo = NULL; 339 } else { 340 const struct common_firmware_header *hdr; 341 unsigned offset; 342 343 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 344 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 345 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 346 memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset, 347 le32_to_cpu(hdr->ucode_size_bytes)); 348 size -= le32_to_cpu(hdr->ucode_size_bytes); 349 ptr += le32_to_cpu(hdr->ucode_size_bytes); 350 } 351 memset_io(ptr, 0, size); 352 /* to restore uvd fence seq */ 353 amdgpu_fence_driver_force_completion(&adev->uvd.ring); 354 } 355 356 return 0; 357 } 358 359 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 360 { 361 struct amdgpu_ring *ring = &adev->uvd.ring; 362 int i, r; 363 364 for (i = 0; i < adev->uvd.max_handles; ++i) { 365 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 366 if (handle != 0 && adev->uvd.filp[i] == filp) { 367 struct dma_fence *fence; 368 369 r = amdgpu_uvd_get_destroy_msg(ring, handle, 370 false, &fence); 371 if (r) { 372 DRM_ERROR("Error destroying UVD (%d)!\n", r); 373 continue; 374 } 375 376 dma_fence_wait(fence, false); 377 dma_fence_put(fence); 378 379 adev->uvd.filp[i] = NULL; 380 atomic_set(&adev->uvd.handles[i], 0); 381 } 382 } 383 } 384 385 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 386 { 387 int i; 388 for (i = 0; i < abo->placement.num_placement; ++i) { 389 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 390 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 391 } 392 } 393 394 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 395 { 396 uint32_t lo, hi; 397 uint64_t addr; 398 399 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 400 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 401 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 402 403 return addr; 404 } 405 406 /** 407 * amdgpu_uvd_cs_pass1 - first parsing round 408 * 409 * @ctx: UVD parser context 410 * 411 * Make sure UVD message and feedback buffers are in VRAM and 412 * nobody is violating an 256MB boundary. 413 */ 414 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 415 { 416 struct ttm_operation_ctx tctx = { false, false }; 417 struct amdgpu_bo_va_mapping *mapping; 418 struct amdgpu_bo *bo; 419 uint32_t cmd; 420 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 421 int r = 0; 422 423 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 424 if (r) { 425 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 426 return r; 427 } 428 429 if (!ctx->parser->adev->uvd.address_64_bit) { 430 /* check if it's a message or feedback command */ 431 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 432 if (cmd == 0x0 || cmd == 0x3) { 433 /* yes, force it into VRAM */ 434 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 435 amdgpu_ttm_placement_from_domain(bo, domain); 436 } 437 amdgpu_uvd_force_into_uvd_segment(bo); 438 439 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 440 } 441 442 return r; 443 } 444 445 /** 446 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 447 * 448 * @msg: pointer to message structure 449 * @buf_sizes: returned buffer sizes 450 * 451 * Peek into the decode message and calculate the necessary buffer sizes. 452 */ 453 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 454 unsigned buf_sizes[]) 455 { 456 unsigned stream_type = msg[4]; 457 unsigned width = msg[6]; 458 unsigned height = msg[7]; 459 unsigned dpb_size = msg[9]; 460 unsigned pitch = msg[28]; 461 unsigned level = msg[57]; 462 463 unsigned width_in_mb = width / 16; 464 unsigned height_in_mb = ALIGN(height / 16, 2); 465 unsigned fs_in_mb = width_in_mb * height_in_mb; 466 467 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 468 unsigned min_ctx_size = ~0; 469 470 image_size = width * height; 471 image_size += image_size / 2; 472 image_size = ALIGN(image_size, 1024); 473 474 switch (stream_type) { 475 case 0: /* H264 */ 476 switch(level) { 477 case 30: 478 num_dpb_buffer = 8100 / fs_in_mb; 479 break; 480 case 31: 481 num_dpb_buffer = 18000 / fs_in_mb; 482 break; 483 case 32: 484 num_dpb_buffer = 20480 / fs_in_mb; 485 break; 486 case 41: 487 num_dpb_buffer = 32768 / fs_in_mb; 488 break; 489 case 42: 490 num_dpb_buffer = 34816 / fs_in_mb; 491 break; 492 case 50: 493 num_dpb_buffer = 110400 / fs_in_mb; 494 break; 495 case 51: 496 num_dpb_buffer = 184320 / fs_in_mb; 497 break; 498 default: 499 num_dpb_buffer = 184320 / fs_in_mb; 500 break; 501 } 502 num_dpb_buffer++; 503 if (num_dpb_buffer > 17) 504 num_dpb_buffer = 17; 505 506 /* reference picture buffer */ 507 min_dpb_size = image_size * num_dpb_buffer; 508 509 /* macroblock context buffer */ 510 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 511 512 /* IT surface buffer */ 513 min_dpb_size += width_in_mb * height_in_mb * 32; 514 break; 515 516 case 1: /* VC1 */ 517 518 /* reference picture buffer */ 519 min_dpb_size = image_size * 3; 520 521 /* CONTEXT_BUFFER */ 522 min_dpb_size += width_in_mb * height_in_mb * 128; 523 524 /* IT surface buffer */ 525 min_dpb_size += width_in_mb * 64; 526 527 /* DB surface buffer */ 528 min_dpb_size += width_in_mb * 128; 529 530 /* BP */ 531 tmp = max(width_in_mb, height_in_mb); 532 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 533 break; 534 535 case 3: /* MPEG2 */ 536 537 /* reference picture buffer */ 538 min_dpb_size = image_size * 3; 539 break; 540 541 case 4: /* MPEG4 */ 542 543 /* reference picture buffer */ 544 min_dpb_size = image_size * 3; 545 546 /* CM */ 547 min_dpb_size += width_in_mb * height_in_mb * 64; 548 549 /* IT surface buffer */ 550 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 551 break; 552 553 case 7: /* H264 Perf */ 554 switch(level) { 555 case 30: 556 num_dpb_buffer = 8100 / fs_in_mb; 557 break; 558 case 31: 559 num_dpb_buffer = 18000 / fs_in_mb; 560 break; 561 case 32: 562 num_dpb_buffer = 20480 / fs_in_mb; 563 break; 564 case 41: 565 num_dpb_buffer = 32768 / fs_in_mb; 566 break; 567 case 42: 568 num_dpb_buffer = 34816 / fs_in_mb; 569 break; 570 case 50: 571 num_dpb_buffer = 110400 / fs_in_mb; 572 break; 573 case 51: 574 num_dpb_buffer = 184320 / fs_in_mb; 575 break; 576 default: 577 num_dpb_buffer = 184320 / fs_in_mb; 578 break; 579 } 580 num_dpb_buffer++; 581 if (num_dpb_buffer > 17) 582 num_dpb_buffer = 17; 583 584 /* reference picture buffer */ 585 min_dpb_size = image_size * num_dpb_buffer; 586 587 if (!adev->uvd.use_ctx_buf){ 588 /* macroblock context buffer */ 589 min_dpb_size += 590 width_in_mb * height_in_mb * num_dpb_buffer * 192; 591 592 /* IT surface buffer */ 593 min_dpb_size += width_in_mb * height_in_mb * 32; 594 } else { 595 /* macroblock context buffer */ 596 min_ctx_size = 597 width_in_mb * height_in_mb * num_dpb_buffer * 192; 598 } 599 break; 600 601 case 8: /* MJPEG */ 602 min_dpb_size = 0; 603 break; 604 605 case 16: /* H265 */ 606 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 607 image_size = ALIGN(image_size, 256); 608 609 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 610 min_dpb_size = image_size * num_dpb_buffer; 611 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 612 * 16 * num_dpb_buffer + 52 * 1024; 613 break; 614 615 default: 616 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 617 return -EINVAL; 618 } 619 620 if (width > pitch) { 621 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 622 return -EINVAL; 623 } 624 625 if (dpb_size < min_dpb_size) { 626 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 627 dpb_size, min_dpb_size); 628 return -EINVAL; 629 } 630 631 buf_sizes[0x1] = dpb_size; 632 buf_sizes[0x2] = image_size; 633 buf_sizes[0x4] = min_ctx_size; 634 return 0; 635 } 636 637 /** 638 * amdgpu_uvd_cs_msg - handle UVD message 639 * 640 * @ctx: UVD parser context 641 * @bo: buffer object containing the message 642 * @offset: offset into the buffer object 643 * 644 * Peek into the UVD message and extract the session id. 645 * Make sure that we don't open up to many sessions. 646 */ 647 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 648 struct amdgpu_bo *bo, unsigned offset) 649 { 650 struct amdgpu_device *adev = ctx->parser->adev; 651 int32_t *msg, msg_type, handle; 652 void *ptr; 653 long r; 654 int i; 655 656 if (offset & 0x3F) { 657 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 658 return -EINVAL; 659 } 660 661 r = amdgpu_bo_kmap(bo, &ptr); 662 if (r) { 663 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); 664 return r; 665 } 666 667 msg = ptr + offset; 668 669 msg_type = msg[1]; 670 handle = msg[2]; 671 672 if (handle == 0) { 673 DRM_ERROR("Invalid UVD handle!\n"); 674 return -EINVAL; 675 } 676 677 switch (msg_type) { 678 case 0: 679 /* it's a create msg, calc image size (width * height) */ 680 amdgpu_bo_kunmap(bo); 681 682 /* try to alloc a new handle */ 683 for (i = 0; i < adev->uvd.max_handles; ++i) { 684 if (atomic_read(&adev->uvd.handles[i]) == handle) { 685 DRM_ERROR("Handle 0x%x already in use!\n", handle); 686 return -EINVAL; 687 } 688 689 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 690 adev->uvd.filp[i] = ctx->parser->filp; 691 return 0; 692 } 693 } 694 695 DRM_ERROR("No more free UVD handles!\n"); 696 return -ENOSPC; 697 698 case 1: 699 /* it's a decode msg, calc buffer sizes */ 700 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 701 amdgpu_bo_kunmap(bo); 702 if (r) 703 return r; 704 705 /* validate the handle */ 706 for (i = 0; i < adev->uvd.max_handles; ++i) { 707 if (atomic_read(&adev->uvd.handles[i]) == handle) { 708 if (adev->uvd.filp[i] != ctx->parser->filp) { 709 DRM_ERROR("UVD handle collision detected!\n"); 710 return -EINVAL; 711 } 712 return 0; 713 } 714 } 715 716 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 717 return -ENOENT; 718 719 case 2: 720 /* it's a destroy msg, free the handle */ 721 for (i = 0; i < adev->uvd.max_handles; ++i) 722 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 723 amdgpu_bo_kunmap(bo); 724 return 0; 725 726 default: 727 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 728 return -EINVAL; 729 } 730 BUG(); 731 return -EINVAL; 732 } 733 734 /** 735 * amdgpu_uvd_cs_pass2 - second parsing round 736 * 737 * @ctx: UVD parser context 738 * 739 * Patch buffer addresses, make sure buffer sizes are correct. 740 */ 741 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 742 { 743 struct amdgpu_bo_va_mapping *mapping; 744 struct amdgpu_bo *bo; 745 uint32_t cmd; 746 uint64_t start, end; 747 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 748 int r; 749 750 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 751 if (r) { 752 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 753 return r; 754 } 755 756 start = amdgpu_bo_gpu_offset(bo); 757 758 end = (mapping->last + 1 - mapping->start); 759 end = end * AMDGPU_GPU_PAGE_SIZE + start; 760 761 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 762 start += addr; 763 764 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 765 lower_32_bits(start)); 766 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 767 upper_32_bits(start)); 768 769 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 770 if (cmd < 0x4) { 771 if ((end - start) < ctx->buf_sizes[cmd]) { 772 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 773 (unsigned)(end - start), 774 ctx->buf_sizes[cmd]); 775 return -EINVAL; 776 } 777 778 } else if (cmd == 0x206) { 779 if ((end - start) < ctx->buf_sizes[4]) { 780 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 781 (unsigned)(end - start), 782 ctx->buf_sizes[4]); 783 return -EINVAL; 784 } 785 } else if ((cmd != 0x100) && (cmd != 0x204)) { 786 DRM_ERROR("invalid UVD command %X!\n", cmd); 787 return -EINVAL; 788 } 789 790 if (!ctx->parser->adev->uvd.address_64_bit) { 791 if ((start >> 28) != ((end - 1) >> 28)) { 792 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 793 start, end); 794 return -EINVAL; 795 } 796 797 if ((cmd == 0 || cmd == 0x3) && 798 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { 799 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 800 start, end); 801 return -EINVAL; 802 } 803 } 804 805 if (cmd == 0) { 806 ctx->has_msg_cmd = true; 807 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 808 if (r) 809 return r; 810 } else if (!ctx->has_msg_cmd) { 811 DRM_ERROR("Message needed before other commands are send!\n"); 812 return -EINVAL; 813 } 814 815 return 0; 816 } 817 818 /** 819 * amdgpu_uvd_cs_reg - parse register writes 820 * 821 * @ctx: UVD parser context 822 * @cb: callback function 823 * 824 * Parse the register writes, call cb on each complete command. 825 */ 826 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 827 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 828 { 829 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 830 int i, r; 831 832 ctx->idx++; 833 for (i = 0; i <= ctx->count; ++i) { 834 unsigned reg = ctx->reg + i; 835 836 if (ctx->idx >= ib->length_dw) { 837 DRM_ERROR("Register command after end of CS!\n"); 838 return -EINVAL; 839 } 840 841 switch (reg) { 842 case mmUVD_GPCOM_VCPU_DATA0: 843 ctx->data0 = ctx->idx; 844 break; 845 case mmUVD_GPCOM_VCPU_DATA1: 846 ctx->data1 = ctx->idx; 847 break; 848 case mmUVD_GPCOM_VCPU_CMD: 849 r = cb(ctx); 850 if (r) 851 return r; 852 break; 853 case mmUVD_ENGINE_CNTL: 854 case mmUVD_NO_OP: 855 break; 856 default: 857 DRM_ERROR("Invalid reg 0x%X!\n", reg); 858 return -EINVAL; 859 } 860 ctx->idx++; 861 } 862 return 0; 863 } 864 865 /** 866 * amdgpu_uvd_cs_packets - parse UVD packets 867 * 868 * @ctx: UVD parser context 869 * @cb: callback function 870 * 871 * Parse the command stream packets. 872 */ 873 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 874 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 875 { 876 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 877 int r; 878 879 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 880 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 881 unsigned type = CP_PACKET_GET_TYPE(cmd); 882 switch (type) { 883 case PACKET_TYPE0: 884 ctx->reg = CP_PACKET0_GET_REG(cmd); 885 ctx->count = CP_PACKET_GET_COUNT(cmd); 886 r = amdgpu_uvd_cs_reg(ctx, cb); 887 if (r) 888 return r; 889 break; 890 case PACKET_TYPE2: 891 ++ctx->idx; 892 break; 893 default: 894 DRM_ERROR("Unknown packet type %d !\n", type); 895 return -EINVAL; 896 } 897 } 898 return 0; 899 } 900 901 /** 902 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 903 * 904 * @parser: Command submission parser context 905 * 906 * Parse the command stream, patch in addresses as necessary. 907 */ 908 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 909 { 910 struct amdgpu_uvd_cs_ctx ctx = {}; 911 unsigned buf_sizes[] = { 912 [0x00000000] = 2048, 913 [0x00000001] = 0xFFFFFFFF, 914 [0x00000002] = 0xFFFFFFFF, 915 [0x00000003] = 2048, 916 [0x00000004] = 0xFFFFFFFF, 917 }; 918 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 919 int r; 920 921 parser->job->vm = NULL; 922 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 923 924 if (ib->length_dw % 16) { 925 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 926 ib->length_dw); 927 return -EINVAL; 928 } 929 930 ctx.parser = parser; 931 ctx.buf_sizes = buf_sizes; 932 ctx.ib_idx = ib_idx; 933 934 /* first round only required on chips without UVD 64 bit address support */ 935 if (!parser->adev->uvd.address_64_bit) { 936 /* first round, make sure the buffers are actually in the UVD segment */ 937 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 938 if (r) 939 return r; 940 } 941 942 /* second round, patch buffer addresses into the command stream */ 943 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 944 if (r) 945 return r; 946 947 if (!ctx.has_msg_cmd) { 948 DRM_ERROR("UVD-IBs need a msg command!\n"); 949 return -EINVAL; 950 } 951 952 return 0; 953 } 954 955 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 956 bool direct, struct dma_fence **fence) 957 { 958 struct amdgpu_device *adev = ring->adev; 959 struct dma_fence *f = NULL; 960 struct amdgpu_job *job; 961 struct amdgpu_ib *ib; 962 uint32_t data[4]; 963 uint64_t addr; 964 long r; 965 int i; 966 967 amdgpu_bo_kunmap(bo); 968 amdgpu_bo_unpin(bo); 969 970 if (!ring->adev->uvd.address_64_bit) { 971 struct ttm_operation_ctx ctx = { true, false }; 972 973 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 974 amdgpu_uvd_force_into_uvd_segment(bo); 975 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 976 if (r) 977 goto err; 978 } 979 980 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 981 if (r) 982 goto err; 983 984 if (adev->asic_type >= CHIP_VEGA10) { 985 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0); 986 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0); 987 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0); 988 data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0); 989 } else { 990 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); 991 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); 992 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); 993 data[3] = PACKET0(mmUVD_NO_OP, 0); 994 } 995 996 ib = &job->ibs[0]; 997 addr = amdgpu_bo_gpu_offset(bo); 998 ib->ptr[0] = data[0]; 999 ib->ptr[1] = addr; 1000 ib->ptr[2] = data[1]; 1001 ib->ptr[3] = addr >> 32; 1002 ib->ptr[4] = data[2]; 1003 ib->ptr[5] = 0; 1004 for (i = 6; i < 16; i += 2) { 1005 ib->ptr[i] = data[3]; 1006 ib->ptr[i+1] = 0; 1007 } 1008 ib->length_dw = 16; 1009 1010 if (direct) { 1011 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, 1012 true, false, 1013 msecs_to_jiffies(10)); 1014 if (r == 0) 1015 r = -ETIMEDOUT; 1016 if (r < 0) 1017 goto err_free; 1018 1019 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); 1020 job->fence = dma_fence_get(f); 1021 if (r) 1022 goto err_free; 1023 1024 amdgpu_job_free(job); 1025 } else { 1026 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, 1027 AMDGPU_FENCE_OWNER_UNDEFINED, false); 1028 if (r) 1029 goto err_free; 1030 1031 r = amdgpu_job_submit(job, ring, &adev->uvd.entity, 1032 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1033 if (r) 1034 goto err_free; 1035 } 1036 1037 amdgpu_bo_fence(bo, f, false); 1038 amdgpu_bo_unreserve(bo); 1039 amdgpu_bo_unref(&bo); 1040 1041 if (fence) 1042 *fence = dma_fence_get(f); 1043 dma_fence_put(f); 1044 1045 return 0; 1046 1047 err_free: 1048 amdgpu_job_free(job); 1049 1050 err: 1051 amdgpu_bo_unreserve(bo); 1052 amdgpu_bo_unref(&bo); 1053 return r; 1054 } 1055 1056 /* multiple fence commands without any stream commands in between can 1057 crash the vcpu so just try to emmit a dummy create/destroy msg to 1058 avoid this */ 1059 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1060 struct dma_fence **fence) 1061 { 1062 struct amdgpu_device *adev = ring->adev; 1063 struct amdgpu_bo *bo = NULL; 1064 uint32_t *msg; 1065 int r, i; 1066 1067 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1068 AMDGPU_GEM_DOMAIN_VRAM, 1069 &bo, NULL, (void **)&msg); 1070 if (r) 1071 return r; 1072 1073 /* stitch together an UVD create msg */ 1074 msg[0] = cpu_to_le32(0x00000de4); 1075 msg[1] = cpu_to_le32(0x00000000); 1076 msg[2] = cpu_to_le32(handle); 1077 msg[3] = cpu_to_le32(0x00000000); 1078 msg[4] = cpu_to_le32(0x00000000); 1079 msg[5] = cpu_to_le32(0x00000000); 1080 msg[6] = cpu_to_le32(0x00000000); 1081 msg[7] = cpu_to_le32(0x00000780); 1082 msg[8] = cpu_to_le32(0x00000440); 1083 msg[9] = cpu_to_le32(0x00000000); 1084 msg[10] = cpu_to_le32(0x01b37000); 1085 for (i = 11; i < 1024; ++i) 1086 msg[i] = cpu_to_le32(0x0); 1087 1088 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1089 } 1090 1091 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1092 bool direct, struct dma_fence **fence) 1093 { 1094 struct amdgpu_device *adev = ring->adev; 1095 struct amdgpu_bo *bo = NULL; 1096 uint32_t *msg; 1097 int r, i; 1098 1099 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1100 AMDGPU_GEM_DOMAIN_VRAM, 1101 &bo, NULL, (void **)&msg); 1102 if (r) 1103 return r; 1104 1105 /* stitch together an UVD destroy msg */ 1106 msg[0] = cpu_to_le32(0x00000de4); 1107 msg[1] = cpu_to_le32(0x00000002); 1108 msg[2] = cpu_to_le32(handle); 1109 msg[3] = cpu_to_le32(0x00000000); 1110 for (i = 4; i < 1024; ++i) 1111 msg[i] = cpu_to_le32(0x0); 1112 1113 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1114 } 1115 1116 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1117 { 1118 struct amdgpu_device *adev = 1119 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1120 unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring); 1121 1122 if (fences == 0) { 1123 if (adev->pm.dpm_enabled) { 1124 amdgpu_dpm_enable_uvd(adev, false); 1125 } else { 1126 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1127 /* shutdown the UVD block */ 1128 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1129 AMD_PG_STATE_GATE); 1130 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1131 AMD_CG_STATE_GATE); 1132 } 1133 } else { 1134 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1135 } 1136 } 1137 1138 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1139 { 1140 struct amdgpu_device *adev = ring->adev; 1141 bool set_clocks; 1142 1143 if (amdgpu_sriov_vf(adev)) 1144 return; 1145 1146 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1147 if (set_clocks) { 1148 if (adev->pm.dpm_enabled) { 1149 amdgpu_dpm_enable_uvd(adev, true); 1150 } else { 1151 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1152 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1153 AMD_CG_STATE_UNGATE); 1154 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1155 AMD_PG_STATE_UNGATE); 1156 } 1157 } 1158 } 1159 1160 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1161 { 1162 if (!amdgpu_sriov_vf(ring->adev)) 1163 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1164 } 1165 1166 /** 1167 * amdgpu_uvd_ring_test_ib - test ib execution 1168 * 1169 * @ring: amdgpu_ring pointer 1170 * 1171 * Test if we can successfully execute an IB 1172 */ 1173 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1174 { 1175 struct dma_fence *fence; 1176 long r; 1177 1178 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1179 if (r) { 1180 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); 1181 goto error; 1182 } 1183 1184 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1185 if (r) { 1186 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); 1187 goto error; 1188 } 1189 1190 r = dma_fence_wait_timeout(fence, false, timeout); 1191 if (r == 0) { 1192 DRM_ERROR("amdgpu: IB test timed out.\n"); 1193 r = -ETIMEDOUT; 1194 } else if (r < 0) { 1195 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1196 } else { 1197 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 1198 r = 0; 1199 } 1200 1201 dma_fence_put(fence); 1202 1203 error: 1204 return r; 1205 } 1206 1207 /** 1208 * amdgpu_uvd_used_handles - returns used UVD handles 1209 * 1210 * @adev: amdgpu_device pointer 1211 * 1212 * Returns the number of UVD handles in use 1213 */ 1214 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1215 { 1216 unsigned i; 1217 uint32_t used_handles = 0; 1218 1219 for (i = 0; i < adev->uvd.max_handles; ++i) { 1220 /* 1221 * Handles can be freed in any order, and not 1222 * necessarily linear. So we need to count 1223 * all non-zero handles. 1224 */ 1225 if (atomic_read(&adev->uvd.handles[i])) 1226 used_handles++; 1227 } 1228 1229 return used_handles; 1230 } 1231