1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef __AMDGPU_UMC_H__ 22 #define __AMDGPU_UMC_H__ 23 24 /* 25 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr 26 * is the index of 8KB block 27 */ 28 #define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) 29 /* channel index is the index of 256B block */ 30 #define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) 31 /* offset in 256B block */ 32 #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) 33 34 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++) 35 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++) 36 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst)) 37 38 struct amdgpu_umc_funcs { 39 void (*err_cnt_init)(struct amdgpu_device *adev); 40 int (*ras_late_init)(struct amdgpu_device *adev); 41 void (*query_ras_error_count)(struct amdgpu_device *adev, 42 void *ras_error_status); 43 void (*query_ras_error_address)(struct amdgpu_device *adev, 44 void *ras_error_status); 45 void (*init_registers)(struct amdgpu_device *adev); 46 }; 47 48 struct amdgpu_umc { 49 /* max error count in one ras query call */ 50 uint32_t max_ras_err_cnt_per_query; 51 /* number of umc channel instance with memory map register access */ 52 uint32_t channel_inst_num; 53 /* number of umc instance with memory map register access */ 54 uint32_t umc_inst_num; 55 /* UMC regiser per channel offset */ 56 uint32_t channel_offs; 57 /* channel index table of interleaved memory */ 58 const uint32_t *channel_idx_tbl; 59 struct ras_common_if *ras_if; 60 61 const struct amdgpu_umc_funcs *funcs; 62 }; 63 64 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev); 65 void amdgpu_umc_ras_fini(struct amdgpu_device *adev); 66 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 67 void *ras_error_status, 68 struct amdgpu_iv_entry *entry); 69 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 70 struct amdgpu_irq_src *source, 71 struct amdgpu_iv_entry *entry); 72 #endif 73