1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras.h" 25 26 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev) 27 { 28 int r; 29 struct ras_fs_if fs_info = { 30 .sysfs_name = "umc_err_count", 31 }; 32 struct ras_ih_if ih_info = { 33 .cb = amdgpu_umc_process_ras_data_cb, 34 }; 35 36 if (!adev->umc.ras_if) { 37 adev->umc.ras_if = 38 kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); 39 if (!adev->umc.ras_if) 40 return -ENOMEM; 41 adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC; 42 adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 43 adev->umc.ras_if->sub_block_index = 0; 44 } 45 ih_info.head = fs_info.head = *adev->umc.ras_if; 46 47 r = amdgpu_ras_late_init(adev, adev->umc.ras_if, 48 &fs_info, &ih_info); 49 if (r) 50 goto free; 51 52 if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) { 53 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); 54 if (r) 55 goto late_fini; 56 } else { 57 r = 0; 58 goto free; 59 } 60 61 /* ras init of specific umc version */ 62 if (adev->umc.ras_funcs && 63 adev->umc.ras_funcs->err_cnt_init) 64 adev->umc.ras_funcs->err_cnt_init(adev); 65 66 return 0; 67 68 late_fini: 69 amdgpu_ras_late_fini(adev, adev->umc.ras_if, &ih_info); 70 free: 71 kfree(adev->umc.ras_if); 72 adev->umc.ras_if = NULL; 73 return r; 74 } 75 76 void amdgpu_umc_ras_fini(struct amdgpu_device *adev) 77 { 78 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && 79 adev->umc.ras_if) { 80 struct ras_common_if *ras_if = adev->umc.ras_if; 81 struct ras_ih_if ih_info = { 82 .head = *ras_if, 83 .cb = amdgpu_umc_process_ras_data_cb, 84 }; 85 86 amdgpu_ras_late_fini(adev, ras_if, &ih_info); 87 kfree(ras_if); 88 } 89 } 90 91 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 92 void *ras_error_status, 93 struct amdgpu_iv_entry *entry) 94 { 95 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 96 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 97 int ret = 0; 98 99 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 100 ret = smu_get_ecc_info(&adev->smu, (void *)&(con->umc_ecc)); 101 if (ret == -EOPNOTSUPP) { 102 if (adev->umc.ras_funcs && 103 adev->umc.ras_funcs->query_ras_error_count) 104 adev->umc.ras_funcs->query_ras_error_count(adev, ras_error_status); 105 106 if (adev->umc.ras_funcs && 107 adev->umc.ras_funcs->query_ras_error_address && 108 adev->umc.max_ras_err_cnt_per_query) { 109 err_data->err_addr = 110 kcalloc(adev->umc.max_ras_err_cnt_per_query, 111 sizeof(struct eeprom_table_record), GFP_KERNEL); 112 113 /* still call query_ras_error_address to clear error status 114 * even NOMEM error is encountered 115 */ 116 if(!err_data->err_addr) 117 dev_warn(adev->dev, "Failed to alloc memory for " 118 "umc error address record!\n"); 119 120 /* umc query_ras_error_address is also responsible for clearing 121 * error status 122 */ 123 adev->umc.ras_funcs->query_ras_error_address(adev, ras_error_status); 124 } 125 } else if (!ret) { 126 if (adev->umc.ras_funcs && 127 adev->umc.ras_funcs->ecc_info_query_ras_error_count) 128 adev->umc.ras_funcs->ecc_info_query_ras_error_count(adev, ras_error_status); 129 130 if (adev->umc.ras_funcs && 131 adev->umc.ras_funcs->ecc_info_query_ras_error_address && 132 adev->umc.max_ras_err_cnt_per_query) { 133 err_data->err_addr = 134 kcalloc(adev->umc.max_ras_err_cnt_per_query, 135 sizeof(struct eeprom_table_record), GFP_KERNEL); 136 137 /* still call query_ras_error_address to clear error status 138 * even NOMEM error is encountered 139 */ 140 if(!err_data->err_addr) 141 dev_warn(adev->dev, "Failed to alloc memory for " 142 "umc error address record!\n"); 143 144 /* umc query_ras_error_address is also responsible for clearing 145 * error status 146 */ 147 adev->umc.ras_funcs->ecc_info_query_ras_error_address(adev, ras_error_status); 148 } 149 } 150 151 /* only uncorrectable error needs gpu reset */ 152 if (err_data->ue_count) { 153 dev_info(adev->dev, "%ld uncorrectable hardware errors " 154 "detected in UMC block\n", 155 err_data->ue_count); 156 157 if ((amdgpu_bad_page_threshold != 0) && 158 err_data->err_addr_cnt) { 159 amdgpu_ras_add_bad_pages(adev, err_data->err_addr, 160 err_data->err_addr_cnt); 161 amdgpu_ras_save_bad_pages(adev); 162 163 if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) 164 adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs); 165 } 166 167 amdgpu_ras_reset_gpu(adev); 168 } 169 170 kfree(err_data->err_addr); 171 return AMDGPU_RAS_SUCCESS; 172 } 173 174 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 175 struct amdgpu_irq_src *source, 176 struct amdgpu_iv_entry *entry) 177 { 178 struct ras_common_if *ras_if = adev->umc.ras_if; 179 struct ras_dispatch_if ih_data = { 180 .entry = entry, 181 }; 182 183 if (!ras_if) 184 return 0; 185 186 ih_data.head = *ras_if; 187 188 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 189 return 0; 190 } 191