1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 #include "amdgpu_socbb.h" 27 28 struct common_firmware_header { 29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 30 uint32_t header_size_bytes; /* size of just the header in bytes */ 31 uint16_t header_version_major; /* header version */ 32 uint16_t header_version_minor; /* header version */ 33 uint16_t ip_version_major; /* IP version */ 34 uint16_t ip_version_minor; /* IP version */ 35 uint32_t ucode_version; 36 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 38 uint32_t crc32; /* crc32 checksum of the payload */ 39 }; 40 41 /* version_major=1, version_minor=0 */ 42 struct mc_firmware_header_v1_0 { 43 struct common_firmware_header header; 44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 46 }; 47 48 /* version_major=1, version_minor=0 */ 49 struct smc_firmware_header_v1_0 { 50 struct common_firmware_header header; 51 uint32_t ucode_start_addr; 52 }; 53 54 /* version_major=2, version_minor=0 */ 55 struct smc_firmware_header_v2_0 { 56 struct smc_firmware_header_v1_0 v1_0; 57 uint32_t ppt_offset_bytes; /* soft pptable offset */ 58 uint32_t ppt_size_bytes; /* soft pptable size */ 59 }; 60 61 struct smc_soft_pptable_entry { 62 uint32_t id; 63 uint32_t ppt_offset_bytes; 64 uint32_t ppt_size_bytes; 65 }; 66 67 /* version_major=2, version_minor=1 */ 68 struct smc_firmware_header_v2_1 { 69 struct smc_firmware_header_v1_0 v1_0; 70 uint32_t pptable_count; 71 uint32_t pptable_entry_offset; 72 }; 73 74 /* version_major=1, version_minor=0 */ 75 struct psp_firmware_header_v1_0 { 76 struct common_firmware_header header; 77 uint32_t ucode_feature_version; 78 uint32_t sos_offset_bytes; 79 uint32_t sos_size_bytes; 80 }; 81 82 /* version_major=1, version_minor=1 */ 83 struct psp_firmware_header_v1_1 { 84 struct psp_firmware_header_v1_0 v1_0; 85 uint32_t toc_header_version; 86 uint32_t toc_offset_bytes; 87 uint32_t toc_size_bytes; 88 }; 89 90 /* version_major=1, version_minor=0 */ 91 struct ta_firmware_header_v1_0 { 92 struct common_firmware_header header; 93 uint32_t ta_xgmi_ucode_version; 94 uint32_t ta_xgmi_offset_bytes; 95 uint32_t ta_xgmi_size_bytes; 96 uint32_t ta_ras_ucode_version; 97 uint32_t ta_ras_offset_bytes; 98 uint32_t ta_ras_size_bytes; 99 }; 100 101 /* version_major=1, version_minor=0 */ 102 struct gfx_firmware_header_v1_0 { 103 struct common_firmware_header header; 104 uint32_t ucode_feature_version; 105 uint32_t jt_offset; /* jt location */ 106 uint32_t jt_size; /* size of jt */ 107 }; 108 109 /* version_major=1, version_minor=0 */ 110 struct mes_firmware_header_v1_0 { 111 struct common_firmware_header header; 112 uint32_t mes_ucode_version; 113 uint32_t mes_ucode_size_bytes; 114 uint32_t mes_ucode_offset_bytes; 115 uint32_t mes_ucode_data_version; 116 uint32_t mes_ucode_data_size_bytes; 117 uint32_t mes_ucode_data_offset_bytes; 118 uint32_t mes_uc_start_addr_lo; 119 uint32_t mes_uc_start_addr_hi; 120 uint32_t mes_data_start_addr_lo; 121 uint32_t mes_data_start_addr_hi; 122 }; 123 124 /* version_major=1, version_minor=0 */ 125 struct rlc_firmware_header_v1_0 { 126 struct common_firmware_header header; 127 uint32_t ucode_feature_version; 128 uint32_t save_and_restore_offset; 129 uint32_t clear_state_descriptor_offset; 130 uint32_t avail_scratch_ram_locations; 131 uint32_t master_pkt_description_offset; 132 }; 133 134 /* version_major=2, version_minor=0 */ 135 struct rlc_firmware_header_v2_0 { 136 struct common_firmware_header header; 137 uint32_t ucode_feature_version; 138 uint32_t jt_offset; /* jt location */ 139 uint32_t jt_size; /* size of jt */ 140 uint32_t save_and_restore_offset; 141 uint32_t clear_state_descriptor_offset; 142 uint32_t avail_scratch_ram_locations; 143 uint32_t reg_restore_list_size; 144 uint32_t reg_list_format_start; 145 uint32_t reg_list_format_separate_start; 146 uint32_t starting_offsets_start; 147 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 148 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 149 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 150 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 151 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 152 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 153 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 154 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 155 }; 156 157 /* version_major=2, version_minor=1 */ 158 struct rlc_firmware_header_v2_1 { 159 struct rlc_firmware_header_v2_0 v2_0; 160 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 161 uint32_t save_restore_list_cntl_ucode_ver; 162 uint32_t save_restore_list_cntl_feature_ver; 163 uint32_t save_restore_list_cntl_size_bytes; 164 uint32_t save_restore_list_cntl_offset_bytes; 165 uint32_t save_restore_list_gpm_ucode_ver; 166 uint32_t save_restore_list_gpm_feature_ver; 167 uint32_t save_restore_list_gpm_size_bytes; 168 uint32_t save_restore_list_gpm_offset_bytes; 169 uint32_t save_restore_list_srm_ucode_ver; 170 uint32_t save_restore_list_srm_feature_ver; 171 uint32_t save_restore_list_srm_size_bytes; 172 uint32_t save_restore_list_srm_offset_bytes; 173 }; 174 175 /* version_major=1, version_minor=0 */ 176 struct sdma_firmware_header_v1_0 { 177 struct common_firmware_header header; 178 uint32_t ucode_feature_version; 179 uint32_t ucode_change_version; 180 uint32_t jt_offset; /* jt location */ 181 uint32_t jt_size; /* size of jt */ 182 }; 183 184 /* version_major=1, version_minor=1 */ 185 struct sdma_firmware_header_v1_1 { 186 struct sdma_firmware_header_v1_0 v1_0; 187 uint32_t digest_size; 188 }; 189 190 /* gpu info payload */ 191 struct gpu_info_firmware_v1_0 { 192 uint32_t gc_num_se; 193 uint32_t gc_num_cu_per_sh; 194 uint32_t gc_num_sh_per_se; 195 uint32_t gc_num_rb_per_se; 196 uint32_t gc_num_tccs; 197 uint32_t gc_num_gprs; 198 uint32_t gc_num_max_gs_thds; 199 uint32_t gc_gs_table_depth; 200 uint32_t gc_gsprim_buff_depth; 201 uint32_t gc_parameter_cache_depth; 202 uint32_t gc_double_offchip_lds_buffer; 203 uint32_t gc_wave_size; 204 uint32_t gc_max_waves_per_simd; 205 uint32_t gc_max_scratch_slots_per_cu; 206 uint32_t gc_lds_size; 207 }; 208 209 struct gpu_info_firmware_v1_1 { 210 struct gpu_info_firmware_v1_0 v1_0; 211 uint32_t num_sc_per_sh; 212 uint32_t num_packer_per_sc; 213 }; 214 215 /* gpu info payload 216 * version_major=1, version_minor=1 */ 217 struct gpu_info_firmware_v1_2 { 218 struct gpu_info_firmware_v1_1 v1_1; 219 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 220 }; 221 222 /* version_major=1, version_minor=0 */ 223 struct gpu_info_firmware_header_v1_0 { 224 struct common_firmware_header header; 225 uint16_t version_major; /* version */ 226 uint16_t version_minor; /* version */ 227 }; 228 229 /* version_major=1, version_minor=0 */ 230 struct dmcu_firmware_header_v1_0 { 231 struct common_firmware_header header; 232 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 233 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 234 }; 235 236 /* header is fixed size */ 237 union amdgpu_firmware_header { 238 struct common_firmware_header common; 239 struct mc_firmware_header_v1_0 mc; 240 struct smc_firmware_header_v1_0 smc; 241 struct smc_firmware_header_v2_0 smc_v2_0; 242 struct psp_firmware_header_v1_0 psp; 243 struct psp_firmware_header_v1_1 psp_v1_1; 244 struct ta_firmware_header_v1_0 ta; 245 struct gfx_firmware_header_v1_0 gfx; 246 struct rlc_firmware_header_v1_0 rlc; 247 struct rlc_firmware_header_v2_0 rlc_v2_0; 248 struct rlc_firmware_header_v2_1 rlc_v2_1; 249 struct sdma_firmware_header_v1_0 sdma; 250 struct sdma_firmware_header_v1_1 sdma_v1_1; 251 struct gpu_info_firmware_header_v1_0 gpu_info; 252 struct dmcu_firmware_header_v1_0 dmcu; 253 uint8_t raw[0x100]; 254 }; 255 256 /* 257 * fw loading support 258 */ 259 enum AMDGPU_UCODE_ID { 260 AMDGPU_UCODE_ID_SDMA0 = 0, 261 AMDGPU_UCODE_ID_SDMA1, 262 AMDGPU_UCODE_ID_CP_CE, 263 AMDGPU_UCODE_ID_CP_PFP, 264 AMDGPU_UCODE_ID_CP_ME, 265 AMDGPU_UCODE_ID_CP_MEC1, 266 AMDGPU_UCODE_ID_CP_MEC1_JT, 267 AMDGPU_UCODE_ID_CP_MEC2, 268 AMDGPU_UCODE_ID_CP_MEC2_JT, 269 AMDGPU_UCODE_ID_CP_MES, 270 AMDGPU_UCODE_ID_CP_MES_DATA, 271 AMDGPU_UCODE_ID_RLC_G, 272 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 273 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 274 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 275 AMDGPU_UCODE_ID_STORAGE, 276 AMDGPU_UCODE_ID_SMC, 277 AMDGPU_UCODE_ID_UVD, 278 AMDGPU_UCODE_ID_UVD1, 279 AMDGPU_UCODE_ID_VCE, 280 AMDGPU_UCODE_ID_VCN, 281 AMDGPU_UCODE_ID_DMCU_ERAM, 282 AMDGPU_UCODE_ID_DMCU_INTV, 283 AMDGPU_UCODE_ID_VCN0_RAM, 284 AMDGPU_UCODE_ID_VCN1_RAM, 285 AMDGPU_UCODE_ID_MAXIMUM, 286 }; 287 288 /* engine firmware status */ 289 enum AMDGPU_UCODE_STATUS { 290 AMDGPU_UCODE_STATUS_INVALID, 291 AMDGPU_UCODE_STATUS_NOT_LOADED, 292 AMDGPU_UCODE_STATUS_LOADED, 293 }; 294 295 enum amdgpu_firmware_load_type { 296 AMDGPU_FW_LOAD_DIRECT = 0, 297 AMDGPU_FW_LOAD_SMU, 298 AMDGPU_FW_LOAD_PSP, 299 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 300 }; 301 302 /* conform to smu_ucode_xfer_cz.h */ 303 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 304 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 305 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 306 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 307 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 308 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 309 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 310 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 311 312 /* amdgpu firmware info */ 313 struct amdgpu_firmware_info { 314 /* ucode ID */ 315 enum AMDGPU_UCODE_ID ucode_id; 316 /* request_firmware */ 317 const struct firmware *fw; 318 /* starting mc address */ 319 uint64_t mc_addr; 320 /* kernel linear address */ 321 void *kaddr; 322 /* ucode_size_bytes */ 323 uint32_t ucode_size; 324 /* starting tmr mc address */ 325 uint32_t tmr_mc_addr_lo; 326 uint32_t tmr_mc_addr_hi; 327 }; 328 329 struct amdgpu_firmware { 330 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 331 enum amdgpu_firmware_load_type load_type; 332 struct amdgpu_bo *fw_buf; 333 unsigned int fw_size; 334 unsigned int max_ucodes; 335 /* firmwares are loaded by psp instead of smu from vega10 */ 336 const struct amdgpu_psp_funcs *funcs; 337 struct amdgpu_bo *rbuf; 338 struct mutex mutex; 339 340 /* gpu info firmware data pointer */ 341 const struct firmware *gpu_info_fw; 342 343 void *fw_buf_ptr; 344 uint64_t fw_buf_mc; 345 }; 346 347 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 348 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 349 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 350 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 351 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 352 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 353 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 354 int amdgpu_ucode_validate(const struct firmware *fw); 355 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 356 uint16_t hdr_major, uint16_t hdr_minor); 357 358 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 359 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 360 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 361 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 362 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 363 364 enum amdgpu_firmware_load_type 365 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 366 367 #endif 368