1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 #include "amdgpu_socbb.h" 27 28 struct common_firmware_header { 29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 30 uint32_t header_size_bytes; /* size of just the header in bytes */ 31 uint16_t header_version_major; /* header version */ 32 uint16_t header_version_minor; /* header version */ 33 uint16_t ip_version_major; /* IP version */ 34 uint16_t ip_version_minor; /* IP version */ 35 uint32_t ucode_version; 36 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 38 uint32_t crc32; /* crc32 checksum of the payload */ 39 }; 40 41 /* version_major=1, version_minor=0 */ 42 struct mc_firmware_header_v1_0 { 43 struct common_firmware_header header; 44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 46 }; 47 48 /* version_major=1, version_minor=0 */ 49 struct smc_firmware_header_v1_0 { 50 struct common_firmware_header header; 51 uint32_t ucode_start_addr; 52 }; 53 54 /* version_major=2, version_minor=0 */ 55 struct smc_firmware_header_v2_0 { 56 struct smc_firmware_header_v1_0 v1_0; 57 uint32_t ppt_offset_bytes; /* soft pptable offset */ 58 uint32_t ppt_size_bytes; /* soft pptable size */ 59 }; 60 61 struct smc_soft_pptable_entry { 62 uint32_t id; 63 uint32_t ppt_offset_bytes; 64 uint32_t ppt_size_bytes; 65 }; 66 67 /* version_major=2, version_minor=1 */ 68 struct smc_firmware_header_v2_1 { 69 struct smc_firmware_header_v1_0 v1_0; 70 uint32_t pptable_count; 71 uint32_t pptable_entry_offset; 72 }; 73 74 struct psp_fw_legacy_bin_desc { 75 uint32_t fw_version; 76 uint32_t offset_bytes; 77 uint32_t size_bytes; 78 }; 79 80 /* version_major=1, version_minor=0 */ 81 struct psp_firmware_header_v1_0 { 82 struct common_firmware_header header; 83 struct psp_fw_legacy_bin_desc sos; 84 }; 85 86 /* version_major=1, version_minor=1 */ 87 struct psp_firmware_header_v1_1 { 88 struct psp_firmware_header_v1_0 v1_0; 89 struct psp_fw_legacy_bin_desc toc; 90 struct psp_fw_legacy_bin_desc kdb; 91 }; 92 93 /* version_major=1, version_minor=2 */ 94 struct psp_firmware_header_v1_2 { 95 struct psp_firmware_header_v1_0 v1_0; 96 struct psp_fw_legacy_bin_desc res; 97 struct psp_fw_legacy_bin_desc kdb; 98 }; 99 100 /* version_major=1, version_minor=3 */ 101 struct psp_firmware_header_v1_3 { 102 struct psp_firmware_header_v1_1 v1_1; 103 struct psp_fw_legacy_bin_desc spl; 104 struct psp_fw_legacy_bin_desc rl; 105 struct psp_fw_legacy_bin_desc sys_drv_aux; 106 struct psp_fw_legacy_bin_desc sos_aux; 107 }; 108 109 struct psp_fw_bin_desc { 110 uint32_t fw_type; 111 uint32_t fw_version; 112 uint32_t offset_bytes; 113 uint32_t size_bytes; 114 }; 115 116 enum psp_fw_type { 117 PSP_FW_TYPE_UNKOWN, 118 PSP_FW_TYPE_PSP_SOS, 119 PSP_FW_TYPE_PSP_SYS_DRV, 120 PSP_FW_TYPE_PSP_KDB, 121 PSP_FW_TYPE_PSP_TOC, 122 PSP_FW_TYPE_PSP_SPL, 123 PSP_FW_TYPE_PSP_RL, 124 PSP_FW_TYPE_PSP_SOC_DRV, 125 PSP_FW_TYPE_PSP_INTF_DRV, 126 PSP_FW_TYPE_PSP_DBG_DRV, 127 }; 128 129 /* version_major=2, version_minor=0 */ 130 struct psp_firmware_header_v2_0 { 131 struct common_firmware_header header; 132 uint32_t psp_fw_bin_count; 133 struct psp_fw_bin_desc psp_fw_bin[]; 134 }; 135 136 /* version_major=1, version_minor=0 */ 137 struct ta_firmware_header_v1_0 { 138 struct common_firmware_header header; 139 struct psp_fw_legacy_bin_desc xgmi; 140 struct psp_fw_legacy_bin_desc ras; 141 struct psp_fw_legacy_bin_desc hdcp; 142 struct psp_fw_legacy_bin_desc dtm; 143 struct psp_fw_legacy_bin_desc securedisplay; 144 }; 145 146 enum ta_fw_type { 147 TA_FW_TYPE_UNKOWN, 148 TA_FW_TYPE_PSP_ASD, 149 TA_FW_TYPE_PSP_XGMI, 150 TA_FW_TYPE_PSP_RAS, 151 TA_FW_TYPE_PSP_HDCP, 152 TA_FW_TYPE_PSP_DTM, 153 TA_FW_TYPE_PSP_RAP, 154 TA_FW_TYPE_PSP_SECUREDISPLAY, 155 TA_FW_TYPE_MAX_INDEX, 156 }; 157 158 /* version_major=2, version_minor=0 */ 159 struct ta_firmware_header_v2_0 { 160 struct common_firmware_header header; 161 uint32_t ta_fw_bin_count; 162 struct psp_fw_bin_desc ta_fw_bin[]; 163 }; 164 165 /* version_major=1, version_minor=0 */ 166 struct gfx_firmware_header_v1_0 { 167 struct common_firmware_header header; 168 uint32_t ucode_feature_version; 169 uint32_t jt_offset; /* jt location */ 170 uint32_t jt_size; /* size of jt */ 171 }; 172 173 /* version_major=2, version_minor=0 */ 174 struct gfx_firmware_header_v2_0 { 175 struct common_firmware_header header; 176 uint32_t ucode_feature_version; 177 uint32_t ucode_size_bytes; 178 uint32_t ucode_offset_bytes; 179 uint32_t data_size_bytes; 180 uint32_t data_offset_bytes; 181 uint32_t ucode_start_addr_lo; 182 uint32_t ucode_start_addr_hi; 183 }; 184 185 /* version_major=1, version_minor=0 */ 186 struct mes_firmware_header_v1_0 { 187 struct common_firmware_header header; 188 uint32_t mes_ucode_version; 189 uint32_t mes_ucode_size_bytes; 190 uint32_t mes_ucode_offset_bytes; 191 uint32_t mes_ucode_data_version; 192 uint32_t mes_ucode_data_size_bytes; 193 uint32_t mes_ucode_data_offset_bytes; 194 uint32_t mes_uc_start_addr_lo; 195 uint32_t mes_uc_start_addr_hi; 196 uint32_t mes_data_start_addr_lo; 197 uint32_t mes_data_start_addr_hi; 198 }; 199 200 /* version_major=1, version_minor=0 */ 201 struct rlc_firmware_header_v1_0 { 202 struct common_firmware_header header; 203 uint32_t ucode_feature_version; 204 uint32_t save_and_restore_offset; 205 uint32_t clear_state_descriptor_offset; 206 uint32_t avail_scratch_ram_locations; 207 uint32_t master_pkt_description_offset; 208 }; 209 210 /* version_major=2, version_minor=0 */ 211 struct rlc_firmware_header_v2_0 { 212 struct common_firmware_header header; 213 uint32_t ucode_feature_version; 214 uint32_t jt_offset; /* jt location */ 215 uint32_t jt_size; /* size of jt */ 216 uint32_t save_and_restore_offset; 217 uint32_t clear_state_descriptor_offset; 218 uint32_t avail_scratch_ram_locations; 219 uint32_t reg_restore_list_size; 220 uint32_t reg_list_format_start; 221 uint32_t reg_list_format_separate_start; 222 uint32_t starting_offsets_start; 223 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 224 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 225 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 226 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 227 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 228 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 229 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 230 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 231 }; 232 233 /* version_major=2, version_minor=1 */ 234 struct rlc_firmware_header_v2_1 { 235 struct rlc_firmware_header_v2_0 v2_0; 236 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 237 uint32_t save_restore_list_cntl_ucode_ver; 238 uint32_t save_restore_list_cntl_feature_ver; 239 uint32_t save_restore_list_cntl_size_bytes; 240 uint32_t save_restore_list_cntl_offset_bytes; 241 uint32_t save_restore_list_gpm_ucode_ver; 242 uint32_t save_restore_list_gpm_feature_ver; 243 uint32_t save_restore_list_gpm_size_bytes; 244 uint32_t save_restore_list_gpm_offset_bytes; 245 uint32_t save_restore_list_srm_ucode_ver; 246 uint32_t save_restore_list_srm_feature_ver; 247 uint32_t save_restore_list_srm_size_bytes; 248 uint32_t save_restore_list_srm_offset_bytes; 249 }; 250 251 /* version_major=2, version_minor=2 */ 252 struct rlc_firmware_header_v2_2 { 253 struct rlc_firmware_header_v2_1 v2_1; 254 uint32_t rlc_iram_ucode_size_bytes; 255 uint32_t rlc_iram_ucode_offset_bytes; 256 uint32_t rlc_dram_ucode_size_bytes; 257 uint32_t rlc_dram_ucode_offset_bytes; 258 }; 259 260 /* version_major=2, version_minor=3 */ 261 struct rlc_firmware_header_v2_3 { 262 struct rlc_firmware_header_v2_2 v2_2; 263 uint32_t rlcp_ucode_version; 264 uint32_t rlcp_ucode_feature_version; 265 uint32_t rlcp_ucode_size_bytes; 266 uint32_t rlcp_ucode_offset_bytes; 267 uint32_t rlcv_ucode_version; 268 uint32_t rlcv_ucode_feature_version; 269 uint32_t rlcv_ucode_size_bytes; 270 uint32_t rlcv_ucode_offset_bytes; 271 }; 272 273 /* version_major=2, version_minor=4 */ 274 struct rlc_firmware_header_v2_4 { 275 struct rlc_firmware_header_v2_3 v2_3; 276 uint32_t global_tap_delays_ucode_size_bytes; 277 uint32_t global_tap_delays_ucode_offset_bytes; 278 uint32_t se0_tap_delays_ucode_size_bytes; 279 uint32_t se0_tap_delays_ucode_offset_bytes; 280 uint32_t se1_tap_delays_ucode_size_bytes; 281 uint32_t se1_tap_delays_ucode_offset_bytes; 282 uint32_t se2_tap_delays_ucode_size_bytes; 283 uint32_t se2_tap_delays_ucode_offset_bytes; 284 uint32_t se3_tap_delays_ucode_size_bytes; 285 uint32_t se3_tap_delays_ucode_offset_bytes; 286 }; 287 288 /* version_major=1, version_minor=0 */ 289 struct sdma_firmware_header_v1_0 { 290 struct common_firmware_header header; 291 uint32_t ucode_feature_version; 292 uint32_t ucode_change_version; 293 uint32_t jt_offset; /* jt location */ 294 uint32_t jt_size; /* size of jt */ 295 }; 296 297 /* version_major=1, version_minor=1 */ 298 struct sdma_firmware_header_v1_1 { 299 struct sdma_firmware_header_v1_0 v1_0; 300 uint32_t digest_size; 301 }; 302 303 /* version_major=2, version_minor=0 */ 304 struct sdma_firmware_header_v2_0 { 305 struct common_firmware_header header; 306 uint32_t ucode_feature_version; 307 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 308 uint32_t ctx_jt_offset; /* context thread jt location */ 309 uint32_t ctx_jt_size; /* context thread size of jt */ 310 uint32_t ctl_ucode_offset; 311 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 312 uint32_t ctl_jt_offset; /* control thread jt location */ 313 uint32_t ctl_jt_size; /* control thread size of jt */ 314 }; 315 316 /* gpu info payload */ 317 struct gpu_info_firmware_v1_0 { 318 uint32_t gc_num_se; 319 uint32_t gc_num_cu_per_sh; 320 uint32_t gc_num_sh_per_se; 321 uint32_t gc_num_rb_per_se; 322 uint32_t gc_num_tccs; 323 uint32_t gc_num_gprs; 324 uint32_t gc_num_max_gs_thds; 325 uint32_t gc_gs_table_depth; 326 uint32_t gc_gsprim_buff_depth; 327 uint32_t gc_parameter_cache_depth; 328 uint32_t gc_double_offchip_lds_buffer; 329 uint32_t gc_wave_size; 330 uint32_t gc_max_waves_per_simd; 331 uint32_t gc_max_scratch_slots_per_cu; 332 uint32_t gc_lds_size; 333 }; 334 335 struct gpu_info_firmware_v1_1 { 336 struct gpu_info_firmware_v1_0 v1_0; 337 uint32_t num_sc_per_sh; 338 uint32_t num_packer_per_sc; 339 }; 340 341 /* gpu info payload 342 * version_major=1, version_minor=1 */ 343 struct gpu_info_firmware_v1_2 { 344 struct gpu_info_firmware_v1_1 v1_1; 345 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 346 }; 347 348 /* version_major=1, version_minor=0 */ 349 struct gpu_info_firmware_header_v1_0 { 350 struct common_firmware_header header; 351 uint16_t version_major; /* version */ 352 uint16_t version_minor; /* version */ 353 }; 354 355 /* version_major=1, version_minor=0 */ 356 struct dmcu_firmware_header_v1_0 { 357 struct common_firmware_header header; 358 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 359 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 360 }; 361 362 /* version_major=1, version_minor=0 */ 363 struct dmcub_firmware_header_v1_0 { 364 struct common_firmware_header header; 365 uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 366 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 367 }; 368 369 /* version_major=1, version_minor=0 */ 370 struct imu_firmware_header_v1_0 { 371 struct common_firmware_header header; 372 uint32_t imu_iram_ucode_size_bytes; 373 uint32_t imu_iram_ucode_offset_bytes; 374 uint32_t imu_dram_ucode_size_bytes; 375 uint32_t imu_dram_ucode_offset_bytes; 376 }; 377 378 /* header is fixed size */ 379 union amdgpu_firmware_header { 380 struct common_firmware_header common; 381 struct mc_firmware_header_v1_0 mc; 382 struct smc_firmware_header_v1_0 smc; 383 struct smc_firmware_header_v2_0 smc_v2_0; 384 struct psp_firmware_header_v1_0 psp; 385 struct psp_firmware_header_v1_1 psp_v1_1; 386 struct psp_firmware_header_v1_3 psp_v1_3; 387 struct psp_firmware_header_v2_0 psp_v2_0; 388 struct ta_firmware_header_v1_0 ta; 389 struct ta_firmware_header_v2_0 ta_v2_0; 390 struct gfx_firmware_header_v1_0 gfx; 391 struct gfx_firmware_header_v2_0 gfx_v2_0; 392 struct rlc_firmware_header_v1_0 rlc; 393 struct rlc_firmware_header_v2_0 rlc_v2_0; 394 struct rlc_firmware_header_v2_1 rlc_v2_1; 395 struct rlc_firmware_header_v2_2 rlc_v2_2; 396 struct rlc_firmware_header_v2_3 rlc_v2_3; 397 struct rlc_firmware_header_v2_4 rlc_v2_4; 398 struct sdma_firmware_header_v1_0 sdma; 399 struct sdma_firmware_header_v1_1 sdma_v1_1; 400 struct sdma_firmware_header_v2_0 sdma_v2_0; 401 struct gpu_info_firmware_header_v1_0 gpu_info; 402 struct dmcu_firmware_header_v1_0 dmcu; 403 struct dmcub_firmware_header_v1_0 dmcub; 404 struct imu_firmware_header_v1_0 imu; 405 uint8_t raw[0x100]; 406 }; 407 408 #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) 409 410 /* 411 * fw loading support 412 */ 413 enum AMDGPU_UCODE_ID { 414 AMDGPU_UCODE_ID_CAP = 0, 415 AMDGPU_UCODE_ID_SDMA0, 416 AMDGPU_UCODE_ID_SDMA1, 417 AMDGPU_UCODE_ID_SDMA2, 418 AMDGPU_UCODE_ID_SDMA3, 419 AMDGPU_UCODE_ID_SDMA4, 420 AMDGPU_UCODE_ID_SDMA5, 421 AMDGPU_UCODE_ID_SDMA6, 422 AMDGPU_UCODE_ID_SDMA7, 423 AMDGPU_UCODE_ID_SDMA_UCODE_TH0, 424 AMDGPU_UCODE_ID_SDMA_UCODE_TH1, 425 AMDGPU_UCODE_ID_CP_CE, 426 AMDGPU_UCODE_ID_CP_PFP, 427 AMDGPU_UCODE_ID_CP_ME, 428 AMDGPU_UCODE_ID_CP_RS64_PFP, 429 AMDGPU_UCODE_ID_CP_RS64_ME, 430 AMDGPU_UCODE_ID_CP_RS64_MEC, 431 AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, 432 AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, 433 AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, 434 AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, 435 AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, 436 AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, 437 AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, 438 AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, 439 AMDGPU_UCODE_ID_CP_MEC1, 440 AMDGPU_UCODE_ID_CP_MEC1_JT, 441 AMDGPU_UCODE_ID_CP_MEC2, 442 AMDGPU_UCODE_ID_CP_MEC2_JT, 443 AMDGPU_UCODE_ID_CP_MES, 444 AMDGPU_UCODE_ID_CP_MES_DATA, 445 AMDGPU_UCODE_ID_CP_MES1, 446 AMDGPU_UCODE_ID_CP_MES1_DATA, 447 AMDGPU_UCODE_ID_IMU_I, 448 AMDGPU_UCODE_ID_IMU_D, 449 AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS, 450 AMDGPU_UCODE_ID_SE0_TAP_DELAYS, 451 AMDGPU_UCODE_ID_SE1_TAP_DELAYS, 452 AMDGPU_UCODE_ID_SE2_TAP_DELAYS, 453 AMDGPU_UCODE_ID_SE3_TAP_DELAYS, 454 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 455 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 456 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 457 AMDGPU_UCODE_ID_RLC_IRAM, 458 AMDGPU_UCODE_ID_RLC_DRAM, 459 AMDGPU_UCODE_ID_RLC_P, 460 AMDGPU_UCODE_ID_RLC_V, 461 AMDGPU_UCODE_ID_RLC_G, 462 AMDGPU_UCODE_ID_STORAGE, 463 AMDGPU_UCODE_ID_SMC, 464 AMDGPU_UCODE_ID_PPTABLE, 465 AMDGPU_UCODE_ID_UVD, 466 AMDGPU_UCODE_ID_UVD1, 467 AMDGPU_UCODE_ID_VCE, 468 AMDGPU_UCODE_ID_VCN, 469 AMDGPU_UCODE_ID_VCN1, 470 AMDGPU_UCODE_ID_DMCU_ERAM, 471 AMDGPU_UCODE_ID_DMCU_INTV, 472 AMDGPU_UCODE_ID_VCN0_RAM, 473 AMDGPU_UCODE_ID_VCN1_RAM, 474 AMDGPU_UCODE_ID_DMCUB, 475 AMDGPU_UCODE_ID_MAXIMUM, 476 }; 477 478 /* engine firmware status */ 479 enum AMDGPU_UCODE_STATUS { 480 AMDGPU_UCODE_STATUS_INVALID, 481 AMDGPU_UCODE_STATUS_NOT_LOADED, 482 AMDGPU_UCODE_STATUS_LOADED, 483 }; 484 485 enum amdgpu_firmware_load_type { 486 AMDGPU_FW_LOAD_DIRECT = 0, 487 AMDGPU_FW_LOAD_PSP, 488 AMDGPU_FW_LOAD_SMU, 489 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 490 }; 491 492 /* conform to smu_ucode_xfer_cz.h */ 493 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 494 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 495 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 496 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 497 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 498 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 499 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 500 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 501 502 /* amdgpu firmware info */ 503 struct amdgpu_firmware_info { 504 /* ucode ID */ 505 enum AMDGPU_UCODE_ID ucode_id; 506 /* request_firmware */ 507 const struct firmware *fw; 508 /* starting mc address */ 509 uint64_t mc_addr; 510 /* kernel linear address */ 511 void *kaddr; 512 /* ucode_size_bytes */ 513 uint32_t ucode_size; 514 /* starting tmr mc address */ 515 uint32_t tmr_mc_addr_lo; 516 uint32_t tmr_mc_addr_hi; 517 }; 518 519 struct amdgpu_firmware { 520 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 521 enum amdgpu_firmware_load_type load_type; 522 struct amdgpu_bo *fw_buf; 523 unsigned int fw_size; 524 unsigned int max_ucodes; 525 /* firmwares are loaded by psp instead of smu from vega10 */ 526 const struct amdgpu_psp_funcs *funcs; 527 struct amdgpu_bo *rbuf; 528 struct mutex mutex; 529 530 /* gpu info firmware data pointer */ 531 const struct firmware *gpu_info_fw; 532 533 void *fw_buf_ptr; 534 uint64_t fw_buf_mc; 535 }; 536 537 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 538 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 539 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 540 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 541 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 542 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 543 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 544 int amdgpu_ucode_validate(const struct firmware *fw); 545 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 546 uint16_t hdr_major, uint16_t hdr_minor); 547 548 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 549 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 550 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 551 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 552 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 553 554 enum amdgpu_firmware_load_type 555 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 556 557 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); 558 559 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); 560 561 #endif 562