1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 #include "amdgpu_socbb.h" 27 28 struct common_firmware_header { 29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 30 uint32_t header_size_bytes; /* size of just the header in bytes */ 31 uint16_t header_version_major; /* header version */ 32 uint16_t header_version_minor; /* header version */ 33 uint16_t ip_version_major; /* IP version */ 34 uint16_t ip_version_minor; /* IP version */ 35 uint32_t ucode_version; 36 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 38 uint32_t crc32; /* crc32 checksum of the payload */ 39 }; 40 41 /* version_major=1, version_minor=0 */ 42 struct mc_firmware_header_v1_0 { 43 struct common_firmware_header header; 44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 46 }; 47 48 /* version_major=1, version_minor=0 */ 49 struct smc_firmware_header_v1_0 { 50 struct common_firmware_header header; 51 uint32_t ucode_start_addr; 52 }; 53 54 /* version_major=2, version_minor=0 */ 55 struct smc_firmware_header_v2_0 { 56 struct smc_firmware_header_v1_0 v1_0; 57 uint32_t ppt_offset_bytes; /* soft pptable offset */ 58 uint32_t ppt_size_bytes; /* soft pptable size */ 59 }; 60 61 struct smc_soft_pptable_entry { 62 uint32_t id; 63 uint32_t ppt_offset_bytes; 64 uint32_t ppt_size_bytes; 65 }; 66 67 /* version_major=2, version_minor=1 */ 68 struct smc_firmware_header_v2_1 { 69 struct smc_firmware_header_v1_0 v1_0; 70 uint32_t pptable_count; 71 uint32_t pptable_entry_offset; 72 }; 73 74 /* version_major=1, version_minor=0 */ 75 struct psp_firmware_header_v1_0 { 76 struct common_firmware_header header; 77 uint32_t ucode_feature_version; 78 uint32_t sos_offset_bytes; 79 uint32_t sos_size_bytes; 80 }; 81 82 /* version_major=1, version_minor=1 */ 83 struct psp_firmware_header_v1_1 { 84 struct psp_firmware_header_v1_0 v1_0; 85 uint32_t toc_header_version; 86 uint32_t toc_offset_bytes; 87 uint32_t toc_size_bytes; 88 uint32_t kdb_header_version; 89 uint32_t kdb_offset_bytes; 90 uint32_t kdb_size_bytes; 91 }; 92 93 /* version_major=1, version_minor=2 */ 94 struct psp_firmware_header_v1_2 { 95 struct psp_firmware_header_v1_0 v1_0; 96 uint32_t reserve[3]; 97 uint32_t kdb_header_version; 98 uint32_t kdb_offset_bytes; 99 uint32_t kdb_size_bytes; 100 }; 101 102 /* version_major=1, version_minor=3 */ 103 struct psp_firmware_header_v1_3 { 104 struct psp_firmware_header_v1_1 v1_1; 105 uint32_t spl_header_version; 106 uint32_t spl_offset_bytes; 107 uint32_t spl_size_bytes; 108 }; 109 110 /* version_major=1, version_minor=0 */ 111 struct ta_firmware_header_v1_0 { 112 struct common_firmware_header header; 113 uint32_t ta_xgmi_ucode_version; 114 uint32_t ta_xgmi_offset_bytes; 115 uint32_t ta_xgmi_size_bytes; 116 uint32_t ta_ras_ucode_version; 117 uint32_t ta_ras_offset_bytes; 118 uint32_t ta_ras_size_bytes; 119 uint32_t ta_hdcp_ucode_version; 120 uint32_t ta_hdcp_offset_bytes; 121 uint32_t ta_hdcp_size_bytes; 122 uint32_t ta_dtm_ucode_version; 123 uint32_t ta_dtm_offset_bytes; 124 uint32_t ta_dtm_size_bytes; 125 }; 126 127 enum ta_fw_type { 128 TA_FW_TYPE_UNKOWN, 129 TA_FW_TYPE_PSP_ASD, 130 TA_FW_TYPE_PSP_XGMI, 131 TA_FW_TYPE_PSP_RAS, 132 TA_FW_TYPE_PSP_HDCP, 133 TA_FW_TYPE_PSP_DTM, 134 }; 135 136 struct ta_fw_bin_desc { 137 uint32_t fw_type; 138 uint32_t fw_version; 139 uint32_t offset_bytes; 140 uint32_t size_bytes; 141 }; 142 143 /* version_major=2, version_minor=0 */ 144 struct ta_firmware_header_v2_0 { 145 struct common_firmware_header header; 146 uint32_t ta_fw_bin_count; 147 struct ta_fw_bin_desc ta_fw_bin[]; 148 }; 149 150 /* version_major=1, version_minor=0 */ 151 struct gfx_firmware_header_v1_0 { 152 struct common_firmware_header header; 153 uint32_t ucode_feature_version; 154 uint32_t jt_offset; /* jt location */ 155 uint32_t jt_size; /* size of jt */ 156 }; 157 158 /* version_major=1, version_minor=0 */ 159 struct mes_firmware_header_v1_0 { 160 struct common_firmware_header header; 161 uint32_t mes_ucode_version; 162 uint32_t mes_ucode_size_bytes; 163 uint32_t mes_ucode_offset_bytes; 164 uint32_t mes_ucode_data_version; 165 uint32_t mes_ucode_data_size_bytes; 166 uint32_t mes_ucode_data_offset_bytes; 167 uint32_t mes_uc_start_addr_lo; 168 uint32_t mes_uc_start_addr_hi; 169 uint32_t mes_data_start_addr_lo; 170 uint32_t mes_data_start_addr_hi; 171 }; 172 173 /* version_major=1, version_minor=0 */ 174 struct rlc_firmware_header_v1_0 { 175 struct common_firmware_header header; 176 uint32_t ucode_feature_version; 177 uint32_t save_and_restore_offset; 178 uint32_t clear_state_descriptor_offset; 179 uint32_t avail_scratch_ram_locations; 180 uint32_t master_pkt_description_offset; 181 }; 182 183 /* version_major=2, version_minor=0 */ 184 struct rlc_firmware_header_v2_0 { 185 struct common_firmware_header header; 186 uint32_t ucode_feature_version; 187 uint32_t jt_offset; /* jt location */ 188 uint32_t jt_size; /* size of jt */ 189 uint32_t save_and_restore_offset; 190 uint32_t clear_state_descriptor_offset; 191 uint32_t avail_scratch_ram_locations; 192 uint32_t reg_restore_list_size; 193 uint32_t reg_list_format_start; 194 uint32_t reg_list_format_separate_start; 195 uint32_t starting_offsets_start; 196 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 197 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 198 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 199 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 200 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 201 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 202 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 203 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 204 }; 205 206 /* version_major=2, version_minor=1 */ 207 struct rlc_firmware_header_v2_1 { 208 struct rlc_firmware_header_v2_0 v2_0; 209 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 210 uint32_t save_restore_list_cntl_ucode_ver; 211 uint32_t save_restore_list_cntl_feature_ver; 212 uint32_t save_restore_list_cntl_size_bytes; 213 uint32_t save_restore_list_cntl_offset_bytes; 214 uint32_t save_restore_list_gpm_ucode_ver; 215 uint32_t save_restore_list_gpm_feature_ver; 216 uint32_t save_restore_list_gpm_size_bytes; 217 uint32_t save_restore_list_gpm_offset_bytes; 218 uint32_t save_restore_list_srm_ucode_ver; 219 uint32_t save_restore_list_srm_feature_ver; 220 uint32_t save_restore_list_srm_size_bytes; 221 uint32_t save_restore_list_srm_offset_bytes; 222 }; 223 224 /* version_major=1, version_minor=0 */ 225 struct sdma_firmware_header_v1_0 { 226 struct common_firmware_header header; 227 uint32_t ucode_feature_version; 228 uint32_t ucode_change_version; 229 uint32_t jt_offset; /* jt location */ 230 uint32_t jt_size; /* size of jt */ 231 }; 232 233 /* version_major=1, version_minor=1 */ 234 struct sdma_firmware_header_v1_1 { 235 struct sdma_firmware_header_v1_0 v1_0; 236 uint32_t digest_size; 237 }; 238 239 /* gpu info payload */ 240 struct gpu_info_firmware_v1_0 { 241 uint32_t gc_num_se; 242 uint32_t gc_num_cu_per_sh; 243 uint32_t gc_num_sh_per_se; 244 uint32_t gc_num_rb_per_se; 245 uint32_t gc_num_tccs; 246 uint32_t gc_num_gprs; 247 uint32_t gc_num_max_gs_thds; 248 uint32_t gc_gs_table_depth; 249 uint32_t gc_gsprim_buff_depth; 250 uint32_t gc_parameter_cache_depth; 251 uint32_t gc_double_offchip_lds_buffer; 252 uint32_t gc_wave_size; 253 uint32_t gc_max_waves_per_simd; 254 uint32_t gc_max_scratch_slots_per_cu; 255 uint32_t gc_lds_size; 256 }; 257 258 struct gpu_info_firmware_v1_1 { 259 struct gpu_info_firmware_v1_0 v1_0; 260 uint32_t num_sc_per_sh; 261 uint32_t num_packer_per_sc; 262 }; 263 264 /* gpu info payload 265 * version_major=1, version_minor=1 */ 266 struct gpu_info_firmware_v1_2 { 267 struct gpu_info_firmware_v1_1 v1_1; 268 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 269 }; 270 271 /* version_major=1, version_minor=0 */ 272 struct gpu_info_firmware_header_v1_0 { 273 struct common_firmware_header header; 274 uint16_t version_major; /* version */ 275 uint16_t version_minor; /* version */ 276 }; 277 278 /* version_major=1, version_minor=0 */ 279 struct dmcu_firmware_header_v1_0 { 280 struct common_firmware_header header; 281 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 282 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 283 }; 284 285 /* version_major=1, version_minor=0 */ 286 struct dmcub_firmware_header_v1_0 { 287 struct common_firmware_header header; 288 uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 289 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 290 }; 291 292 /* header is fixed size */ 293 union amdgpu_firmware_header { 294 struct common_firmware_header common; 295 struct mc_firmware_header_v1_0 mc; 296 struct smc_firmware_header_v1_0 smc; 297 struct smc_firmware_header_v2_0 smc_v2_0; 298 struct psp_firmware_header_v1_0 psp; 299 struct psp_firmware_header_v1_1 psp_v1_1; 300 struct psp_firmware_header_v1_3 psp_v1_3; 301 struct ta_firmware_header_v1_0 ta; 302 struct ta_firmware_header_v2_0 ta_v2_0; 303 struct gfx_firmware_header_v1_0 gfx; 304 struct rlc_firmware_header_v1_0 rlc; 305 struct rlc_firmware_header_v2_0 rlc_v2_0; 306 struct rlc_firmware_header_v2_1 rlc_v2_1; 307 struct sdma_firmware_header_v1_0 sdma; 308 struct sdma_firmware_header_v1_1 sdma_v1_1; 309 struct gpu_info_firmware_header_v1_0 gpu_info; 310 struct dmcu_firmware_header_v1_0 dmcu; 311 struct dmcub_firmware_header_v1_0 dmcub; 312 uint8_t raw[0x100]; 313 }; 314 315 #define UCODE_MAX_TA_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct ta_fw_bin_desc)) 316 317 /* 318 * fw loading support 319 */ 320 enum AMDGPU_UCODE_ID { 321 AMDGPU_UCODE_ID_SDMA0 = 0, 322 AMDGPU_UCODE_ID_SDMA1, 323 AMDGPU_UCODE_ID_SDMA2, 324 AMDGPU_UCODE_ID_SDMA3, 325 AMDGPU_UCODE_ID_SDMA4, 326 AMDGPU_UCODE_ID_SDMA5, 327 AMDGPU_UCODE_ID_SDMA6, 328 AMDGPU_UCODE_ID_SDMA7, 329 AMDGPU_UCODE_ID_CP_CE, 330 AMDGPU_UCODE_ID_CP_PFP, 331 AMDGPU_UCODE_ID_CP_ME, 332 AMDGPU_UCODE_ID_CP_MEC1, 333 AMDGPU_UCODE_ID_CP_MEC1_JT, 334 AMDGPU_UCODE_ID_CP_MEC2, 335 AMDGPU_UCODE_ID_CP_MEC2_JT, 336 AMDGPU_UCODE_ID_CP_MES, 337 AMDGPU_UCODE_ID_CP_MES_DATA, 338 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 339 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 340 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 341 AMDGPU_UCODE_ID_RLC_G, 342 AMDGPU_UCODE_ID_STORAGE, 343 AMDGPU_UCODE_ID_SMC, 344 AMDGPU_UCODE_ID_UVD, 345 AMDGPU_UCODE_ID_UVD1, 346 AMDGPU_UCODE_ID_VCE, 347 AMDGPU_UCODE_ID_VCN, 348 AMDGPU_UCODE_ID_VCN1, 349 AMDGPU_UCODE_ID_DMCU_ERAM, 350 AMDGPU_UCODE_ID_DMCU_INTV, 351 AMDGPU_UCODE_ID_VCN0_RAM, 352 AMDGPU_UCODE_ID_VCN1_RAM, 353 AMDGPU_UCODE_ID_DMCUB, 354 AMDGPU_UCODE_ID_MAXIMUM, 355 }; 356 357 /* engine firmware status */ 358 enum AMDGPU_UCODE_STATUS { 359 AMDGPU_UCODE_STATUS_INVALID, 360 AMDGPU_UCODE_STATUS_NOT_LOADED, 361 AMDGPU_UCODE_STATUS_LOADED, 362 }; 363 364 enum amdgpu_firmware_load_type { 365 AMDGPU_FW_LOAD_DIRECT = 0, 366 AMDGPU_FW_LOAD_SMU, 367 AMDGPU_FW_LOAD_PSP, 368 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 369 }; 370 371 /* conform to smu_ucode_xfer_cz.h */ 372 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 373 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 374 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 375 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 376 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 377 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 378 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 379 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 380 381 /* amdgpu firmware info */ 382 struct amdgpu_firmware_info { 383 /* ucode ID */ 384 enum AMDGPU_UCODE_ID ucode_id; 385 /* request_firmware */ 386 const struct firmware *fw; 387 /* starting mc address */ 388 uint64_t mc_addr; 389 /* kernel linear address */ 390 void *kaddr; 391 /* ucode_size_bytes */ 392 uint32_t ucode_size; 393 /* starting tmr mc address */ 394 uint32_t tmr_mc_addr_lo; 395 uint32_t tmr_mc_addr_hi; 396 }; 397 398 struct amdgpu_firmware { 399 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 400 enum amdgpu_firmware_load_type load_type; 401 struct amdgpu_bo *fw_buf; 402 unsigned int fw_size; 403 unsigned int max_ucodes; 404 /* firmwares are loaded by psp instead of smu from vega10 */ 405 const struct amdgpu_psp_funcs *funcs; 406 struct amdgpu_bo *rbuf; 407 struct mutex mutex; 408 409 /* gpu info firmware data pointer */ 410 const struct firmware *gpu_info_fw; 411 412 void *fw_buf_ptr; 413 uint64_t fw_buf_mc; 414 }; 415 416 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 417 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 418 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 419 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 420 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 421 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 422 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 423 int amdgpu_ucode_validate(const struct firmware *fw); 424 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 425 uint16_t hdr_major, uint16_t hdr_minor); 426 427 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 428 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 429 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 430 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 431 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 432 433 enum amdgpu_firmware_load_type 434 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 435 436 #endif 437