1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 #include "amdgpu_socbb.h" 27 28 struct common_firmware_header { 29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 30 uint32_t header_size_bytes; /* size of just the header in bytes */ 31 uint16_t header_version_major; /* header version */ 32 uint16_t header_version_minor; /* header version */ 33 uint16_t ip_version_major; /* IP version */ 34 uint16_t ip_version_minor; /* IP version */ 35 uint32_t ucode_version; 36 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 38 uint32_t crc32; /* crc32 checksum of the payload */ 39 }; 40 41 /* version_major=1, version_minor=0 */ 42 struct mc_firmware_header_v1_0 { 43 struct common_firmware_header header; 44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 46 }; 47 48 /* version_major=1, version_minor=0 */ 49 struct smc_firmware_header_v1_0 { 50 struct common_firmware_header header; 51 uint32_t ucode_start_addr; 52 }; 53 54 /* version_major=2, version_minor=0 */ 55 struct smc_firmware_header_v2_0 { 56 struct smc_firmware_header_v1_0 v1_0; 57 uint32_t ppt_offset_bytes; /* soft pptable offset */ 58 uint32_t ppt_size_bytes; /* soft pptable size */ 59 }; 60 61 struct smc_soft_pptable_entry { 62 uint32_t id; 63 uint32_t ppt_offset_bytes; 64 uint32_t ppt_size_bytes; 65 }; 66 67 /* version_major=2, version_minor=1 */ 68 struct smc_firmware_header_v2_1 { 69 struct smc_firmware_header_v1_0 v1_0; 70 uint32_t pptable_count; 71 uint32_t pptable_entry_offset; 72 }; 73 74 struct psp_fw_legacy_bin_desc { 75 uint32_t fw_version; 76 uint32_t offset_bytes; 77 uint32_t size_bytes; 78 }; 79 80 /* version_major=1, version_minor=0 */ 81 struct psp_firmware_header_v1_0 { 82 struct common_firmware_header header; 83 struct psp_fw_legacy_bin_desc sos; 84 }; 85 86 /* version_major=1, version_minor=1 */ 87 struct psp_firmware_header_v1_1 { 88 struct psp_firmware_header_v1_0 v1_0; 89 struct psp_fw_legacy_bin_desc toc; 90 struct psp_fw_legacy_bin_desc kdb; 91 }; 92 93 /* version_major=1, version_minor=2 */ 94 struct psp_firmware_header_v1_2 { 95 struct psp_firmware_header_v1_0 v1_0; 96 struct psp_fw_legacy_bin_desc res; 97 struct psp_fw_legacy_bin_desc kdb; 98 }; 99 100 /* version_major=1, version_minor=3 */ 101 struct psp_firmware_header_v1_3 { 102 struct psp_firmware_header_v1_1 v1_1; 103 struct psp_fw_legacy_bin_desc spl; 104 struct psp_fw_legacy_bin_desc rl; 105 struct psp_fw_legacy_bin_desc sys_drv_aux; 106 struct psp_fw_legacy_bin_desc sos_aux; 107 }; 108 109 struct psp_fw_bin_desc { 110 uint32_t fw_type; 111 uint32_t fw_version; 112 uint32_t offset_bytes; 113 uint32_t size_bytes; 114 }; 115 116 enum psp_fw_type { 117 PSP_FW_TYPE_UNKOWN, 118 PSP_FW_TYPE_PSP_SOS, 119 PSP_FW_TYPE_PSP_SYS_DRV, 120 PSP_FW_TYPE_PSP_KDB, 121 PSP_FW_TYPE_PSP_TOC, 122 PSP_FW_TYPE_PSP_SPL, 123 PSP_FW_TYPE_PSP_RL, 124 PSP_FW_TYPE_PSP_SOC_DRV, 125 PSP_FW_TYPE_PSP_INTF_DRV, 126 PSP_FW_TYPE_PSP_DBG_DRV, 127 }; 128 129 /* version_major=2, version_minor=0 */ 130 struct psp_firmware_header_v2_0 { 131 struct common_firmware_header header; 132 uint32_t psp_fw_bin_count; 133 struct psp_fw_bin_desc psp_fw_bin[]; 134 }; 135 136 /* version_major=1, version_minor=0 */ 137 struct ta_firmware_header_v1_0 { 138 struct common_firmware_header header; 139 uint32_t ta_xgmi_ucode_version; 140 uint32_t ta_xgmi_offset_bytes; 141 uint32_t ta_xgmi_size_bytes; 142 uint32_t ta_ras_ucode_version; 143 uint32_t ta_ras_offset_bytes; 144 uint32_t ta_ras_size_bytes; 145 uint32_t ta_hdcp_ucode_version; 146 uint32_t ta_hdcp_offset_bytes; 147 uint32_t ta_hdcp_size_bytes; 148 uint32_t ta_dtm_ucode_version; 149 uint32_t ta_dtm_offset_bytes; 150 uint32_t ta_dtm_size_bytes; 151 uint32_t ta_securedisplay_ucode_version; 152 uint32_t ta_securedisplay_offset_bytes; 153 uint32_t ta_securedisplay_size_bytes; 154 }; 155 156 enum ta_fw_type { 157 TA_FW_TYPE_UNKOWN, 158 TA_FW_TYPE_PSP_ASD, 159 TA_FW_TYPE_PSP_XGMI, 160 TA_FW_TYPE_PSP_RAS, 161 TA_FW_TYPE_PSP_HDCP, 162 TA_FW_TYPE_PSP_DTM, 163 TA_FW_TYPE_PSP_RAP, 164 TA_FW_TYPE_PSP_SECUREDISPLAY, 165 TA_FW_TYPE_MAX_INDEX, 166 }; 167 168 /* version_major=2, version_minor=0 */ 169 struct ta_firmware_header_v2_0 { 170 struct common_firmware_header header; 171 uint32_t ta_fw_bin_count; 172 struct psp_fw_bin_desc ta_fw_bin[]; 173 }; 174 175 /* version_major=1, version_minor=0 */ 176 struct gfx_firmware_header_v1_0 { 177 struct common_firmware_header header; 178 uint32_t ucode_feature_version; 179 uint32_t jt_offset; /* jt location */ 180 uint32_t jt_size; /* size of jt */ 181 }; 182 183 /* version_major=1, version_minor=0 */ 184 struct mes_firmware_header_v1_0 { 185 struct common_firmware_header header; 186 uint32_t mes_ucode_version; 187 uint32_t mes_ucode_size_bytes; 188 uint32_t mes_ucode_offset_bytes; 189 uint32_t mes_ucode_data_version; 190 uint32_t mes_ucode_data_size_bytes; 191 uint32_t mes_ucode_data_offset_bytes; 192 uint32_t mes_uc_start_addr_lo; 193 uint32_t mes_uc_start_addr_hi; 194 uint32_t mes_data_start_addr_lo; 195 uint32_t mes_data_start_addr_hi; 196 }; 197 198 /* version_major=1, version_minor=0 */ 199 struct rlc_firmware_header_v1_0 { 200 struct common_firmware_header header; 201 uint32_t ucode_feature_version; 202 uint32_t save_and_restore_offset; 203 uint32_t clear_state_descriptor_offset; 204 uint32_t avail_scratch_ram_locations; 205 uint32_t master_pkt_description_offset; 206 }; 207 208 /* version_major=2, version_minor=0 */ 209 struct rlc_firmware_header_v2_0 { 210 struct common_firmware_header header; 211 uint32_t ucode_feature_version; 212 uint32_t jt_offset; /* jt location */ 213 uint32_t jt_size; /* size of jt */ 214 uint32_t save_and_restore_offset; 215 uint32_t clear_state_descriptor_offset; 216 uint32_t avail_scratch_ram_locations; 217 uint32_t reg_restore_list_size; 218 uint32_t reg_list_format_start; 219 uint32_t reg_list_format_separate_start; 220 uint32_t starting_offsets_start; 221 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 222 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 223 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 224 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 225 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 226 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 227 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 228 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 229 }; 230 231 /* version_major=2, version_minor=1 */ 232 struct rlc_firmware_header_v2_1 { 233 struct rlc_firmware_header_v2_0 v2_0; 234 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 235 uint32_t save_restore_list_cntl_ucode_ver; 236 uint32_t save_restore_list_cntl_feature_ver; 237 uint32_t save_restore_list_cntl_size_bytes; 238 uint32_t save_restore_list_cntl_offset_bytes; 239 uint32_t save_restore_list_gpm_ucode_ver; 240 uint32_t save_restore_list_gpm_feature_ver; 241 uint32_t save_restore_list_gpm_size_bytes; 242 uint32_t save_restore_list_gpm_offset_bytes; 243 uint32_t save_restore_list_srm_ucode_ver; 244 uint32_t save_restore_list_srm_feature_ver; 245 uint32_t save_restore_list_srm_size_bytes; 246 uint32_t save_restore_list_srm_offset_bytes; 247 }; 248 249 /* version_major=2, version_minor=1 */ 250 struct rlc_firmware_header_v2_2 { 251 struct rlc_firmware_header_v2_1 v2_1; 252 uint32_t rlc_iram_ucode_size_bytes; 253 uint32_t rlc_iram_ucode_offset_bytes; 254 uint32_t rlc_dram_ucode_size_bytes; 255 uint32_t rlc_dram_ucode_offset_bytes; 256 }; 257 258 /* version_major=1, version_minor=0 */ 259 struct sdma_firmware_header_v1_0 { 260 struct common_firmware_header header; 261 uint32_t ucode_feature_version; 262 uint32_t ucode_change_version; 263 uint32_t jt_offset; /* jt location */ 264 uint32_t jt_size; /* size of jt */ 265 }; 266 267 /* version_major=1, version_minor=1 */ 268 struct sdma_firmware_header_v1_1 { 269 struct sdma_firmware_header_v1_0 v1_0; 270 uint32_t digest_size; 271 }; 272 273 /* gpu info payload */ 274 struct gpu_info_firmware_v1_0 { 275 uint32_t gc_num_se; 276 uint32_t gc_num_cu_per_sh; 277 uint32_t gc_num_sh_per_se; 278 uint32_t gc_num_rb_per_se; 279 uint32_t gc_num_tccs; 280 uint32_t gc_num_gprs; 281 uint32_t gc_num_max_gs_thds; 282 uint32_t gc_gs_table_depth; 283 uint32_t gc_gsprim_buff_depth; 284 uint32_t gc_parameter_cache_depth; 285 uint32_t gc_double_offchip_lds_buffer; 286 uint32_t gc_wave_size; 287 uint32_t gc_max_waves_per_simd; 288 uint32_t gc_max_scratch_slots_per_cu; 289 uint32_t gc_lds_size; 290 }; 291 292 struct gpu_info_firmware_v1_1 { 293 struct gpu_info_firmware_v1_0 v1_0; 294 uint32_t num_sc_per_sh; 295 uint32_t num_packer_per_sc; 296 }; 297 298 /* gpu info payload 299 * version_major=1, version_minor=1 */ 300 struct gpu_info_firmware_v1_2 { 301 struct gpu_info_firmware_v1_1 v1_1; 302 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 303 }; 304 305 /* version_major=1, version_minor=0 */ 306 struct gpu_info_firmware_header_v1_0 { 307 struct common_firmware_header header; 308 uint16_t version_major; /* version */ 309 uint16_t version_minor; /* version */ 310 }; 311 312 /* version_major=1, version_minor=0 */ 313 struct dmcu_firmware_header_v1_0 { 314 struct common_firmware_header header; 315 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 316 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 317 }; 318 319 /* version_major=1, version_minor=0 */ 320 struct dmcub_firmware_header_v1_0 { 321 struct common_firmware_header header; 322 uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 323 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 324 }; 325 326 /* header is fixed size */ 327 union amdgpu_firmware_header { 328 struct common_firmware_header common; 329 struct mc_firmware_header_v1_0 mc; 330 struct smc_firmware_header_v1_0 smc; 331 struct smc_firmware_header_v2_0 smc_v2_0; 332 struct psp_firmware_header_v1_0 psp; 333 struct psp_firmware_header_v1_1 psp_v1_1; 334 struct psp_firmware_header_v1_3 psp_v1_3; 335 struct psp_firmware_header_v2_0 psp_v2_0; 336 struct ta_firmware_header_v1_0 ta; 337 struct ta_firmware_header_v2_0 ta_v2_0; 338 struct gfx_firmware_header_v1_0 gfx; 339 struct rlc_firmware_header_v1_0 rlc; 340 struct rlc_firmware_header_v2_0 rlc_v2_0; 341 struct rlc_firmware_header_v2_1 rlc_v2_1; 342 struct sdma_firmware_header_v1_0 sdma; 343 struct sdma_firmware_header_v1_1 sdma_v1_1; 344 struct gpu_info_firmware_header_v1_0 gpu_info; 345 struct dmcu_firmware_header_v1_0 dmcu; 346 struct dmcub_firmware_header_v1_0 dmcub; 347 uint8_t raw[0x100]; 348 }; 349 350 #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) 351 352 /* 353 * fw loading support 354 */ 355 enum AMDGPU_UCODE_ID { 356 AMDGPU_UCODE_ID_SDMA0 = 0, 357 AMDGPU_UCODE_ID_SDMA1, 358 AMDGPU_UCODE_ID_SDMA2, 359 AMDGPU_UCODE_ID_SDMA3, 360 AMDGPU_UCODE_ID_SDMA4, 361 AMDGPU_UCODE_ID_SDMA5, 362 AMDGPU_UCODE_ID_SDMA6, 363 AMDGPU_UCODE_ID_SDMA7, 364 AMDGPU_UCODE_ID_CP_CE, 365 AMDGPU_UCODE_ID_CP_PFP, 366 AMDGPU_UCODE_ID_CP_ME, 367 AMDGPU_UCODE_ID_CP_MEC1, 368 AMDGPU_UCODE_ID_CP_MEC1_JT, 369 AMDGPU_UCODE_ID_CP_MEC2, 370 AMDGPU_UCODE_ID_CP_MEC2_JT, 371 AMDGPU_UCODE_ID_CP_MES, 372 AMDGPU_UCODE_ID_CP_MES_DATA, 373 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 374 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 375 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 376 AMDGPU_UCODE_ID_RLC_IRAM, 377 AMDGPU_UCODE_ID_RLC_DRAM, 378 AMDGPU_UCODE_ID_RLC_G, 379 AMDGPU_UCODE_ID_STORAGE, 380 AMDGPU_UCODE_ID_SMC, 381 AMDGPU_UCODE_ID_UVD, 382 AMDGPU_UCODE_ID_UVD1, 383 AMDGPU_UCODE_ID_VCE, 384 AMDGPU_UCODE_ID_VCN, 385 AMDGPU_UCODE_ID_VCN1, 386 AMDGPU_UCODE_ID_DMCU_ERAM, 387 AMDGPU_UCODE_ID_DMCU_INTV, 388 AMDGPU_UCODE_ID_VCN0_RAM, 389 AMDGPU_UCODE_ID_VCN1_RAM, 390 AMDGPU_UCODE_ID_DMCUB, 391 AMDGPU_UCODE_ID_MAXIMUM, 392 }; 393 394 /* engine firmware status */ 395 enum AMDGPU_UCODE_STATUS { 396 AMDGPU_UCODE_STATUS_INVALID, 397 AMDGPU_UCODE_STATUS_NOT_LOADED, 398 AMDGPU_UCODE_STATUS_LOADED, 399 }; 400 401 enum amdgpu_firmware_load_type { 402 AMDGPU_FW_LOAD_DIRECT = 0, 403 AMDGPU_FW_LOAD_SMU, 404 AMDGPU_FW_LOAD_PSP, 405 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 406 }; 407 408 /* conform to smu_ucode_xfer_cz.h */ 409 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 410 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 411 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 412 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 413 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 414 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 415 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 416 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 417 418 /* amdgpu firmware info */ 419 struct amdgpu_firmware_info { 420 /* ucode ID */ 421 enum AMDGPU_UCODE_ID ucode_id; 422 /* request_firmware */ 423 const struct firmware *fw; 424 /* starting mc address */ 425 uint64_t mc_addr; 426 /* kernel linear address */ 427 void *kaddr; 428 /* ucode_size_bytes */ 429 uint32_t ucode_size; 430 /* starting tmr mc address */ 431 uint32_t tmr_mc_addr_lo; 432 uint32_t tmr_mc_addr_hi; 433 }; 434 435 struct amdgpu_firmware { 436 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 437 enum amdgpu_firmware_load_type load_type; 438 struct amdgpu_bo *fw_buf; 439 unsigned int fw_size; 440 unsigned int max_ucodes; 441 /* firmwares are loaded by psp instead of smu from vega10 */ 442 const struct amdgpu_psp_funcs *funcs; 443 struct amdgpu_bo *rbuf; 444 struct mutex mutex; 445 446 /* gpu info firmware data pointer */ 447 const struct firmware *gpu_info_fw; 448 449 void *fw_buf_ptr; 450 uint64_t fw_buf_mc; 451 }; 452 453 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 454 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 455 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 456 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 457 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 458 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 459 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 460 int amdgpu_ucode_validate(const struct firmware *fw); 461 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 462 uint16_t hdr_major, uint16_t hdr_minor); 463 464 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 465 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 466 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 467 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 468 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 469 470 enum amdgpu_firmware_load_type 471 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 472 473 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); 474 475 #endif 476