1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 struct common_firmware_header { 27 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 28 uint32_t header_size_bytes; /* size of just the header in bytes */ 29 uint16_t header_version_major; /* header version */ 30 uint16_t header_version_minor; /* header version */ 31 uint16_t ip_version_major; /* IP version */ 32 uint16_t ip_version_minor; /* IP version */ 33 uint32_t ucode_version; 34 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 35 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 36 uint32_t crc32; /* crc32 checksum of the payload */ 37 }; 38 39 /* version_major=1, version_minor=0 */ 40 struct mc_firmware_header_v1_0 { 41 struct common_firmware_header header; 42 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 43 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 44 }; 45 46 /* version_major=1, version_minor=0 */ 47 struct smc_firmware_header_v1_0 { 48 struct common_firmware_header header; 49 uint32_t ucode_start_addr; 50 }; 51 52 /* version_major=1, version_minor=0 */ 53 struct psp_firmware_header_v1_0 { 54 struct common_firmware_header header; 55 uint32_t ucode_feature_version; 56 uint32_t sos_offset_bytes; 57 uint32_t sos_size_bytes; 58 }; 59 60 /* version_major=1, version_minor=0 */ 61 struct gfx_firmware_header_v1_0 { 62 struct common_firmware_header header; 63 uint32_t ucode_feature_version; 64 uint32_t jt_offset; /* jt location */ 65 uint32_t jt_size; /* size of jt */ 66 }; 67 68 /* version_major=1, version_minor=0 */ 69 struct rlc_firmware_header_v1_0 { 70 struct common_firmware_header header; 71 uint32_t ucode_feature_version; 72 uint32_t save_and_restore_offset; 73 uint32_t clear_state_descriptor_offset; 74 uint32_t avail_scratch_ram_locations; 75 uint32_t master_pkt_description_offset; 76 }; 77 78 /* version_major=2, version_minor=0 */ 79 struct rlc_firmware_header_v2_0 { 80 struct common_firmware_header header; 81 uint32_t ucode_feature_version; 82 uint32_t jt_offset; /* jt location */ 83 uint32_t jt_size; /* size of jt */ 84 uint32_t save_and_restore_offset; 85 uint32_t clear_state_descriptor_offset; 86 uint32_t avail_scratch_ram_locations; 87 uint32_t reg_restore_list_size; 88 uint32_t reg_list_format_start; 89 uint32_t reg_list_format_separate_start; 90 uint32_t starting_offsets_start; 91 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 92 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 93 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 94 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 95 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 96 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 97 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 98 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 99 }; 100 101 /* version_major=1, version_minor=0 */ 102 struct sdma_firmware_header_v1_0 { 103 struct common_firmware_header header; 104 uint32_t ucode_feature_version; 105 uint32_t ucode_change_version; 106 uint32_t jt_offset; /* jt location */ 107 uint32_t jt_size; /* size of jt */ 108 }; 109 110 /* version_major=1, version_minor=1 */ 111 struct sdma_firmware_header_v1_1 { 112 struct sdma_firmware_header_v1_0 v1_0; 113 uint32_t digest_size; 114 }; 115 116 /* header is fixed size */ 117 union amdgpu_firmware_header { 118 struct common_firmware_header common; 119 struct mc_firmware_header_v1_0 mc; 120 struct smc_firmware_header_v1_0 smc; 121 struct psp_firmware_header_v1_0 psp; 122 struct gfx_firmware_header_v1_0 gfx; 123 struct rlc_firmware_header_v1_0 rlc; 124 struct rlc_firmware_header_v2_0 rlc_v2_0; 125 struct sdma_firmware_header_v1_0 sdma; 126 struct sdma_firmware_header_v1_1 sdma_v1_1; 127 uint8_t raw[0x100]; 128 }; 129 130 /* 131 * fw loading support 132 */ 133 enum AMDGPU_UCODE_ID { 134 AMDGPU_UCODE_ID_SDMA0 = 0, 135 AMDGPU_UCODE_ID_SDMA1, 136 AMDGPU_UCODE_ID_CP_CE, 137 AMDGPU_UCODE_ID_CP_PFP, 138 AMDGPU_UCODE_ID_CP_ME, 139 AMDGPU_UCODE_ID_CP_MEC1, 140 AMDGPU_UCODE_ID_CP_MEC1_JT, 141 AMDGPU_UCODE_ID_CP_MEC2, 142 AMDGPU_UCODE_ID_CP_MEC2_JT, 143 AMDGPU_UCODE_ID_RLC_G, 144 AMDGPU_UCODE_ID_STORAGE, 145 AMDGPU_UCODE_ID_SMC, 146 AMDGPU_UCODE_ID_UVD, 147 AMDGPU_UCODE_ID_VCE, 148 AMDGPU_UCODE_ID_MAXIMUM, 149 }; 150 151 /* engine firmware status */ 152 enum AMDGPU_UCODE_STATUS { 153 AMDGPU_UCODE_STATUS_INVALID, 154 AMDGPU_UCODE_STATUS_NOT_LOADED, 155 AMDGPU_UCODE_STATUS_LOADED, 156 }; 157 158 /* conform to smu_ucode_xfer_cz.h */ 159 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 160 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 161 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 162 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 163 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 164 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 165 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 166 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 167 168 /* amdgpu firmware info */ 169 struct amdgpu_firmware_info { 170 /* ucode ID */ 171 enum AMDGPU_UCODE_ID ucode_id; 172 /* request_firmware */ 173 const struct firmware *fw; 174 /* starting mc address */ 175 uint64_t mc_addr; 176 /* kernel linear address */ 177 void *kaddr; 178 /* ucode_size_bytes */ 179 uint32_t ucode_size; 180 }; 181 182 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 183 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 184 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 185 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 186 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 187 int amdgpu_ucode_validate(const struct firmware *fw); 188 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 189 uint16_t hdr_major, uint16_t hdr_minor); 190 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 191 int amdgpu_ucode_fini_bo(struct amdgpu_device *adev); 192 193 enum amdgpu_firmware_load_type 194 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 195 196 #endif 197