1 /*
2  * Copyright 2012 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __AMDGPU_UCODE_H__
24 #define __AMDGPU_UCODE_H__
25 
26 #include "amdgpu_socbb.h"
27 
28 struct common_firmware_header {
29 	uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 	uint32_t header_size_bytes; /* size of just the header in bytes */
31 	uint16_t header_version_major; /* header version */
32 	uint16_t header_version_minor; /* header version */
33 	uint16_t ip_version_major; /* IP version */
34 	uint16_t ip_version_minor; /* IP version */
35 	uint32_t ucode_version;
36 	uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 	uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 	uint32_t crc32;  /* crc32 checksum of the payload */
39 };
40 
41 /* version_major=1, version_minor=0 */
42 struct mc_firmware_header_v1_0 {
43 	struct common_firmware_header header;
44 	uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 	uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
46 };
47 
48 /* version_major=1, version_minor=0 */
49 struct smc_firmware_header_v1_0 {
50 	struct common_firmware_header header;
51 	uint32_t ucode_start_addr;
52 };
53 
54 /* version_major=2, version_minor=0 */
55 struct smc_firmware_header_v2_0 {
56 	struct smc_firmware_header_v1_0 v1_0;
57 	uint32_t ppt_offset_bytes; /* soft pptable offset */
58 	uint32_t ppt_size_bytes; /* soft pptable size */
59 };
60 
61 struct smc_soft_pptable_entry {
62         uint32_t id;
63         uint32_t ppt_offset_bytes;
64         uint32_t ppt_size_bytes;
65 };
66 
67 /* version_major=2, version_minor=1 */
68 struct smc_firmware_header_v2_1 {
69         struct smc_firmware_header_v1_0 v1_0;
70         uint32_t pptable_count;
71         uint32_t pptable_entry_offset;
72 };
73 
74 struct psp_fw_legacy_bin_desc {
75 	uint32_t fw_version;
76 	uint32_t offset_bytes;
77 	uint32_t size_bytes;
78 };
79 
80 /* version_major=1, version_minor=0 */
81 struct psp_firmware_header_v1_0 {
82 	struct common_firmware_header header;
83 	struct psp_fw_legacy_bin_desc sos;
84 };
85 
86 /* version_major=1, version_minor=1 */
87 struct psp_firmware_header_v1_1 {
88 	struct psp_firmware_header_v1_0 v1_0;
89 	struct psp_fw_legacy_bin_desc toc;
90 	struct psp_fw_legacy_bin_desc kdb;
91 };
92 
93 /* version_major=1, version_minor=2 */
94 struct psp_firmware_header_v1_2 {
95 	struct psp_firmware_header_v1_0 v1_0;
96 	struct psp_fw_legacy_bin_desc res;
97 	struct psp_fw_legacy_bin_desc kdb;
98 };
99 
100 /* version_major=1, version_minor=3 */
101 struct psp_firmware_header_v1_3 {
102 	struct psp_firmware_header_v1_1 v1_1;
103 	struct psp_fw_legacy_bin_desc spl;
104 	struct psp_fw_legacy_bin_desc rl;
105 	struct psp_fw_legacy_bin_desc sys_drv_aux;
106 	struct psp_fw_legacy_bin_desc sos_aux;
107 };
108 
109 struct psp_fw_bin_desc {
110 	uint32_t fw_type;
111 	uint32_t fw_version;
112 	uint32_t offset_bytes;
113 	uint32_t size_bytes;
114 };
115 
116 enum psp_fw_type {
117 	PSP_FW_TYPE_UNKOWN,
118 	PSP_FW_TYPE_PSP_SOS,
119 	PSP_FW_TYPE_PSP_SYS_DRV,
120 	PSP_FW_TYPE_PSP_KDB,
121 	PSP_FW_TYPE_PSP_TOC,
122 	PSP_FW_TYPE_PSP_SPL,
123 	PSP_FW_TYPE_PSP_RL,
124 	PSP_FW_TYPE_PSP_SOC_DRV,
125 	PSP_FW_TYPE_PSP_INTF_DRV,
126 	PSP_FW_TYPE_PSP_DBG_DRV,
127 	PSP_FW_TYPE_PSP_RAS_DRV,
128 	PSP_FW_TYPE_MAX_INDEX,
129 };
130 
131 /* version_major=2, version_minor=0 */
132 struct psp_firmware_header_v2_0 {
133 	struct common_firmware_header header;
134 	uint32_t psp_fw_bin_count;
135 	struct psp_fw_bin_desc psp_fw_bin[];
136 };
137 
138 /* version_major=1, version_minor=0 */
139 struct ta_firmware_header_v1_0 {
140 	struct common_firmware_header header;
141 	struct psp_fw_legacy_bin_desc xgmi;
142 	struct psp_fw_legacy_bin_desc ras;
143 	struct psp_fw_legacy_bin_desc hdcp;
144 	struct psp_fw_legacy_bin_desc dtm;
145 	struct psp_fw_legacy_bin_desc securedisplay;
146 };
147 
148 enum ta_fw_type {
149 	TA_FW_TYPE_UNKOWN,
150 	TA_FW_TYPE_PSP_ASD,
151 	TA_FW_TYPE_PSP_XGMI,
152 	TA_FW_TYPE_PSP_RAS,
153 	TA_FW_TYPE_PSP_HDCP,
154 	TA_FW_TYPE_PSP_DTM,
155 	TA_FW_TYPE_PSP_RAP,
156 	TA_FW_TYPE_PSP_SECUREDISPLAY,
157 	TA_FW_TYPE_MAX_INDEX,
158 };
159 
160 /* version_major=2, version_minor=0 */
161 struct ta_firmware_header_v2_0 {
162 	struct common_firmware_header header;
163 	uint32_t ta_fw_bin_count;
164 	struct psp_fw_bin_desc ta_fw_bin[];
165 };
166 
167 /* version_major=1, version_minor=0 */
168 struct gfx_firmware_header_v1_0 {
169 	struct common_firmware_header header;
170 	uint32_t ucode_feature_version;
171 	uint32_t jt_offset; /* jt location */
172 	uint32_t jt_size;  /* size of jt */
173 };
174 
175 /* version_major=2, version_minor=0 */
176 struct gfx_firmware_header_v2_0 {
177 	struct common_firmware_header header;
178 	uint32_t ucode_feature_version;
179 	uint32_t ucode_size_bytes;
180 	uint32_t ucode_offset_bytes;
181 	uint32_t data_size_bytes;
182 	uint32_t data_offset_bytes;
183 	uint32_t ucode_start_addr_lo;
184 	uint32_t ucode_start_addr_hi;
185 };
186 
187 /* version_major=1, version_minor=0 */
188 struct mes_firmware_header_v1_0 {
189 	struct common_firmware_header header;
190 	uint32_t mes_ucode_version;
191 	uint32_t mes_ucode_size_bytes;
192 	uint32_t mes_ucode_offset_bytes;
193 	uint32_t mes_ucode_data_version;
194 	uint32_t mes_ucode_data_size_bytes;
195 	uint32_t mes_ucode_data_offset_bytes;
196 	uint32_t mes_uc_start_addr_lo;
197 	uint32_t mes_uc_start_addr_hi;
198 	uint32_t mes_data_start_addr_lo;
199 	uint32_t mes_data_start_addr_hi;
200 };
201 
202 /* version_major=1, version_minor=0 */
203 struct rlc_firmware_header_v1_0 {
204 	struct common_firmware_header header;
205 	uint32_t ucode_feature_version;
206 	uint32_t save_and_restore_offset;
207 	uint32_t clear_state_descriptor_offset;
208 	uint32_t avail_scratch_ram_locations;
209 	uint32_t master_pkt_description_offset;
210 };
211 
212 /* version_major=2, version_minor=0 */
213 struct rlc_firmware_header_v2_0 {
214 	struct common_firmware_header header;
215 	uint32_t ucode_feature_version;
216 	uint32_t jt_offset; /* jt location */
217 	uint32_t jt_size;  /* size of jt */
218 	uint32_t save_and_restore_offset;
219 	uint32_t clear_state_descriptor_offset;
220 	uint32_t avail_scratch_ram_locations;
221 	uint32_t reg_restore_list_size;
222 	uint32_t reg_list_format_start;
223 	uint32_t reg_list_format_separate_start;
224 	uint32_t starting_offsets_start;
225 	uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
226 	uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
227 	uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
228 	uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
229 	uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
230 	uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
231 	uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
232 	uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
233 };
234 
235 /* version_major=2, version_minor=1 */
236 struct rlc_firmware_header_v2_1 {
237 	struct rlc_firmware_header_v2_0 v2_0;
238 	uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
239 	uint32_t save_restore_list_cntl_ucode_ver;
240 	uint32_t save_restore_list_cntl_feature_ver;
241 	uint32_t save_restore_list_cntl_size_bytes;
242 	uint32_t save_restore_list_cntl_offset_bytes;
243 	uint32_t save_restore_list_gpm_ucode_ver;
244 	uint32_t save_restore_list_gpm_feature_ver;
245 	uint32_t save_restore_list_gpm_size_bytes;
246 	uint32_t save_restore_list_gpm_offset_bytes;
247 	uint32_t save_restore_list_srm_ucode_ver;
248 	uint32_t save_restore_list_srm_feature_ver;
249 	uint32_t save_restore_list_srm_size_bytes;
250 	uint32_t save_restore_list_srm_offset_bytes;
251 };
252 
253 /* version_major=2, version_minor=2 */
254 struct rlc_firmware_header_v2_2 {
255 	struct rlc_firmware_header_v2_1 v2_1;
256 	uint32_t rlc_iram_ucode_size_bytes;
257 	uint32_t rlc_iram_ucode_offset_bytes;
258 	uint32_t rlc_dram_ucode_size_bytes;
259 	uint32_t rlc_dram_ucode_offset_bytes;
260 };
261 
262 /* version_major=2, version_minor=3 */
263 struct rlc_firmware_header_v2_3 {
264     struct rlc_firmware_header_v2_2 v2_2;
265     uint32_t rlcp_ucode_version;
266     uint32_t rlcp_ucode_feature_version;
267     uint32_t rlcp_ucode_size_bytes;
268     uint32_t rlcp_ucode_offset_bytes;
269     uint32_t rlcv_ucode_version;
270     uint32_t rlcv_ucode_feature_version;
271     uint32_t rlcv_ucode_size_bytes;
272     uint32_t rlcv_ucode_offset_bytes;
273 };
274 
275 /* version_major=2, version_minor=4 */
276 struct rlc_firmware_header_v2_4 {
277     struct rlc_firmware_header_v2_3 v2_3;
278     uint32_t global_tap_delays_ucode_size_bytes;
279     uint32_t global_tap_delays_ucode_offset_bytes;
280     uint32_t se0_tap_delays_ucode_size_bytes;
281     uint32_t se0_tap_delays_ucode_offset_bytes;
282     uint32_t se1_tap_delays_ucode_size_bytes;
283     uint32_t se1_tap_delays_ucode_offset_bytes;
284     uint32_t se2_tap_delays_ucode_size_bytes;
285     uint32_t se2_tap_delays_ucode_offset_bytes;
286     uint32_t se3_tap_delays_ucode_size_bytes;
287     uint32_t se3_tap_delays_ucode_offset_bytes;
288 };
289 
290 /* version_major=1, version_minor=0 */
291 struct sdma_firmware_header_v1_0 {
292 	struct common_firmware_header header;
293 	uint32_t ucode_feature_version;
294 	uint32_t ucode_change_version;
295 	uint32_t jt_offset; /* jt location */
296 	uint32_t jt_size; /* size of jt */
297 };
298 
299 /* version_major=1, version_minor=1 */
300 struct sdma_firmware_header_v1_1 {
301 	struct sdma_firmware_header_v1_0 v1_0;
302 	uint32_t digest_size;
303 };
304 
305 /* version_major=2, version_minor=0 */
306 struct sdma_firmware_header_v2_0 {
307 	struct common_firmware_header header;
308 	uint32_t ucode_feature_version;
309 	uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
310 	uint32_t ctx_jt_offset; /* context thread jt location */
311 	uint32_t ctx_jt_size; /* context thread size of jt */
312 	uint32_t ctl_ucode_offset;
313 	uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
314 	uint32_t ctl_jt_offset; /* control thread jt location */
315 	uint32_t ctl_jt_size; /* control thread size of jt */
316 };
317 
318 /* gpu info payload */
319 struct gpu_info_firmware_v1_0 {
320 	uint32_t gc_num_se;
321 	uint32_t gc_num_cu_per_sh;
322 	uint32_t gc_num_sh_per_se;
323 	uint32_t gc_num_rb_per_se;
324 	uint32_t gc_num_tccs;
325 	uint32_t gc_num_gprs;
326 	uint32_t gc_num_max_gs_thds;
327 	uint32_t gc_gs_table_depth;
328 	uint32_t gc_gsprim_buff_depth;
329 	uint32_t gc_parameter_cache_depth;
330 	uint32_t gc_double_offchip_lds_buffer;
331 	uint32_t gc_wave_size;
332 	uint32_t gc_max_waves_per_simd;
333 	uint32_t gc_max_scratch_slots_per_cu;
334 	uint32_t gc_lds_size;
335 };
336 
337 struct gpu_info_firmware_v1_1 {
338 	struct gpu_info_firmware_v1_0 v1_0;
339 	uint32_t num_sc_per_sh;
340 	uint32_t num_packer_per_sc;
341 };
342 
343 /* gpu info payload
344  * version_major=1, version_minor=1 */
345 struct gpu_info_firmware_v1_2 {
346 	struct gpu_info_firmware_v1_1 v1_1;
347 	struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
348 };
349 
350 /* version_major=1, version_minor=0 */
351 struct gpu_info_firmware_header_v1_0 {
352 	struct common_firmware_header header;
353 	uint16_t version_major; /* version */
354 	uint16_t version_minor; /* version */
355 };
356 
357 /* version_major=1, version_minor=0 */
358 struct dmcu_firmware_header_v1_0 {
359 	struct common_firmware_header header;
360 	uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
361 	uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
362 };
363 
364 /* version_major=1, version_minor=0 */
365 struct dmcub_firmware_header_v1_0 {
366 	struct common_firmware_header header;
367 	uint32_t inst_const_bytes; /* size of instruction region, in bytes */
368 	uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
369 };
370 
371 /* version_major=1, version_minor=0 */
372 struct imu_firmware_header_v1_0 {
373     struct common_firmware_header header;
374     uint32_t imu_iram_ucode_size_bytes;
375     uint32_t imu_iram_ucode_offset_bytes;
376     uint32_t imu_dram_ucode_size_bytes;
377     uint32_t imu_dram_ucode_offset_bytes;
378 };
379 
380 /* header is fixed size */
381 union amdgpu_firmware_header {
382 	struct common_firmware_header common;
383 	struct mc_firmware_header_v1_0 mc;
384 	struct smc_firmware_header_v1_0 smc;
385 	struct smc_firmware_header_v2_0 smc_v2_0;
386 	struct psp_firmware_header_v1_0 psp;
387 	struct psp_firmware_header_v1_1 psp_v1_1;
388 	struct psp_firmware_header_v1_3 psp_v1_3;
389 	struct psp_firmware_header_v2_0 psp_v2_0;
390 	struct ta_firmware_header_v1_0 ta;
391 	struct ta_firmware_header_v2_0 ta_v2_0;
392 	struct gfx_firmware_header_v1_0 gfx;
393 	struct gfx_firmware_header_v2_0 gfx_v2_0;
394 	struct rlc_firmware_header_v1_0 rlc;
395 	struct rlc_firmware_header_v2_0 rlc_v2_0;
396 	struct rlc_firmware_header_v2_1 rlc_v2_1;
397 	struct rlc_firmware_header_v2_2 rlc_v2_2;
398 	struct rlc_firmware_header_v2_3 rlc_v2_3;
399 	struct rlc_firmware_header_v2_4 rlc_v2_4;
400 	struct sdma_firmware_header_v1_0 sdma;
401 	struct sdma_firmware_header_v1_1 sdma_v1_1;
402 	struct sdma_firmware_header_v2_0 sdma_v2_0;
403 	struct gpu_info_firmware_header_v1_0 gpu_info;
404 	struct dmcu_firmware_header_v1_0 dmcu;
405 	struct dmcub_firmware_header_v1_0 dmcub;
406 	struct imu_firmware_header_v1_0 imu;
407 	uint8_t raw[0x100];
408 };
409 
410 #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc))
411 
412 /*
413  * fw loading support
414  */
415 enum AMDGPU_UCODE_ID {
416 	AMDGPU_UCODE_ID_CAP = 0,
417 	AMDGPU_UCODE_ID_SDMA0,
418 	AMDGPU_UCODE_ID_SDMA1,
419 	AMDGPU_UCODE_ID_SDMA2,
420 	AMDGPU_UCODE_ID_SDMA3,
421 	AMDGPU_UCODE_ID_SDMA4,
422 	AMDGPU_UCODE_ID_SDMA5,
423 	AMDGPU_UCODE_ID_SDMA6,
424 	AMDGPU_UCODE_ID_SDMA7,
425 	AMDGPU_UCODE_ID_SDMA_UCODE_TH0,
426 	AMDGPU_UCODE_ID_SDMA_UCODE_TH1,
427 	AMDGPU_UCODE_ID_CP_CE,
428 	AMDGPU_UCODE_ID_CP_PFP,
429 	AMDGPU_UCODE_ID_CP_ME,
430 	AMDGPU_UCODE_ID_CP_RS64_PFP,
431 	AMDGPU_UCODE_ID_CP_RS64_ME,
432 	AMDGPU_UCODE_ID_CP_RS64_MEC,
433 	AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,
434 	AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,
435 	AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,
436 	AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,
437 	AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,
438 	AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,
439 	AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,
440 	AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,
441 	AMDGPU_UCODE_ID_CP_MEC1,
442 	AMDGPU_UCODE_ID_CP_MEC1_JT,
443 	AMDGPU_UCODE_ID_CP_MEC2,
444 	AMDGPU_UCODE_ID_CP_MEC2_JT,
445 	AMDGPU_UCODE_ID_CP_MES,
446 	AMDGPU_UCODE_ID_CP_MES_DATA,
447 	AMDGPU_UCODE_ID_CP_MES1,
448 	AMDGPU_UCODE_ID_CP_MES1_DATA,
449 	AMDGPU_UCODE_ID_IMU_I,
450 	AMDGPU_UCODE_ID_IMU_D,
451 	AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS,
452 	AMDGPU_UCODE_ID_SE0_TAP_DELAYS,
453 	AMDGPU_UCODE_ID_SE1_TAP_DELAYS,
454 	AMDGPU_UCODE_ID_SE2_TAP_DELAYS,
455 	AMDGPU_UCODE_ID_SE3_TAP_DELAYS,
456 	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
457 	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
458 	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
459 	AMDGPU_UCODE_ID_RLC_IRAM,
460 	AMDGPU_UCODE_ID_RLC_DRAM,
461 	AMDGPU_UCODE_ID_RLC_P,
462 	AMDGPU_UCODE_ID_RLC_V,
463 	AMDGPU_UCODE_ID_RLC_G,
464 	AMDGPU_UCODE_ID_STORAGE,
465 	AMDGPU_UCODE_ID_SMC,
466 	AMDGPU_UCODE_ID_PPTABLE,
467 	AMDGPU_UCODE_ID_UVD,
468 	AMDGPU_UCODE_ID_UVD1,
469 	AMDGPU_UCODE_ID_VCE,
470 	AMDGPU_UCODE_ID_VCN,
471 	AMDGPU_UCODE_ID_VCN1,
472 	AMDGPU_UCODE_ID_DMCU_ERAM,
473 	AMDGPU_UCODE_ID_DMCU_INTV,
474 	AMDGPU_UCODE_ID_VCN0_RAM,
475 	AMDGPU_UCODE_ID_VCN1_RAM,
476 	AMDGPU_UCODE_ID_DMCUB,
477 	AMDGPU_UCODE_ID_MAXIMUM,
478 };
479 
480 /* engine firmware status */
481 enum AMDGPU_UCODE_STATUS {
482 	AMDGPU_UCODE_STATUS_INVALID,
483 	AMDGPU_UCODE_STATUS_NOT_LOADED,
484 	AMDGPU_UCODE_STATUS_LOADED,
485 };
486 
487 enum amdgpu_firmware_load_type {
488 	AMDGPU_FW_LOAD_DIRECT = 0,
489 	AMDGPU_FW_LOAD_PSP,
490 	AMDGPU_FW_LOAD_SMU,
491 	AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
492 };
493 
494 /* conform to smu_ucode_xfer_cz.h */
495 #define AMDGPU_SDMA0_UCODE_LOADED	0x00000001
496 #define AMDGPU_SDMA1_UCODE_LOADED	0x00000002
497 #define AMDGPU_CPCE_UCODE_LOADED	0x00000004
498 #define AMDGPU_CPPFP_UCODE_LOADED	0x00000008
499 #define AMDGPU_CPME_UCODE_LOADED	0x00000010
500 #define AMDGPU_CPMEC1_UCODE_LOADED	0x00000020
501 #define AMDGPU_CPMEC2_UCODE_LOADED	0x00000040
502 #define AMDGPU_CPRLC_UCODE_LOADED	0x00000100
503 
504 /* amdgpu firmware info */
505 struct amdgpu_firmware_info {
506 	/* ucode ID */
507 	enum AMDGPU_UCODE_ID ucode_id;
508 	/* request_firmware */
509 	const struct firmware *fw;
510 	/* starting mc address */
511 	uint64_t mc_addr;
512 	/* kernel linear address */
513 	void *kaddr;
514 	/* ucode_size_bytes */
515 	uint32_t ucode_size;
516 	/* starting tmr mc address */
517 	uint32_t tmr_mc_addr_lo;
518 	uint32_t tmr_mc_addr_hi;
519 };
520 
521 struct amdgpu_firmware {
522 	struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
523 	enum amdgpu_firmware_load_type load_type;
524 	struct amdgpu_bo *fw_buf;
525 	unsigned int fw_size;
526 	unsigned int max_ucodes;
527 	/* firmwares are loaded by psp instead of smu from vega10 */
528 	const struct amdgpu_psp_funcs *funcs;
529 	struct amdgpu_bo *rbuf;
530 	struct mutex mutex;
531 
532 	/* gpu info firmware data pointer */
533 	const struct firmware *gpu_info_fw;
534 
535 	void *fw_buf_ptr;
536 	uint64_t fw_buf_mc;
537 };
538 
539 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
540 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
541 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
542 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
543 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
544 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
545 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
546 int amdgpu_ucode_validate(const struct firmware *fw);
547 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
548 				uint16_t hdr_major, uint16_t hdr_minor);
549 
550 int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
551 int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
552 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
553 void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
554 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
555 
556 enum amdgpu_firmware_load_type
557 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
558 
559 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
560 
561 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);
562 
563 #endif
564