1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 #include "amdgpu_socbb.h" 27 28 struct common_firmware_header { 29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 30 uint32_t header_size_bytes; /* size of just the header in bytes */ 31 uint16_t header_version_major; /* header version */ 32 uint16_t header_version_minor; /* header version */ 33 uint16_t ip_version_major; /* IP version */ 34 uint16_t ip_version_minor; /* IP version */ 35 uint32_t ucode_version; 36 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 38 uint32_t crc32; /* crc32 checksum of the payload */ 39 }; 40 41 /* version_major=1, version_minor=0 */ 42 struct mc_firmware_header_v1_0 { 43 struct common_firmware_header header; 44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 46 }; 47 48 /* version_major=1, version_minor=0 */ 49 struct smc_firmware_header_v1_0 { 50 struct common_firmware_header header; 51 uint32_t ucode_start_addr; 52 }; 53 54 /* version_major=2, version_minor=0 */ 55 struct smc_firmware_header_v2_0 { 56 struct smc_firmware_header_v1_0 v1_0; 57 uint32_t ppt_offset_bytes; /* soft pptable offset */ 58 uint32_t ppt_size_bytes; /* soft pptable size */ 59 }; 60 61 struct smc_soft_pptable_entry { 62 uint32_t id; 63 uint32_t ppt_offset_bytes; 64 uint32_t ppt_size_bytes; 65 }; 66 67 /* version_major=2, version_minor=1 */ 68 struct smc_firmware_header_v2_1 { 69 struct smc_firmware_header_v1_0 v1_0; 70 uint32_t pptable_count; 71 uint32_t pptable_entry_offset; 72 }; 73 74 struct psp_fw_legacy_bin_desc { 75 uint32_t fw_version; 76 uint32_t offset_bytes; 77 uint32_t size_bytes; 78 }; 79 80 /* version_major=1, version_minor=0 */ 81 struct psp_firmware_header_v1_0 { 82 struct common_firmware_header header; 83 struct psp_fw_legacy_bin_desc sos; 84 }; 85 86 /* version_major=1, version_minor=1 */ 87 struct psp_firmware_header_v1_1 { 88 struct psp_firmware_header_v1_0 v1_0; 89 struct psp_fw_legacy_bin_desc toc; 90 struct psp_fw_legacy_bin_desc kdb; 91 }; 92 93 /* version_major=1, version_minor=2 */ 94 struct psp_firmware_header_v1_2 { 95 struct psp_firmware_header_v1_0 v1_0; 96 struct psp_fw_legacy_bin_desc res; 97 struct psp_fw_legacy_bin_desc kdb; 98 }; 99 100 /* version_major=1, version_minor=3 */ 101 struct psp_firmware_header_v1_3 { 102 struct psp_firmware_header_v1_1 v1_1; 103 struct psp_fw_legacy_bin_desc spl; 104 struct psp_fw_legacy_bin_desc rl; 105 struct psp_fw_legacy_bin_desc sys_drv_aux; 106 struct psp_fw_legacy_bin_desc sos_aux; 107 }; 108 109 struct psp_fw_bin_desc { 110 uint32_t fw_type; 111 uint32_t fw_version; 112 uint32_t offset_bytes; 113 uint32_t size_bytes; 114 }; 115 116 enum psp_fw_type { 117 PSP_FW_TYPE_UNKOWN, 118 PSP_FW_TYPE_PSP_SOS, 119 PSP_FW_TYPE_PSP_SYS_DRV, 120 PSP_FW_TYPE_PSP_KDB, 121 PSP_FW_TYPE_PSP_TOC, 122 PSP_FW_TYPE_PSP_SPL, 123 PSP_FW_TYPE_PSP_RL, 124 PSP_FW_TYPE_PSP_SOC_DRV, 125 PSP_FW_TYPE_PSP_INTF_DRV, 126 PSP_FW_TYPE_PSP_DBG_DRV, 127 PSP_FW_TYPE_PSP_RAS_DRV, 128 }; 129 130 /* version_major=2, version_minor=0 */ 131 struct psp_firmware_header_v2_0 { 132 struct common_firmware_header header; 133 uint32_t psp_fw_bin_count; 134 struct psp_fw_bin_desc psp_fw_bin[]; 135 }; 136 137 /* version_major=1, version_minor=0 */ 138 struct ta_firmware_header_v1_0 { 139 struct common_firmware_header header; 140 struct psp_fw_legacy_bin_desc xgmi; 141 struct psp_fw_legacy_bin_desc ras; 142 struct psp_fw_legacy_bin_desc hdcp; 143 struct psp_fw_legacy_bin_desc dtm; 144 struct psp_fw_legacy_bin_desc securedisplay; 145 }; 146 147 enum ta_fw_type { 148 TA_FW_TYPE_UNKOWN, 149 TA_FW_TYPE_PSP_ASD, 150 TA_FW_TYPE_PSP_XGMI, 151 TA_FW_TYPE_PSP_RAS, 152 TA_FW_TYPE_PSP_HDCP, 153 TA_FW_TYPE_PSP_DTM, 154 TA_FW_TYPE_PSP_RAP, 155 TA_FW_TYPE_PSP_SECUREDISPLAY, 156 TA_FW_TYPE_MAX_INDEX, 157 }; 158 159 /* version_major=2, version_minor=0 */ 160 struct ta_firmware_header_v2_0 { 161 struct common_firmware_header header; 162 uint32_t ta_fw_bin_count; 163 struct psp_fw_bin_desc ta_fw_bin[]; 164 }; 165 166 /* version_major=1, version_minor=0 */ 167 struct gfx_firmware_header_v1_0 { 168 struct common_firmware_header header; 169 uint32_t ucode_feature_version; 170 uint32_t jt_offset; /* jt location */ 171 uint32_t jt_size; /* size of jt */ 172 }; 173 174 /* version_major=2, version_minor=0 */ 175 struct gfx_firmware_header_v2_0 { 176 struct common_firmware_header header; 177 uint32_t ucode_feature_version; 178 uint32_t ucode_size_bytes; 179 uint32_t ucode_offset_bytes; 180 uint32_t data_size_bytes; 181 uint32_t data_offset_bytes; 182 uint32_t ucode_start_addr_lo; 183 uint32_t ucode_start_addr_hi; 184 }; 185 186 /* version_major=1, version_minor=0 */ 187 struct mes_firmware_header_v1_0 { 188 struct common_firmware_header header; 189 uint32_t mes_ucode_version; 190 uint32_t mes_ucode_size_bytes; 191 uint32_t mes_ucode_offset_bytes; 192 uint32_t mes_ucode_data_version; 193 uint32_t mes_ucode_data_size_bytes; 194 uint32_t mes_ucode_data_offset_bytes; 195 uint32_t mes_uc_start_addr_lo; 196 uint32_t mes_uc_start_addr_hi; 197 uint32_t mes_data_start_addr_lo; 198 uint32_t mes_data_start_addr_hi; 199 }; 200 201 /* version_major=1, version_minor=0 */ 202 struct rlc_firmware_header_v1_0 { 203 struct common_firmware_header header; 204 uint32_t ucode_feature_version; 205 uint32_t save_and_restore_offset; 206 uint32_t clear_state_descriptor_offset; 207 uint32_t avail_scratch_ram_locations; 208 uint32_t master_pkt_description_offset; 209 }; 210 211 /* version_major=2, version_minor=0 */ 212 struct rlc_firmware_header_v2_0 { 213 struct common_firmware_header header; 214 uint32_t ucode_feature_version; 215 uint32_t jt_offset; /* jt location */ 216 uint32_t jt_size; /* size of jt */ 217 uint32_t save_and_restore_offset; 218 uint32_t clear_state_descriptor_offset; 219 uint32_t avail_scratch_ram_locations; 220 uint32_t reg_restore_list_size; 221 uint32_t reg_list_format_start; 222 uint32_t reg_list_format_separate_start; 223 uint32_t starting_offsets_start; 224 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 225 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 226 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 227 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 228 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 229 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 230 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 231 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 232 }; 233 234 /* version_major=2, version_minor=1 */ 235 struct rlc_firmware_header_v2_1 { 236 struct rlc_firmware_header_v2_0 v2_0; 237 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 238 uint32_t save_restore_list_cntl_ucode_ver; 239 uint32_t save_restore_list_cntl_feature_ver; 240 uint32_t save_restore_list_cntl_size_bytes; 241 uint32_t save_restore_list_cntl_offset_bytes; 242 uint32_t save_restore_list_gpm_ucode_ver; 243 uint32_t save_restore_list_gpm_feature_ver; 244 uint32_t save_restore_list_gpm_size_bytes; 245 uint32_t save_restore_list_gpm_offset_bytes; 246 uint32_t save_restore_list_srm_ucode_ver; 247 uint32_t save_restore_list_srm_feature_ver; 248 uint32_t save_restore_list_srm_size_bytes; 249 uint32_t save_restore_list_srm_offset_bytes; 250 }; 251 252 /* version_major=2, version_minor=2 */ 253 struct rlc_firmware_header_v2_2 { 254 struct rlc_firmware_header_v2_1 v2_1; 255 uint32_t rlc_iram_ucode_size_bytes; 256 uint32_t rlc_iram_ucode_offset_bytes; 257 uint32_t rlc_dram_ucode_size_bytes; 258 uint32_t rlc_dram_ucode_offset_bytes; 259 }; 260 261 /* version_major=2, version_minor=3 */ 262 struct rlc_firmware_header_v2_3 { 263 struct rlc_firmware_header_v2_2 v2_2; 264 uint32_t rlcp_ucode_version; 265 uint32_t rlcp_ucode_feature_version; 266 uint32_t rlcp_ucode_size_bytes; 267 uint32_t rlcp_ucode_offset_bytes; 268 uint32_t rlcv_ucode_version; 269 uint32_t rlcv_ucode_feature_version; 270 uint32_t rlcv_ucode_size_bytes; 271 uint32_t rlcv_ucode_offset_bytes; 272 }; 273 274 /* version_major=2, version_minor=4 */ 275 struct rlc_firmware_header_v2_4 { 276 struct rlc_firmware_header_v2_3 v2_3; 277 uint32_t global_tap_delays_ucode_size_bytes; 278 uint32_t global_tap_delays_ucode_offset_bytes; 279 uint32_t se0_tap_delays_ucode_size_bytes; 280 uint32_t se0_tap_delays_ucode_offset_bytes; 281 uint32_t se1_tap_delays_ucode_size_bytes; 282 uint32_t se1_tap_delays_ucode_offset_bytes; 283 uint32_t se2_tap_delays_ucode_size_bytes; 284 uint32_t se2_tap_delays_ucode_offset_bytes; 285 uint32_t se3_tap_delays_ucode_size_bytes; 286 uint32_t se3_tap_delays_ucode_offset_bytes; 287 }; 288 289 /* version_major=1, version_minor=0 */ 290 struct sdma_firmware_header_v1_0 { 291 struct common_firmware_header header; 292 uint32_t ucode_feature_version; 293 uint32_t ucode_change_version; 294 uint32_t jt_offset; /* jt location */ 295 uint32_t jt_size; /* size of jt */ 296 }; 297 298 /* version_major=1, version_minor=1 */ 299 struct sdma_firmware_header_v1_1 { 300 struct sdma_firmware_header_v1_0 v1_0; 301 uint32_t digest_size; 302 }; 303 304 /* version_major=2, version_minor=0 */ 305 struct sdma_firmware_header_v2_0 { 306 struct common_firmware_header header; 307 uint32_t ucode_feature_version; 308 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 309 uint32_t ctx_jt_offset; /* context thread jt location */ 310 uint32_t ctx_jt_size; /* context thread size of jt */ 311 uint32_t ctl_ucode_offset; 312 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 313 uint32_t ctl_jt_offset; /* control thread jt location */ 314 uint32_t ctl_jt_size; /* control thread size of jt */ 315 }; 316 317 /* gpu info payload */ 318 struct gpu_info_firmware_v1_0 { 319 uint32_t gc_num_se; 320 uint32_t gc_num_cu_per_sh; 321 uint32_t gc_num_sh_per_se; 322 uint32_t gc_num_rb_per_se; 323 uint32_t gc_num_tccs; 324 uint32_t gc_num_gprs; 325 uint32_t gc_num_max_gs_thds; 326 uint32_t gc_gs_table_depth; 327 uint32_t gc_gsprim_buff_depth; 328 uint32_t gc_parameter_cache_depth; 329 uint32_t gc_double_offchip_lds_buffer; 330 uint32_t gc_wave_size; 331 uint32_t gc_max_waves_per_simd; 332 uint32_t gc_max_scratch_slots_per_cu; 333 uint32_t gc_lds_size; 334 }; 335 336 struct gpu_info_firmware_v1_1 { 337 struct gpu_info_firmware_v1_0 v1_0; 338 uint32_t num_sc_per_sh; 339 uint32_t num_packer_per_sc; 340 }; 341 342 /* gpu info payload 343 * version_major=1, version_minor=1 */ 344 struct gpu_info_firmware_v1_2 { 345 struct gpu_info_firmware_v1_1 v1_1; 346 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 347 }; 348 349 /* version_major=1, version_minor=0 */ 350 struct gpu_info_firmware_header_v1_0 { 351 struct common_firmware_header header; 352 uint16_t version_major; /* version */ 353 uint16_t version_minor; /* version */ 354 }; 355 356 /* version_major=1, version_minor=0 */ 357 struct dmcu_firmware_header_v1_0 { 358 struct common_firmware_header header; 359 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 360 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 361 }; 362 363 /* version_major=1, version_minor=0 */ 364 struct dmcub_firmware_header_v1_0 { 365 struct common_firmware_header header; 366 uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 367 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 368 }; 369 370 /* version_major=1, version_minor=0 */ 371 struct imu_firmware_header_v1_0 { 372 struct common_firmware_header header; 373 uint32_t imu_iram_ucode_size_bytes; 374 uint32_t imu_iram_ucode_offset_bytes; 375 uint32_t imu_dram_ucode_size_bytes; 376 uint32_t imu_dram_ucode_offset_bytes; 377 }; 378 379 /* header is fixed size */ 380 union amdgpu_firmware_header { 381 struct common_firmware_header common; 382 struct mc_firmware_header_v1_0 mc; 383 struct smc_firmware_header_v1_0 smc; 384 struct smc_firmware_header_v2_0 smc_v2_0; 385 struct psp_firmware_header_v1_0 psp; 386 struct psp_firmware_header_v1_1 psp_v1_1; 387 struct psp_firmware_header_v1_3 psp_v1_3; 388 struct psp_firmware_header_v2_0 psp_v2_0; 389 struct ta_firmware_header_v1_0 ta; 390 struct ta_firmware_header_v2_0 ta_v2_0; 391 struct gfx_firmware_header_v1_0 gfx; 392 struct gfx_firmware_header_v2_0 gfx_v2_0; 393 struct rlc_firmware_header_v1_0 rlc; 394 struct rlc_firmware_header_v2_0 rlc_v2_0; 395 struct rlc_firmware_header_v2_1 rlc_v2_1; 396 struct rlc_firmware_header_v2_2 rlc_v2_2; 397 struct rlc_firmware_header_v2_3 rlc_v2_3; 398 struct rlc_firmware_header_v2_4 rlc_v2_4; 399 struct sdma_firmware_header_v1_0 sdma; 400 struct sdma_firmware_header_v1_1 sdma_v1_1; 401 struct sdma_firmware_header_v2_0 sdma_v2_0; 402 struct gpu_info_firmware_header_v1_0 gpu_info; 403 struct dmcu_firmware_header_v1_0 dmcu; 404 struct dmcub_firmware_header_v1_0 dmcub; 405 struct imu_firmware_header_v1_0 imu; 406 uint8_t raw[0x100]; 407 }; 408 409 #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) 410 411 /* 412 * fw loading support 413 */ 414 enum AMDGPU_UCODE_ID { 415 AMDGPU_UCODE_ID_CAP = 0, 416 AMDGPU_UCODE_ID_SDMA0, 417 AMDGPU_UCODE_ID_SDMA1, 418 AMDGPU_UCODE_ID_SDMA2, 419 AMDGPU_UCODE_ID_SDMA3, 420 AMDGPU_UCODE_ID_SDMA4, 421 AMDGPU_UCODE_ID_SDMA5, 422 AMDGPU_UCODE_ID_SDMA6, 423 AMDGPU_UCODE_ID_SDMA7, 424 AMDGPU_UCODE_ID_SDMA_UCODE_TH0, 425 AMDGPU_UCODE_ID_SDMA_UCODE_TH1, 426 AMDGPU_UCODE_ID_CP_CE, 427 AMDGPU_UCODE_ID_CP_PFP, 428 AMDGPU_UCODE_ID_CP_ME, 429 AMDGPU_UCODE_ID_CP_RS64_PFP, 430 AMDGPU_UCODE_ID_CP_RS64_ME, 431 AMDGPU_UCODE_ID_CP_RS64_MEC, 432 AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, 433 AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, 434 AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, 435 AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, 436 AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, 437 AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, 438 AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, 439 AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, 440 AMDGPU_UCODE_ID_CP_MEC1, 441 AMDGPU_UCODE_ID_CP_MEC1_JT, 442 AMDGPU_UCODE_ID_CP_MEC2, 443 AMDGPU_UCODE_ID_CP_MEC2_JT, 444 AMDGPU_UCODE_ID_CP_MES, 445 AMDGPU_UCODE_ID_CP_MES_DATA, 446 AMDGPU_UCODE_ID_CP_MES1, 447 AMDGPU_UCODE_ID_CP_MES1_DATA, 448 AMDGPU_UCODE_ID_IMU_I, 449 AMDGPU_UCODE_ID_IMU_D, 450 AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS, 451 AMDGPU_UCODE_ID_SE0_TAP_DELAYS, 452 AMDGPU_UCODE_ID_SE1_TAP_DELAYS, 453 AMDGPU_UCODE_ID_SE2_TAP_DELAYS, 454 AMDGPU_UCODE_ID_SE3_TAP_DELAYS, 455 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 456 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 457 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 458 AMDGPU_UCODE_ID_RLC_IRAM, 459 AMDGPU_UCODE_ID_RLC_DRAM, 460 AMDGPU_UCODE_ID_RLC_P, 461 AMDGPU_UCODE_ID_RLC_V, 462 AMDGPU_UCODE_ID_RLC_G, 463 AMDGPU_UCODE_ID_STORAGE, 464 AMDGPU_UCODE_ID_SMC, 465 AMDGPU_UCODE_ID_PPTABLE, 466 AMDGPU_UCODE_ID_UVD, 467 AMDGPU_UCODE_ID_UVD1, 468 AMDGPU_UCODE_ID_VCE, 469 AMDGPU_UCODE_ID_VCN, 470 AMDGPU_UCODE_ID_VCN1, 471 AMDGPU_UCODE_ID_DMCU_ERAM, 472 AMDGPU_UCODE_ID_DMCU_INTV, 473 AMDGPU_UCODE_ID_VCN0_RAM, 474 AMDGPU_UCODE_ID_VCN1_RAM, 475 AMDGPU_UCODE_ID_DMCUB, 476 AMDGPU_UCODE_ID_MAXIMUM, 477 }; 478 479 /* engine firmware status */ 480 enum AMDGPU_UCODE_STATUS { 481 AMDGPU_UCODE_STATUS_INVALID, 482 AMDGPU_UCODE_STATUS_NOT_LOADED, 483 AMDGPU_UCODE_STATUS_LOADED, 484 }; 485 486 enum amdgpu_firmware_load_type { 487 AMDGPU_FW_LOAD_DIRECT = 0, 488 AMDGPU_FW_LOAD_PSP, 489 AMDGPU_FW_LOAD_SMU, 490 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 491 }; 492 493 /* conform to smu_ucode_xfer_cz.h */ 494 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 495 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 496 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 497 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 498 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 499 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 500 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 501 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 502 503 /* amdgpu firmware info */ 504 struct amdgpu_firmware_info { 505 /* ucode ID */ 506 enum AMDGPU_UCODE_ID ucode_id; 507 /* request_firmware */ 508 const struct firmware *fw; 509 /* starting mc address */ 510 uint64_t mc_addr; 511 /* kernel linear address */ 512 void *kaddr; 513 /* ucode_size_bytes */ 514 uint32_t ucode_size; 515 /* starting tmr mc address */ 516 uint32_t tmr_mc_addr_lo; 517 uint32_t tmr_mc_addr_hi; 518 }; 519 520 struct amdgpu_firmware { 521 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 522 enum amdgpu_firmware_load_type load_type; 523 struct amdgpu_bo *fw_buf; 524 unsigned int fw_size; 525 unsigned int max_ucodes; 526 /* firmwares are loaded by psp instead of smu from vega10 */ 527 const struct amdgpu_psp_funcs *funcs; 528 struct amdgpu_bo *rbuf; 529 struct mutex mutex; 530 531 /* gpu info firmware data pointer */ 532 const struct firmware *gpu_info_fw; 533 534 void *fw_buf_ptr; 535 uint64_t fw_buf_mc; 536 }; 537 538 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 539 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 540 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 541 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 542 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 543 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 544 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 545 int amdgpu_ucode_validate(const struct firmware *fw); 546 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 547 uint16_t hdr_major, uint16_t hdr_minor); 548 549 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 550 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 551 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 552 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 553 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 554 555 enum amdgpu_firmware_load_type 556 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 557 558 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); 559 560 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); 561 562 #endif 563