1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 struct common_firmware_header { 27 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 28 uint32_t header_size_bytes; /* size of just the header in bytes */ 29 uint16_t header_version_major; /* header version */ 30 uint16_t header_version_minor; /* header version */ 31 uint16_t ip_version_major; /* IP version */ 32 uint16_t ip_version_minor; /* IP version */ 33 uint32_t ucode_version; 34 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 35 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 36 uint32_t crc32; /* crc32 checksum of the payload */ 37 }; 38 39 /* version_major=1, version_minor=0 */ 40 struct mc_firmware_header_v1_0 { 41 struct common_firmware_header header; 42 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 43 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 44 }; 45 46 /* version_major=1, version_minor=0 */ 47 struct smc_firmware_header_v1_0 { 48 struct common_firmware_header header; 49 uint32_t ucode_start_addr; 50 }; 51 52 /* version_major=1, version_minor=0 */ 53 struct psp_firmware_header_v1_0 { 54 struct common_firmware_header header; 55 uint32_t ucode_feature_version; 56 uint32_t sos_offset_bytes; 57 uint32_t sos_size_bytes; 58 }; 59 60 /* version_major=1, version_minor=0 */ 61 struct gfx_firmware_header_v1_0 { 62 struct common_firmware_header header; 63 uint32_t ucode_feature_version; 64 uint32_t jt_offset; /* jt location */ 65 uint32_t jt_size; /* size of jt */ 66 }; 67 68 /* version_major=1, version_minor=0 */ 69 struct rlc_firmware_header_v1_0 { 70 struct common_firmware_header header; 71 uint32_t ucode_feature_version; 72 uint32_t save_and_restore_offset; 73 uint32_t clear_state_descriptor_offset; 74 uint32_t avail_scratch_ram_locations; 75 uint32_t master_pkt_description_offset; 76 }; 77 78 /* version_major=2, version_minor=0 */ 79 struct rlc_firmware_header_v2_0 { 80 struct common_firmware_header header; 81 uint32_t ucode_feature_version; 82 uint32_t jt_offset; /* jt location */ 83 uint32_t jt_size; /* size of jt */ 84 uint32_t save_and_restore_offset; 85 uint32_t clear_state_descriptor_offset; 86 uint32_t avail_scratch_ram_locations; 87 uint32_t reg_restore_list_size; 88 uint32_t reg_list_format_start; 89 uint32_t reg_list_format_separate_start; 90 uint32_t starting_offsets_start; 91 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 92 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 93 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 94 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 95 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 96 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 97 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 98 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 99 }; 100 101 /* version_major=2, version_minor=1 */ 102 struct rlc_firmware_header_v2_1 { 103 struct rlc_firmware_header_v2_0 v2_0; 104 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 105 uint32_t save_restore_list_cntl_ucode_ver; 106 uint32_t save_restore_list_cntl_feature_ver; 107 uint32_t save_restore_list_cntl_size_bytes; 108 uint32_t save_restore_list_cntl_offset_bytes; 109 uint32_t save_restore_list_gpm_ucode_ver; 110 uint32_t save_restore_list_gpm_feature_ver; 111 uint32_t save_restore_list_gpm_size_bytes; 112 uint32_t save_restore_list_gpm_offset_bytes; 113 uint32_t save_restore_list_srm_ucode_ver; 114 uint32_t save_restore_list_srm_feature_ver; 115 uint32_t save_restore_list_srm_size_bytes; 116 uint32_t save_restore_list_srm_offset_bytes; 117 }; 118 119 /* version_major=1, version_minor=0 */ 120 struct sdma_firmware_header_v1_0 { 121 struct common_firmware_header header; 122 uint32_t ucode_feature_version; 123 uint32_t ucode_change_version; 124 uint32_t jt_offset; /* jt location */ 125 uint32_t jt_size; /* size of jt */ 126 }; 127 128 /* version_major=1, version_minor=1 */ 129 struct sdma_firmware_header_v1_1 { 130 struct sdma_firmware_header_v1_0 v1_0; 131 uint32_t digest_size; 132 }; 133 134 /* gpu info payload */ 135 struct gpu_info_firmware_v1_0 { 136 uint32_t gc_num_se; 137 uint32_t gc_num_cu_per_sh; 138 uint32_t gc_num_sh_per_se; 139 uint32_t gc_num_rb_per_se; 140 uint32_t gc_num_tccs; 141 uint32_t gc_num_gprs; 142 uint32_t gc_num_max_gs_thds; 143 uint32_t gc_gs_table_depth; 144 uint32_t gc_gsprim_buff_depth; 145 uint32_t gc_parameter_cache_depth; 146 uint32_t gc_double_offchip_lds_buffer; 147 uint32_t gc_wave_size; 148 uint32_t gc_max_waves_per_simd; 149 uint32_t gc_max_scratch_slots_per_cu; 150 uint32_t gc_lds_size; 151 }; 152 153 /* version_major=1, version_minor=0 */ 154 struct gpu_info_firmware_header_v1_0 { 155 struct common_firmware_header header; 156 uint16_t version_major; /* version */ 157 uint16_t version_minor; /* version */ 158 }; 159 160 /* version_major=1, version_minor=0 */ 161 struct dmcu_firmware_header_v1_0 { 162 struct common_firmware_header header; 163 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 164 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 165 }; 166 167 /* header is fixed size */ 168 union amdgpu_firmware_header { 169 struct common_firmware_header common; 170 struct mc_firmware_header_v1_0 mc; 171 struct smc_firmware_header_v1_0 smc; 172 struct psp_firmware_header_v1_0 psp; 173 struct gfx_firmware_header_v1_0 gfx; 174 struct rlc_firmware_header_v1_0 rlc; 175 struct rlc_firmware_header_v2_0 rlc_v2_0; 176 struct rlc_firmware_header_v2_1 rlc_v2_1; 177 struct sdma_firmware_header_v1_0 sdma; 178 struct sdma_firmware_header_v1_1 sdma_v1_1; 179 struct gpu_info_firmware_header_v1_0 gpu_info; 180 struct dmcu_firmware_header_v1_0 dmcu; 181 uint8_t raw[0x100]; 182 }; 183 184 /* 185 * fw loading support 186 */ 187 enum AMDGPU_UCODE_ID { 188 AMDGPU_UCODE_ID_SDMA0 = 0, 189 AMDGPU_UCODE_ID_SDMA1, 190 AMDGPU_UCODE_ID_CP_CE, 191 AMDGPU_UCODE_ID_CP_PFP, 192 AMDGPU_UCODE_ID_CP_ME, 193 AMDGPU_UCODE_ID_CP_MEC1, 194 AMDGPU_UCODE_ID_CP_MEC1_JT, 195 AMDGPU_UCODE_ID_CP_MEC2, 196 AMDGPU_UCODE_ID_CP_MEC2_JT, 197 AMDGPU_UCODE_ID_RLC_G, 198 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 199 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 200 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 201 AMDGPU_UCODE_ID_STORAGE, 202 AMDGPU_UCODE_ID_SMC, 203 AMDGPU_UCODE_ID_UVD, 204 AMDGPU_UCODE_ID_UVD1, 205 AMDGPU_UCODE_ID_VCE, 206 AMDGPU_UCODE_ID_VCN, 207 AMDGPU_UCODE_ID_DMCU_ERAM, 208 AMDGPU_UCODE_ID_DMCU_INTV, 209 AMDGPU_UCODE_ID_MAXIMUM, 210 }; 211 212 /* engine firmware status */ 213 enum AMDGPU_UCODE_STATUS { 214 AMDGPU_UCODE_STATUS_INVALID, 215 AMDGPU_UCODE_STATUS_NOT_LOADED, 216 AMDGPU_UCODE_STATUS_LOADED, 217 }; 218 219 enum amdgpu_firmware_load_type { 220 AMDGPU_FW_LOAD_DIRECT = 0, 221 AMDGPU_FW_LOAD_SMU, 222 AMDGPU_FW_LOAD_PSP, 223 }; 224 225 /* conform to smu_ucode_xfer_cz.h */ 226 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 227 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 228 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 229 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 230 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 231 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 232 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 233 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 234 235 /* amdgpu firmware info */ 236 struct amdgpu_firmware_info { 237 /* ucode ID */ 238 enum AMDGPU_UCODE_ID ucode_id; 239 /* request_firmware */ 240 const struct firmware *fw; 241 /* starting mc address */ 242 uint64_t mc_addr; 243 /* kernel linear address */ 244 void *kaddr; 245 /* ucode_size_bytes */ 246 uint32_t ucode_size; 247 /* starting tmr mc address */ 248 uint32_t tmr_mc_addr_lo; 249 uint32_t tmr_mc_addr_hi; 250 }; 251 252 struct amdgpu_firmware { 253 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 254 enum amdgpu_firmware_load_type load_type; 255 struct amdgpu_bo *fw_buf; 256 unsigned int fw_size; 257 unsigned int max_ucodes; 258 /* firmwares are loaded by psp instead of smu from vega10 */ 259 const struct amdgpu_psp_funcs *funcs; 260 struct amdgpu_bo *rbuf; 261 struct mutex mutex; 262 263 /* gpu info firmware data pointer */ 264 const struct firmware *gpu_info_fw; 265 266 void *fw_buf_ptr; 267 uint64_t fw_buf_mc; 268 }; 269 270 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 271 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 272 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 273 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 274 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 275 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 276 int amdgpu_ucode_validate(const struct firmware *fw); 277 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 278 uint16_t hdr_major, uint16_t hdr_minor); 279 280 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 281 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 282 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 283 284 enum amdgpu_firmware_load_type 285 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 286 287 #endif 288