1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 32 { 33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 41 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 42 le32_to_cpu(hdr->ucode_array_offset_bytes)); 43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 44 } 45 46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 47 { 48 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 50 51 DRM_DEBUG("MC\n"); 52 amdgpu_ucode_print_common_hdr(hdr); 53 54 if (version_major == 1) { 55 const struct mc_firmware_header_v1_0 *mc_hdr = 56 container_of(hdr, struct mc_firmware_header_v1_0, header); 57 58 DRM_DEBUG("io_debug_size_bytes: %u\n", 59 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 62 } else { 63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 64 } 65 } 66 67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 68 { 69 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 71 const struct smc_firmware_header_v1_0 *v1_0_hdr; 72 const struct smc_firmware_header_v2_0 *v2_0_hdr; 73 const struct smc_firmware_header_v2_1 *v2_1_hdr; 74 75 DRM_DEBUG("SMC\n"); 76 amdgpu_ucode_print_common_hdr(hdr); 77 78 if (version_major == 1) { 79 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); 80 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); 81 } else if (version_major == 2) { 82 switch (version_minor) { 83 case 0: 84 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); 85 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); 86 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); 87 break; 88 case 1: 89 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); 90 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); 91 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); 92 break; 93 default: 94 break; 95 } 96 97 } else { 98 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 99 } 100 } 101 102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 103 { 104 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 105 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 106 107 DRM_DEBUG("GFX\n"); 108 amdgpu_ucode_print_common_hdr(hdr); 109 110 if (version_major == 1) { 111 const struct gfx_firmware_header_v1_0 *gfx_hdr = 112 container_of(hdr, struct gfx_firmware_header_v1_0, header); 113 114 DRM_DEBUG("ucode_feature_version: %u\n", 115 le32_to_cpu(gfx_hdr->ucode_feature_version)); 116 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 117 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 118 } else { 119 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 120 } 121 } 122 123 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 124 { 125 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 126 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 127 128 DRM_DEBUG("RLC\n"); 129 amdgpu_ucode_print_common_hdr(hdr); 130 131 if (version_major == 1) { 132 const struct rlc_firmware_header_v1_0 *rlc_hdr = 133 container_of(hdr, struct rlc_firmware_header_v1_0, header); 134 135 DRM_DEBUG("ucode_feature_version: %u\n", 136 le32_to_cpu(rlc_hdr->ucode_feature_version)); 137 DRM_DEBUG("save_and_restore_offset: %u\n", 138 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 139 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 140 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 141 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 142 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 143 DRM_DEBUG("master_pkt_description_offset: %u\n", 144 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 145 } else if (version_major == 2) { 146 const struct rlc_firmware_header_v2_0 *rlc_hdr = 147 container_of(hdr, struct rlc_firmware_header_v2_0, header); 148 149 DRM_DEBUG("ucode_feature_version: %u\n", 150 le32_to_cpu(rlc_hdr->ucode_feature_version)); 151 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 152 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 153 DRM_DEBUG("save_and_restore_offset: %u\n", 154 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 155 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 156 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 157 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 158 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 159 DRM_DEBUG("reg_restore_list_size: %u\n", 160 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 161 DRM_DEBUG("reg_list_format_start: %u\n", 162 le32_to_cpu(rlc_hdr->reg_list_format_start)); 163 DRM_DEBUG("reg_list_format_separate_start: %u\n", 164 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 165 DRM_DEBUG("starting_offsets_start: %u\n", 166 le32_to_cpu(rlc_hdr->starting_offsets_start)); 167 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 168 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 169 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 170 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 171 DRM_DEBUG("reg_list_size_bytes: %u\n", 172 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 173 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 174 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 175 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 176 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 177 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 178 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 179 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 180 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 181 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 182 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 183 if (version_minor == 1) { 184 const struct rlc_firmware_header_v2_1 *v2_1 = 185 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 186 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 187 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); 188 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 189 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); 190 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 191 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); 192 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 193 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); 194 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 195 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); 196 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 197 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); 198 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 199 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); 200 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 201 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); 202 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 203 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); 204 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 205 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); 206 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 207 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); 208 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 209 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes)); 210 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 211 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes)); 212 } 213 } else { 214 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 215 } 216 } 217 218 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 219 { 220 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 221 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 222 223 DRM_DEBUG("SDMA\n"); 224 amdgpu_ucode_print_common_hdr(hdr); 225 226 if (version_major == 1) { 227 const struct sdma_firmware_header_v1_0 *sdma_hdr = 228 container_of(hdr, struct sdma_firmware_header_v1_0, header); 229 230 DRM_DEBUG("ucode_feature_version: %u\n", 231 le32_to_cpu(sdma_hdr->ucode_feature_version)); 232 DRM_DEBUG("ucode_change_version: %u\n", 233 le32_to_cpu(sdma_hdr->ucode_change_version)); 234 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 235 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 236 if (version_minor >= 1) { 237 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 238 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 239 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 240 } 241 } else { 242 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 243 version_major, version_minor); 244 } 245 } 246 247 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 248 { 249 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 250 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 251 252 DRM_DEBUG("PSP\n"); 253 amdgpu_ucode_print_common_hdr(hdr); 254 255 if (version_major == 1) { 256 const struct psp_firmware_header_v1_0 *psp_hdr = 257 container_of(hdr, struct psp_firmware_header_v1_0, header); 258 259 DRM_DEBUG("ucode_feature_version: %u\n", 260 le32_to_cpu(psp_hdr->sos.fw_version)); 261 DRM_DEBUG("sos_offset_bytes: %u\n", 262 le32_to_cpu(psp_hdr->sos.offset_bytes)); 263 DRM_DEBUG("sos_size_bytes: %u\n", 264 le32_to_cpu(psp_hdr->sos.size_bytes)); 265 if (version_minor == 1) { 266 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 267 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 268 DRM_DEBUG("toc_header_version: %u\n", 269 le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); 270 DRM_DEBUG("toc_offset_bytes: %u\n", 271 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); 272 DRM_DEBUG("toc_size_bytes: %u\n", 273 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); 274 DRM_DEBUG("kdb_header_version: %u\n", 275 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); 276 DRM_DEBUG("kdb_offset_bytes: %u\n", 277 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); 278 DRM_DEBUG("kdb_size_bytes: %u\n", 279 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); 280 } 281 if (version_minor == 2) { 282 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 283 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 284 DRM_DEBUG("kdb_header_version: %u\n", 285 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); 286 DRM_DEBUG("kdb_offset_bytes: %u\n", 287 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); 288 DRM_DEBUG("kdb_size_bytes: %u\n", 289 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); 290 } 291 if (version_minor == 3) { 292 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 293 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 294 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = 295 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); 296 DRM_DEBUG("toc_header_version: %u\n", 297 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); 298 DRM_DEBUG("toc_offset_bytes: %u\n", 299 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); 300 DRM_DEBUG("toc_size_bytes: %u\n", 301 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); 302 DRM_DEBUG("kdb_header_version: %u\n", 303 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); 304 DRM_DEBUG("kdb_offset_bytes: %u\n", 305 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); 306 DRM_DEBUG("kdb_size_bytes: %u\n", 307 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); 308 DRM_DEBUG("spl_header_version: %u\n", 309 le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); 310 DRM_DEBUG("spl_offset_bytes: %u\n", 311 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); 312 DRM_DEBUG("spl_size_bytes: %u\n", 313 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); 314 } 315 } else { 316 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 317 version_major, version_minor); 318 } 319 } 320 321 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 322 { 323 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 324 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 325 326 DRM_DEBUG("GPU_INFO\n"); 327 amdgpu_ucode_print_common_hdr(hdr); 328 329 if (version_major == 1) { 330 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 331 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 332 333 DRM_DEBUG("version_major: %u\n", 334 le16_to_cpu(gpu_info_hdr->version_major)); 335 DRM_DEBUG("version_minor: %u\n", 336 le16_to_cpu(gpu_info_hdr->version_minor)); 337 } else { 338 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 339 } 340 } 341 342 int amdgpu_ucode_validate(const struct firmware *fw) 343 { 344 const struct common_firmware_header *hdr = 345 (const struct common_firmware_header *)fw->data; 346 347 if (fw->size == le32_to_cpu(hdr->size_bytes)) 348 return 0; 349 350 return -EINVAL; 351 } 352 353 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 354 uint16_t hdr_major, uint16_t hdr_minor) 355 { 356 if ((hdr->common.header_version_major == hdr_major) && 357 (hdr->common.header_version_minor == hdr_minor)) 358 return false; 359 return true; 360 } 361 362 enum amdgpu_firmware_load_type 363 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 364 { 365 switch (adev->asic_type) { 366 #ifdef CONFIG_DRM_AMDGPU_SI 367 case CHIP_TAHITI: 368 case CHIP_PITCAIRN: 369 case CHIP_VERDE: 370 case CHIP_OLAND: 371 case CHIP_HAINAN: 372 return AMDGPU_FW_LOAD_DIRECT; 373 #endif 374 #ifdef CONFIG_DRM_AMDGPU_CIK 375 case CHIP_BONAIRE: 376 case CHIP_KAVERI: 377 case CHIP_KABINI: 378 case CHIP_HAWAII: 379 case CHIP_MULLINS: 380 return AMDGPU_FW_LOAD_DIRECT; 381 #endif 382 case CHIP_TOPAZ: 383 case CHIP_TONGA: 384 case CHIP_FIJI: 385 case CHIP_CARRIZO: 386 case CHIP_STONEY: 387 case CHIP_POLARIS10: 388 case CHIP_POLARIS11: 389 case CHIP_POLARIS12: 390 case CHIP_VEGAM: 391 return AMDGPU_FW_LOAD_SMU; 392 case CHIP_VEGA10: 393 case CHIP_RAVEN: 394 case CHIP_VEGA12: 395 case CHIP_VEGA20: 396 case CHIP_ARCTURUS: 397 case CHIP_RENOIR: 398 case CHIP_NAVI10: 399 case CHIP_NAVI14: 400 case CHIP_NAVI12: 401 case CHIP_SIENNA_CICHLID: 402 case CHIP_NAVY_FLOUNDER: 403 case CHIP_VANGOGH: 404 case CHIP_DIMGREY_CAVEFISH: 405 case CHIP_ALDEBARAN: 406 case CHIP_BEIGE_GOBY: 407 case CHIP_YELLOW_CARP: 408 if (!load_type) 409 return AMDGPU_FW_LOAD_DIRECT; 410 else 411 return AMDGPU_FW_LOAD_PSP; 412 default: 413 DRM_ERROR("Unknown firmware load type\n"); 414 } 415 416 return AMDGPU_FW_LOAD_DIRECT; 417 } 418 419 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) 420 { 421 switch (ucode_id) { 422 case AMDGPU_UCODE_ID_SDMA0: 423 return "SDMA0"; 424 case AMDGPU_UCODE_ID_SDMA1: 425 return "SDMA1"; 426 case AMDGPU_UCODE_ID_SDMA2: 427 return "SDMA2"; 428 case AMDGPU_UCODE_ID_SDMA3: 429 return "SDMA3"; 430 case AMDGPU_UCODE_ID_SDMA4: 431 return "SDMA4"; 432 case AMDGPU_UCODE_ID_SDMA5: 433 return "SDMA5"; 434 case AMDGPU_UCODE_ID_SDMA6: 435 return "SDMA6"; 436 case AMDGPU_UCODE_ID_SDMA7: 437 return "SDMA7"; 438 case AMDGPU_UCODE_ID_CP_CE: 439 return "CP_CE"; 440 case AMDGPU_UCODE_ID_CP_PFP: 441 return "CP_PFP"; 442 case AMDGPU_UCODE_ID_CP_ME: 443 return "CP_ME"; 444 case AMDGPU_UCODE_ID_CP_MEC1: 445 return "CP_MEC1"; 446 case AMDGPU_UCODE_ID_CP_MEC1_JT: 447 return "CP_MEC1_JT"; 448 case AMDGPU_UCODE_ID_CP_MEC2: 449 return "CP_MEC2"; 450 case AMDGPU_UCODE_ID_CP_MEC2_JT: 451 return "CP_MEC2_JT"; 452 case AMDGPU_UCODE_ID_CP_MES: 453 return "CP_MES"; 454 case AMDGPU_UCODE_ID_CP_MES_DATA: 455 return "CP_MES_DATA"; 456 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 457 return "RLC_RESTORE_LIST_CNTL"; 458 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 459 return "RLC_RESTORE_LIST_GPM_MEM"; 460 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 461 return "RLC_RESTORE_LIST_SRM_MEM"; 462 case AMDGPU_UCODE_ID_RLC_IRAM: 463 return "RLC_IRAM"; 464 case AMDGPU_UCODE_ID_RLC_DRAM: 465 return "RLC_DRAM"; 466 case AMDGPU_UCODE_ID_RLC_G: 467 return "RLC_G"; 468 case AMDGPU_UCODE_ID_STORAGE: 469 return "STORAGE"; 470 case AMDGPU_UCODE_ID_SMC: 471 return "SMC"; 472 case AMDGPU_UCODE_ID_UVD: 473 return "UVD"; 474 case AMDGPU_UCODE_ID_UVD1: 475 return "UVD1"; 476 case AMDGPU_UCODE_ID_VCE: 477 return "VCE"; 478 case AMDGPU_UCODE_ID_VCN: 479 return "VCN"; 480 case AMDGPU_UCODE_ID_VCN1: 481 return "VCN1"; 482 case AMDGPU_UCODE_ID_DMCU_ERAM: 483 return "DMCU_ERAM"; 484 case AMDGPU_UCODE_ID_DMCU_INTV: 485 return "DMCU_INTV"; 486 case AMDGPU_UCODE_ID_VCN0_RAM: 487 return "VCN0_RAM"; 488 case AMDGPU_UCODE_ID_VCN1_RAM: 489 return "VCN1_RAM"; 490 case AMDGPU_UCODE_ID_DMCUB: 491 return "DMCUB"; 492 default: 493 return "UNKNOWN UCODE"; 494 } 495 } 496 497 #define FW_VERSION_ATTR(name, mode, field) \ 498 static ssize_t show_##name(struct device *dev, \ 499 struct device_attribute *attr, \ 500 char *buf) \ 501 { \ 502 struct drm_device *ddev = dev_get_drvdata(dev); \ 503 struct amdgpu_device *adev = drm_to_adev(ddev); \ 504 \ 505 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \ 506 } \ 507 static DEVICE_ATTR(name, mode, show_##name, NULL) 508 509 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 510 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 511 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 512 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 513 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 514 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 515 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 516 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 517 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 518 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 519 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 520 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 521 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version); 522 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version); 523 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_ras_ucode_version); 524 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_xgmi_ucode_version); 525 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 526 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 527 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 528 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 529 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 530 531 static struct attribute *fw_attrs[] = { 532 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 533 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 534 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 535 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 536 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 537 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 538 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 539 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 540 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 541 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 542 &dev_attr_dmcu_fw_version.attr, NULL 543 }; 544 545 static const struct attribute_group fw_attr_group = { 546 .name = "fw_version", 547 .attrs = fw_attrs 548 }; 549 550 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 551 { 552 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 553 } 554 555 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 556 { 557 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 558 } 559 560 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 561 struct amdgpu_firmware_info *ucode, 562 uint64_t mc_addr, void *kptr) 563 { 564 const struct common_firmware_header *header = NULL; 565 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 566 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 567 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 568 const struct mes_firmware_header_v1_0 *mes_hdr = NULL; 569 570 if (NULL == ucode->fw) 571 return 0; 572 573 ucode->mc_addr = mc_addr; 574 ucode->kaddr = kptr; 575 576 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 577 return 0; 578 579 header = (const struct common_firmware_header *)ucode->fw->data; 580 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 581 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 582 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 583 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; 584 585 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || 586 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && 587 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 && 588 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT && 589 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT && 590 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES && 591 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA && 592 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL && 593 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && 594 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM && 595 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM && 596 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM && 597 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM && 598 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV && 599 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) { 600 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 601 602 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 603 le32_to_cpu(header->ucode_array_offset_bytes)), 604 ucode->ucode_size); 605 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 || 606 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) { 607 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 608 le32_to_cpu(cp_hdr->jt_size) * 4; 609 610 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 611 le32_to_cpu(header->ucode_array_offset_bytes)), 612 ucode->ucode_size); 613 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 614 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) { 615 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 616 617 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 618 le32_to_cpu(header->ucode_array_offset_bytes) + 619 le32_to_cpu(cp_hdr->jt_offset) * 4), 620 ucode->ucode_size); 621 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) { 622 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 623 le32_to_cpu(dmcu_hdr->intv_size_bytes); 624 625 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 626 le32_to_cpu(header->ucode_array_offset_bytes)), 627 ucode->ucode_size); 628 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) { 629 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 630 631 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 632 le32_to_cpu(header->ucode_array_offset_bytes) + 633 le32_to_cpu(dmcu_hdr->intv_offset_bytes)), 634 ucode->ucode_size); 635 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) { 636 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 637 memcpy(ucode->kaddr, 638 (void *)((uint8_t *)ucode->fw->data + 639 le32_to_cpu(header->ucode_array_offset_bytes)), 640 ucode->ucode_size); 641 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { 642 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 643 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, 644 ucode->ucode_size); 645 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) { 646 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 647 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm, 648 ucode->ucode_size); 649 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { 650 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 651 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm, 652 ucode->ucode_size); 653 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) { 654 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; 655 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode, 656 ucode->ucode_size); 657 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) { 658 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; 659 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode, 660 ucode->ucode_size); 661 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) { 662 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 663 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data + 664 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)), 665 ucode->ucode_size); 666 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) { 667 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 668 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data + 669 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)), 670 ucode->ucode_size); 671 } 672 673 return 0; 674 } 675 676 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 677 uint64_t mc_addr, void *kptr) 678 { 679 const struct gfx_firmware_header_v1_0 *header = NULL; 680 const struct common_firmware_header *comm_hdr = NULL; 681 uint8_t *src_addr = NULL; 682 uint8_t *dst_addr = NULL; 683 684 if (NULL == ucode->fw) 685 return 0; 686 687 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 688 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 689 dst_addr = ucode->kaddr + 690 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 691 PAGE_SIZE); 692 src_addr = (uint8_t *)ucode->fw->data + 693 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 694 (le32_to_cpu(header->jt_offset) * 4); 695 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 696 697 return 0; 698 } 699 700 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 701 { 702 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) { 703 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 704 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 705 &adev->firmware.fw_buf, 706 &adev->firmware.fw_buf_mc, 707 &adev->firmware.fw_buf_ptr); 708 if (!adev->firmware.fw_buf) { 709 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 710 return -ENOMEM; 711 } else if (amdgpu_sriov_vf(adev)) { 712 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 713 } 714 } 715 return 0; 716 } 717 718 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 719 { 720 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) 721 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 722 &adev->firmware.fw_buf_mc, 723 &adev->firmware.fw_buf_ptr); 724 } 725 726 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 727 { 728 uint64_t fw_offset = 0; 729 int i; 730 struct amdgpu_firmware_info *ucode = NULL; 731 732 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 733 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend)) 734 return 0; 735 /* 736 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 737 * ucode info here 738 */ 739 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 740 if (amdgpu_sriov_vf(adev)) 741 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 742 else 743 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 744 } else { 745 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 746 } 747 748 for (i = 0; i < adev->firmware.max_ucodes; i++) { 749 ucode = &adev->firmware.ucode[i]; 750 if (ucode->fw) { 751 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 752 adev->firmware.fw_buf_ptr + fw_offset); 753 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 754 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 755 const struct gfx_firmware_header_v1_0 *cp_hdr; 756 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 757 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 758 adev->firmware.fw_buf_ptr + fw_offset); 759 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 760 } 761 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 762 } 763 } 764 return 0; 765 } 766