1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 32 { 33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 41 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 42 le32_to_cpu(hdr->ucode_array_offset_bytes)); 43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 44 } 45 46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 47 { 48 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 50 51 DRM_DEBUG("MC\n"); 52 amdgpu_ucode_print_common_hdr(hdr); 53 54 if (version_major == 1) { 55 const struct mc_firmware_header_v1_0 *mc_hdr = 56 container_of(hdr, struct mc_firmware_header_v1_0, header); 57 58 DRM_DEBUG("io_debug_size_bytes: %u\n", 59 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 62 } else { 63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 64 } 65 } 66 67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 68 { 69 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 71 72 DRM_DEBUG("SMC\n"); 73 amdgpu_ucode_print_common_hdr(hdr); 74 75 if (version_major == 1) { 76 const struct smc_firmware_header_v1_0 *smc_hdr = 77 container_of(hdr, struct smc_firmware_header_v1_0, header); 78 79 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); 80 } else { 81 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 82 } 83 } 84 85 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 86 { 87 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 88 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 89 90 DRM_DEBUG("GFX\n"); 91 amdgpu_ucode_print_common_hdr(hdr); 92 93 if (version_major == 1) { 94 const struct gfx_firmware_header_v1_0 *gfx_hdr = 95 container_of(hdr, struct gfx_firmware_header_v1_0, header); 96 97 DRM_DEBUG("ucode_feature_version: %u\n", 98 le32_to_cpu(gfx_hdr->ucode_feature_version)); 99 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 100 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 101 } else { 102 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 103 } 104 } 105 106 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 107 { 108 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 109 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 110 111 DRM_DEBUG("RLC\n"); 112 amdgpu_ucode_print_common_hdr(hdr); 113 114 if (version_major == 1) { 115 const struct rlc_firmware_header_v1_0 *rlc_hdr = 116 container_of(hdr, struct rlc_firmware_header_v1_0, header); 117 118 DRM_DEBUG("ucode_feature_version: %u\n", 119 le32_to_cpu(rlc_hdr->ucode_feature_version)); 120 DRM_DEBUG("save_and_restore_offset: %u\n", 121 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 122 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 124 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 126 DRM_DEBUG("master_pkt_description_offset: %u\n", 127 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 128 } else if (version_major == 2) { 129 const struct rlc_firmware_header_v2_0 *rlc_hdr = 130 container_of(hdr, struct rlc_firmware_header_v2_0, header); 131 132 DRM_DEBUG("ucode_feature_version: %u\n", 133 le32_to_cpu(rlc_hdr->ucode_feature_version)); 134 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 135 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 136 DRM_DEBUG("save_and_restore_offset: %u\n", 137 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 138 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 139 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 140 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 141 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 142 DRM_DEBUG("reg_restore_list_size: %u\n", 143 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 144 DRM_DEBUG("reg_list_format_start: %u\n", 145 le32_to_cpu(rlc_hdr->reg_list_format_start)); 146 DRM_DEBUG("reg_list_format_separate_start: %u\n", 147 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 148 DRM_DEBUG("starting_offsets_start: %u\n", 149 le32_to_cpu(rlc_hdr->starting_offsets_start)); 150 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 151 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 152 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 153 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 154 DRM_DEBUG("reg_list_size_bytes: %u\n", 155 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 156 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 157 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 158 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 159 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 160 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 161 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 162 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 163 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 164 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 165 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 166 if (version_minor == 1) { 167 const struct rlc_firmware_header_v2_1 *v2_1 = 168 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 169 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 170 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); 171 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 172 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); 173 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 174 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); 175 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 176 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); 177 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 178 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); 179 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 180 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); 181 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 182 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); 183 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 184 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); 185 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 186 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); 187 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 188 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); 189 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 190 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); 191 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 192 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes)); 193 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 194 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes)); 195 } 196 } else { 197 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 198 } 199 } 200 201 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 202 { 203 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 204 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 205 206 DRM_DEBUG("SDMA\n"); 207 amdgpu_ucode_print_common_hdr(hdr); 208 209 if (version_major == 1) { 210 const struct sdma_firmware_header_v1_0 *sdma_hdr = 211 container_of(hdr, struct sdma_firmware_header_v1_0, header); 212 213 DRM_DEBUG("ucode_feature_version: %u\n", 214 le32_to_cpu(sdma_hdr->ucode_feature_version)); 215 DRM_DEBUG("ucode_change_version: %u\n", 216 le32_to_cpu(sdma_hdr->ucode_change_version)); 217 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 218 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 219 if (version_minor >= 1) { 220 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 221 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 222 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 223 } 224 } else { 225 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 226 version_major, version_minor); 227 } 228 } 229 230 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 231 { 232 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 233 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 234 235 DRM_DEBUG("GPU_INFO\n"); 236 amdgpu_ucode_print_common_hdr(hdr); 237 238 if (version_major == 1) { 239 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 240 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 241 242 DRM_DEBUG("version_major: %u\n", 243 le16_to_cpu(gpu_info_hdr->version_major)); 244 DRM_DEBUG("version_minor: %u\n", 245 le16_to_cpu(gpu_info_hdr->version_minor)); 246 } else { 247 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 248 } 249 } 250 251 int amdgpu_ucode_validate(const struct firmware *fw) 252 { 253 const struct common_firmware_header *hdr = 254 (const struct common_firmware_header *)fw->data; 255 256 if (fw->size == le32_to_cpu(hdr->size_bytes)) 257 return 0; 258 259 return -EINVAL; 260 } 261 262 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 263 uint16_t hdr_major, uint16_t hdr_minor) 264 { 265 if ((hdr->common.header_version_major == hdr_major) && 266 (hdr->common.header_version_minor == hdr_minor)) 267 return false; 268 return true; 269 } 270 271 enum amdgpu_firmware_load_type 272 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 273 { 274 switch (adev->asic_type) { 275 #ifdef CONFIG_DRM_AMDGPU_SI 276 case CHIP_TAHITI: 277 case CHIP_PITCAIRN: 278 case CHIP_VERDE: 279 case CHIP_OLAND: 280 case CHIP_HAINAN: 281 return AMDGPU_FW_LOAD_DIRECT; 282 #endif 283 #ifdef CONFIG_DRM_AMDGPU_CIK 284 case CHIP_BONAIRE: 285 case CHIP_KAVERI: 286 case CHIP_KABINI: 287 case CHIP_HAWAII: 288 case CHIP_MULLINS: 289 return AMDGPU_FW_LOAD_DIRECT; 290 #endif 291 case CHIP_TOPAZ: 292 case CHIP_TONGA: 293 case CHIP_FIJI: 294 case CHIP_CARRIZO: 295 case CHIP_STONEY: 296 case CHIP_POLARIS10: 297 case CHIP_POLARIS11: 298 case CHIP_POLARIS12: 299 case CHIP_VEGAM: 300 return AMDGPU_FW_LOAD_SMU; 301 case CHIP_VEGA10: 302 case CHIP_RAVEN: 303 case CHIP_VEGA12: 304 case CHIP_VEGA20: 305 if (!load_type) 306 return AMDGPU_FW_LOAD_DIRECT; 307 else 308 return AMDGPU_FW_LOAD_PSP; 309 default: 310 DRM_ERROR("Unknown firmware load type\n"); 311 } 312 313 return AMDGPU_FW_LOAD_DIRECT; 314 } 315 316 #define FW_VERSION_ATTR(name, mode, field) \ 317 static ssize_t show_##name(struct device *dev, \ 318 struct device_attribute *attr, \ 319 char *buf) \ 320 { \ 321 struct drm_device *ddev = dev_get_drvdata(dev); \ 322 struct amdgpu_device *adev = ddev->dev_private; \ 323 \ 324 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \ 325 } \ 326 static DEVICE_ATTR(name, mode, show_##name, NULL) 327 328 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 329 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 330 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 331 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 332 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 333 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 334 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 335 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 336 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 337 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 338 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 339 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 340 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version); 341 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version); 342 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_fw_version); 343 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_fw_version); 344 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 345 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 346 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 347 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 348 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 349 350 static struct attribute *fw_attrs[] = { 351 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 352 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 353 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 354 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 355 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 356 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 357 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 358 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 359 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 360 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 361 &dev_attr_dmcu_fw_version.attr, NULL 362 }; 363 364 static const struct attribute_group fw_attr_group = { 365 .name = "fw_version", 366 .attrs = fw_attrs 367 }; 368 369 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 370 { 371 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 372 } 373 374 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 375 { 376 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 377 } 378 379 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 380 struct amdgpu_firmware_info *ucode, 381 uint64_t mc_addr, void *kptr) 382 { 383 const struct common_firmware_header *header = NULL; 384 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 385 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 386 387 if (NULL == ucode->fw) 388 return 0; 389 390 ucode->mc_addr = mc_addr; 391 ucode->kaddr = kptr; 392 393 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 394 return 0; 395 396 header = (const struct common_firmware_header *)ucode->fw->data; 397 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 398 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 399 400 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || 401 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && 402 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 && 403 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT && 404 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT && 405 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL && 406 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && 407 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM && 408 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM && 409 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) { 410 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 411 412 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 413 le32_to_cpu(header->ucode_array_offset_bytes)), 414 ucode->ucode_size); 415 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 || 416 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) { 417 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 418 le32_to_cpu(cp_hdr->jt_size) * 4; 419 420 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 421 le32_to_cpu(header->ucode_array_offset_bytes)), 422 ucode->ucode_size); 423 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 424 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) { 425 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 426 427 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 428 le32_to_cpu(header->ucode_array_offset_bytes) + 429 le32_to_cpu(cp_hdr->jt_offset) * 4), 430 ucode->ucode_size); 431 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) { 432 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 433 le32_to_cpu(dmcu_hdr->intv_size_bytes); 434 435 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 436 le32_to_cpu(header->ucode_array_offset_bytes)), 437 ucode->ucode_size); 438 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) { 439 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 440 441 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 442 le32_to_cpu(header->ucode_array_offset_bytes) + 443 le32_to_cpu(dmcu_hdr->intv_offset_bytes)), 444 ucode->ucode_size); 445 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { 446 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 447 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, 448 ucode->ucode_size); 449 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) { 450 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 451 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm, 452 ucode->ucode_size); 453 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { 454 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 455 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm, 456 ucode->ucode_size); 457 } 458 459 return 0; 460 } 461 462 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 463 uint64_t mc_addr, void *kptr) 464 { 465 const struct gfx_firmware_header_v1_0 *header = NULL; 466 const struct common_firmware_header *comm_hdr = NULL; 467 uint8_t* src_addr = NULL; 468 uint8_t* dst_addr = NULL; 469 470 if (NULL == ucode->fw) 471 return 0; 472 473 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 474 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 475 dst_addr = ucode->kaddr + 476 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 477 PAGE_SIZE); 478 src_addr = (uint8_t *)ucode->fw->data + 479 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 480 (le32_to_cpu(header->jt_offset) * 4); 481 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 482 483 return 0; 484 } 485 486 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 487 { 488 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) { 489 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 490 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 491 &adev->firmware.fw_buf, 492 &adev->firmware.fw_buf_mc, 493 &adev->firmware.fw_buf_ptr); 494 if (!adev->firmware.fw_buf) { 495 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 496 return -ENOMEM; 497 } else if (amdgpu_sriov_vf(adev)) { 498 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 499 } 500 } 501 return 0; 502 } 503 504 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 505 { 506 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) 507 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 508 &adev->firmware.fw_buf_mc, 509 &adev->firmware.fw_buf_ptr); 510 } 511 512 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 513 { 514 uint64_t fw_offset = 0; 515 int i; 516 struct amdgpu_firmware_info *ucode = NULL; 517 518 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 519 if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend)) 520 return 0; 521 /* 522 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 523 * ucode info here 524 */ 525 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 526 if (amdgpu_sriov_vf(adev)) 527 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 528 else 529 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 530 } else { 531 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 532 } 533 534 for (i = 0; i < adev->firmware.max_ucodes; i++) { 535 ucode = &adev->firmware.ucode[i]; 536 if (ucode->fw) { 537 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 538 adev->firmware.fw_buf_ptr + fw_offset); 539 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 540 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 541 const struct gfx_firmware_header_v1_0 *cp_hdr; 542 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 543 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 544 adev->firmware.fw_buf_ptr + fw_offset); 545 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 546 } 547 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 548 } 549 } 550 return 0; 551 } 552