1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 32 { 33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 41 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 42 le32_to_cpu(hdr->ucode_array_offset_bytes)); 43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 44 } 45 46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 47 { 48 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 50 51 DRM_DEBUG("MC\n"); 52 amdgpu_ucode_print_common_hdr(hdr); 53 54 if (version_major == 1) { 55 const struct mc_firmware_header_v1_0 *mc_hdr = 56 container_of(hdr, struct mc_firmware_header_v1_0, header); 57 58 DRM_DEBUG("io_debug_size_bytes: %u\n", 59 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 62 } else { 63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 64 } 65 } 66 67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 68 { 69 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 71 const struct smc_firmware_header_v1_0 *v1_0_hdr; 72 const struct smc_firmware_header_v2_0 *v2_0_hdr; 73 const struct smc_firmware_header_v2_1 *v2_1_hdr; 74 75 DRM_DEBUG("SMC\n"); 76 amdgpu_ucode_print_common_hdr(hdr); 77 78 if (version_major == 1) { 79 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); 80 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); 81 } else if (version_major == 2) { 82 switch (version_minor) { 83 case 0: 84 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); 85 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); 86 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); 87 break; 88 case 1: 89 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); 90 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); 91 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); 92 break; 93 default: 94 break; 95 } 96 97 } else { 98 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 99 } 100 } 101 102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 103 { 104 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 105 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 106 107 DRM_DEBUG("GFX\n"); 108 amdgpu_ucode_print_common_hdr(hdr); 109 110 if (version_major == 1) { 111 const struct gfx_firmware_header_v1_0 *gfx_hdr = 112 container_of(hdr, struct gfx_firmware_header_v1_0, header); 113 114 DRM_DEBUG("ucode_feature_version: %u\n", 115 le32_to_cpu(gfx_hdr->ucode_feature_version)); 116 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 117 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 118 } else if (version_major == 2) { 119 const struct gfx_firmware_header_v2_0 *gfx_hdr = 120 container_of(hdr, struct gfx_firmware_header_v2_0, header); 121 122 DRM_DEBUG("ucode_feature_version: %u\n", 123 le32_to_cpu(gfx_hdr->ucode_feature_version)); 124 } else { 125 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 126 } 127 } 128 129 void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr) 130 { 131 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 132 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 133 134 DRM_DEBUG("IMU\n"); 135 amdgpu_ucode_print_common_hdr(hdr); 136 137 if (version_major != 1) { 138 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 139 } 140 } 141 142 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 143 { 144 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 145 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 146 147 DRM_DEBUG("RLC\n"); 148 amdgpu_ucode_print_common_hdr(hdr); 149 150 if (version_major == 1) { 151 const struct rlc_firmware_header_v1_0 *rlc_hdr = 152 container_of(hdr, struct rlc_firmware_header_v1_0, header); 153 154 DRM_DEBUG("ucode_feature_version: %u\n", 155 le32_to_cpu(rlc_hdr->ucode_feature_version)); 156 DRM_DEBUG("save_and_restore_offset: %u\n", 157 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 158 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 159 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 160 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 161 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 162 DRM_DEBUG("master_pkt_description_offset: %u\n", 163 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 164 } else if (version_major == 2) { 165 const struct rlc_firmware_header_v2_0 *rlc_hdr = 166 container_of(hdr, struct rlc_firmware_header_v2_0, header); 167 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 = 168 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 169 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 = 170 container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1); 171 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 = 172 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2); 173 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 = 174 container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3); 175 176 switch (version_minor) { 177 case 0: 178 /* rlc_hdr v2_0 */ 179 DRM_DEBUG("ucode_feature_version: %u\n", 180 le32_to_cpu(rlc_hdr->ucode_feature_version)); 181 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 182 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 183 DRM_DEBUG("save_and_restore_offset: %u\n", 184 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 185 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 186 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 187 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 188 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 189 DRM_DEBUG("reg_restore_list_size: %u\n", 190 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 191 DRM_DEBUG("reg_list_format_start: %u\n", 192 le32_to_cpu(rlc_hdr->reg_list_format_start)); 193 DRM_DEBUG("reg_list_format_separate_start: %u\n", 194 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 195 DRM_DEBUG("starting_offsets_start: %u\n", 196 le32_to_cpu(rlc_hdr->starting_offsets_start)); 197 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 198 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 199 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 200 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 201 DRM_DEBUG("reg_list_size_bytes: %u\n", 202 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 203 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 204 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 205 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 206 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 207 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 208 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 209 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 210 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 211 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 212 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 213 break; 214 case 1: 215 /* rlc_hdr v2_1 */ 216 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 217 le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length)); 218 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 219 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver)); 220 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 221 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver)); 222 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 223 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes)); 224 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 225 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes)); 226 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 227 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver)); 228 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 229 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver)); 230 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 231 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes)); 232 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 233 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes)); 234 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 235 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver)); 236 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 237 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver)); 238 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 239 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes)); 240 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 241 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes)); 242 break; 243 case 2: 244 /* rlc_hdr v2_2 */ 245 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", 246 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes)); 247 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", 248 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes)); 249 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", 250 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes)); 251 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", 252 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes)); 253 break; 254 case 3: 255 /* rlc_hdr v2_3 */ 256 DRM_DEBUG("rlcp_ucode_version: %u\n", 257 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version)); 258 DRM_DEBUG("rlcp_ucode_feature_version: %u\n", 259 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version)); 260 DRM_DEBUG("rlcp_ucode_size_bytes: %u\n", 261 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes)); 262 DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n", 263 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes)); 264 DRM_DEBUG("rlcv_ucode_version: %u\n", 265 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version)); 266 DRM_DEBUG("rlcv_ucode_feature_version: %u\n", 267 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version)); 268 DRM_DEBUG("rlcv_ucode_size_bytes: %u\n", 269 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes)); 270 DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n", 271 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes)); 272 break; 273 case 4: 274 /* rlc_hdr v2_4 */ 275 DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n", 276 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes)); 277 DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n", 278 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes)); 279 DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n", 280 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes)); 281 DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n", 282 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes)); 283 DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n", 284 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes)); 285 DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n", 286 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes)); 287 DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n", 288 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes)); 289 DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n", 290 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes)); 291 DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n", 292 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes)); 293 DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n", 294 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes)); 295 break; 296 default: 297 DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor); 298 break; 299 } 300 } else { 301 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 302 } 303 } 304 305 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 306 { 307 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 308 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 309 310 DRM_DEBUG("SDMA\n"); 311 amdgpu_ucode_print_common_hdr(hdr); 312 313 if (version_major == 1) { 314 const struct sdma_firmware_header_v1_0 *sdma_hdr = 315 container_of(hdr, struct sdma_firmware_header_v1_0, header); 316 317 DRM_DEBUG("ucode_feature_version: %u\n", 318 le32_to_cpu(sdma_hdr->ucode_feature_version)); 319 DRM_DEBUG("ucode_change_version: %u\n", 320 le32_to_cpu(sdma_hdr->ucode_change_version)); 321 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 322 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 323 if (version_minor >= 1) { 324 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 325 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 326 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 327 } 328 } else if (version_major == 2) { 329 const struct sdma_firmware_header_v2_0 *sdma_hdr = 330 container_of(hdr, struct sdma_firmware_header_v2_0, header); 331 332 DRM_DEBUG("ucode_feature_version: %u\n", 333 le32_to_cpu(sdma_hdr->ucode_feature_version)); 334 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset)); 335 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size)); 336 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 337 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset)); 338 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size)); 339 } else { 340 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 341 version_major, version_minor); 342 } 343 } 344 345 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 346 { 347 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 348 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 349 uint32_t fw_index; 350 const struct psp_fw_bin_desc *desc; 351 352 DRM_DEBUG("PSP\n"); 353 amdgpu_ucode_print_common_hdr(hdr); 354 355 if (version_major == 1) { 356 const struct psp_firmware_header_v1_0 *psp_hdr = 357 container_of(hdr, struct psp_firmware_header_v1_0, header); 358 359 DRM_DEBUG("ucode_feature_version: %u\n", 360 le32_to_cpu(psp_hdr->sos.fw_version)); 361 DRM_DEBUG("sos_offset_bytes: %u\n", 362 le32_to_cpu(psp_hdr->sos.offset_bytes)); 363 DRM_DEBUG("sos_size_bytes: %u\n", 364 le32_to_cpu(psp_hdr->sos.size_bytes)); 365 if (version_minor == 1) { 366 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 367 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 368 DRM_DEBUG("toc_header_version: %u\n", 369 le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); 370 DRM_DEBUG("toc_offset_bytes: %u\n", 371 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); 372 DRM_DEBUG("toc_size_bytes: %u\n", 373 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); 374 DRM_DEBUG("kdb_header_version: %u\n", 375 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); 376 DRM_DEBUG("kdb_offset_bytes: %u\n", 377 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); 378 DRM_DEBUG("kdb_size_bytes: %u\n", 379 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); 380 } 381 if (version_minor == 2) { 382 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 383 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 384 DRM_DEBUG("kdb_header_version: %u\n", 385 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); 386 DRM_DEBUG("kdb_offset_bytes: %u\n", 387 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); 388 DRM_DEBUG("kdb_size_bytes: %u\n", 389 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); 390 } 391 if (version_minor == 3) { 392 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 393 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 394 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = 395 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); 396 DRM_DEBUG("toc_header_version: %u\n", 397 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); 398 DRM_DEBUG("toc_offset_bytes: %u\n", 399 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); 400 DRM_DEBUG("toc_size_bytes: %u\n", 401 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); 402 DRM_DEBUG("kdb_header_version: %u\n", 403 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); 404 DRM_DEBUG("kdb_offset_bytes: %u\n", 405 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); 406 DRM_DEBUG("kdb_size_bytes: %u\n", 407 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); 408 DRM_DEBUG("spl_header_version: %u\n", 409 le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); 410 DRM_DEBUG("spl_offset_bytes: %u\n", 411 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); 412 DRM_DEBUG("spl_size_bytes: %u\n", 413 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); 414 } 415 } else if (version_major == 2) { 416 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 = 417 container_of(hdr, struct psp_firmware_header_v2_0, header); 418 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) { 419 desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]); 420 switch (desc->fw_type) { 421 case PSP_FW_TYPE_PSP_SOS: 422 DRM_DEBUG("psp_sos_version: %u\n", 423 le32_to_cpu(desc->fw_version)); 424 DRM_DEBUG("psp_sos_size_bytes: %u\n", 425 le32_to_cpu(desc->size_bytes)); 426 break; 427 case PSP_FW_TYPE_PSP_SYS_DRV: 428 DRM_DEBUG("psp_sys_drv_version: %u\n", 429 le32_to_cpu(desc->fw_version)); 430 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n", 431 le32_to_cpu(desc->size_bytes)); 432 break; 433 case PSP_FW_TYPE_PSP_KDB: 434 DRM_DEBUG("psp_kdb_version: %u\n", 435 le32_to_cpu(desc->fw_version)); 436 DRM_DEBUG("psp_kdb_size_bytes: %u\n", 437 le32_to_cpu(desc->size_bytes)); 438 break; 439 case PSP_FW_TYPE_PSP_TOC: 440 DRM_DEBUG("psp_toc_version: %u\n", 441 le32_to_cpu(desc->fw_version)); 442 DRM_DEBUG("psp_toc_size_bytes: %u\n", 443 le32_to_cpu(desc->size_bytes)); 444 break; 445 case PSP_FW_TYPE_PSP_SPL: 446 DRM_DEBUG("psp_spl_version: %u\n", 447 le32_to_cpu(desc->fw_version)); 448 DRM_DEBUG("psp_spl_size_bytes: %u\n", 449 le32_to_cpu(desc->size_bytes)); 450 break; 451 case PSP_FW_TYPE_PSP_RL: 452 DRM_DEBUG("psp_rl_version: %u\n", 453 le32_to_cpu(desc->fw_version)); 454 DRM_DEBUG("psp_rl_size_bytes: %u\n", 455 le32_to_cpu(desc->size_bytes)); 456 break; 457 case PSP_FW_TYPE_PSP_SOC_DRV: 458 DRM_DEBUG("psp_soc_drv_version: %u\n", 459 le32_to_cpu(desc->fw_version)); 460 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n", 461 le32_to_cpu(desc->size_bytes)); 462 break; 463 case PSP_FW_TYPE_PSP_INTF_DRV: 464 DRM_DEBUG("psp_intf_drv_version: %u\n", 465 le32_to_cpu(desc->fw_version)); 466 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n", 467 le32_to_cpu(desc->size_bytes)); 468 break; 469 case PSP_FW_TYPE_PSP_DBG_DRV: 470 DRM_DEBUG("psp_dbg_drv_version: %u\n", 471 le32_to_cpu(desc->fw_version)); 472 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n", 473 le32_to_cpu(desc->size_bytes)); 474 break; 475 default: 476 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type); 477 break; 478 } 479 } 480 } else { 481 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 482 version_major, version_minor); 483 } 484 } 485 486 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 487 { 488 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 489 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 490 491 DRM_DEBUG("GPU_INFO\n"); 492 amdgpu_ucode_print_common_hdr(hdr); 493 494 if (version_major == 1) { 495 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 496 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 497 498 DRM_DEBUG("version_major: %u\n", 499 le16_to_cpu(gpu_info_hdr->version_major)); 500 DRM_DEBUG("version_minor: %u\n", 501 le16_to_cpu(gpu_info_hdr->version_minor)); 502 } else { 503 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 504 } 505 } 506 507 int amdgpu_ucode_validate(const struct firmware *fw) 508 { 509 const struct common_firmware_header *hdr = 510 (const struct common_firmware_header *)fw->data; 511 512 if (fw->size == le32_to_cpu(hdr->size_bytes)) 513 return 0; 514 515 return -EINVAL; 516 } 517 518 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 519 uint16_t hdr_major, uint16_t hdr_minor) 520 { 521 if ((hdr->common.header_version_major == hdr_major) && 522 (hdr->common.header_version_minor == hdr_minor)) 523 return true; 524 return false; 525 } 526 527 enum amdgpu_firmware_load_type 528 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 529 { 530 switch (adev->asic_type) { 531 #ifdef CONFIG_DRM_AMDGPU_SI 532 case CHIP_TAHITI: 533 case CHIP_PITCAIRN: 534 case CHIP_VERDE: 535 case CHIP_OLAND: 536 case CHIP_HAINAN: 537 return AMDGPU_FW_LOAD_DIRECT; 538 #endif 539 #ifdef CONFIG_DRM_AMDGPU_CIK 540 case CHIP_BONAIRE: 541 case CHIP_KAVERI: 542 case CHIP_KABINI: 543 case CHIP_HAWAII: 544 case CHIP_MULLINS: 545 return AMDGPU_FW_LOAD_DIRECT; 546 #endif 547 case CHIP_TOPAZ: 548 case CHIP_TONGA: 549 case CHIP_FIJI: 550 case CHIP_CARRIZO: 551 case CHIP_STONEY: 552 case CHIP_POLARIS10: 553 case CHIP_POLARIS11: 554 case CHIP_POLARIS12: 555 case CHIP_VEGAM: 556 return AMDGPU_FW_LOAD_SMU; 557 case CHIP_CYAN_SKILLFISH: 558 if (!(load_type && 559 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) 560 return AMDGPU_FW_LOAD_DIRECT; 561 else 562 return AMDGPU_FW_LOAD_PSP; 563 default: 564 if (!load_type) 565 return AMDGPU_FW_LOAD_DIRECT; 566 else 567 return AMDGPU_FW_LOAD_PSP; 568 } 569 } 570 571 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) 572 { 573 switch (ucode_id) { 574 case AMDGPU_UCODE_ID_SDMA0: 575 return "SDMA0"; 576 case AMDGPU_UCODE_ID_SDMA1: 577 return "SDMA1"; 578 case AMDGPU_UCODE_ID_SDMA2: 579 return "SDMA2"; 580 case AMDGPU_UCODE_ID_SDMA3: 581 return "SDMA3"; 582 case AMDGPU_UCODE_ID_SDMA4: 583 return "SDMA4"; 584 case AMDGPU_UCODE_ID_SDMA5: 585 return "SDMA5"; 586 case AMDGPU_UCODE_ID_SDMA6: 587 return "SDMA6"; 588 case AMDGPU_UCODE_ID_SDMA7: 589 return "SDMA7"; 590 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 591 return "SDMA_CTX"; 592 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 593 return "SDMA_CTL"; 594 case AMDGPU_UCODE_ID_CP_CE: 595 return "CP_CE"; 596 case AMDGPU_UCODE_ID_CP_PFP: 597 return "CP_PFP"; 598 case AMDGPU_UCODE_ID_CP_ME: 599 return "CP_ME"; 600 case AMDGPU_UCODE_ID_CP_MEC1: 601 return "CP_MEC1"; 602 case AMDGPU_UCODE_ID_CP_MEC1_JT: 603 return "CP_MEC1_JT"; 604 case AMDGPU_UCODE_ID_CP_MEC2: 605 return "CP_MEC2"; 606 case AMDGPU_UCODE_ID_CP_MEC2_JT: 607 return "CP_MEC2_JT"; 608 case AMDGPU_UCODE_ID_CP_MES: 609 return "CP_MES"; 610 case AMDGPU_UCODE_ID_CP_MES_DATA: 611 return "CP_MES_DATA"; 612 case AMDGPU_UCODE_ID_CP_MES1: 613 return "CP_MES_KIQ"; 614 case AMDGPU_UCODE_ID_CP_MES1_DATA: 615 return "CP_MES_KIQ_DATA"; 616 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 617 return "RLC_RESTORE_LIST_CNTL"; 618 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 619 return "RLC_RESTORE_LIST_GPM_MEM"; 620 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 621 return "RLC_RESTORE_LIST_SRM_MEM"; 622 case AMDGPU_UCODE_ID_RLC_IRAM: 623 return "RLC_IRAM"; 624 case AMDGPU_UCODE_ID_RLC_DRAM: 625 return "RLC_DRAM"; 626 case AMDGPU_UCODE_ID_RLC_G: 627 return "RLC_G"; 628 case AMDGPU_UCODE_ID_RLC_P: 629 return "RLC_P"; 630 case AMDGPU_UCODE_ID_RLC_V: 631 return "RLC_V"; 632 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 633 return "GLOBAL_TAP_DELAYS"; 634 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 635 return "SE0_TAP_DELAYS"; 636 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 637 return "SE1_TAP_DELAYS"; 638 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 639 return "SE2_TAP_DELAYS"; 640 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 641 return "SE3_TAP_DELAYS"; 642 case AMDGPU_UCODE_ID_IMU_I: 643 return "IMU_I"; 644 case AMDGPU_UCODE_ID_IMU_D: 645 return "IMU_D"; 646 case AMDGPU_UCODE_ID_STORAGE: 647 return "STORAGE"; 648 case AMDGPU_UCODE_ID_SMC: 649 return "SMC"; 650 case AMDGPU_UCODE_ID_PPTABLE: 651 return "PPTABLE"; 652 case AMDGPU_UCODE_ID_UVD: 653 return "UVD"; 654 case AMDGPU_UCODE_ID_UVD1: 655 return "UVD1"; 656 case AMDGPU_UCODE_ID_VCE: 657 return "VCE"; 658 case AMDGPU_UCODE_ID_VCN: 659 return "VCN"; 660 case AMDGPU_UCODE_ID_VCN1: 661 return "VCN1"; 662 case AMDGPU_UCODE_ID_DMCU_ERAM: 663 return "DMCU_ERAM"; 664 case AMDGPU_UCODE_ID_DMCU_INTV: 665 return "DMCU_INTV"; 666 case AMDGPU_UCODE_ID_VCN0_RAM: 667 return "VCN0_RAM"; 668 case AMDGPU_UCODE_ID_VCN1_RAM: 669 return "VCN1_RAM"; 670 case AMDGPU_UCODE_ID_DMCUB: 671 return "DMCUB"; 672 default: 673 return "UNKNOWN UCODE"; 674 } 675 } 676 677 #define FW_VERSION_ATTR(name, mode, field) \ 678 static ssize_t show_##name(struct device *dev, \ 679 struct device_attribute *attr, \ 680 char *buf) \ 681 { \ 682 struct drm_device *ddev = dev_get_drvdata(dev); \ 683 struct amdgpu_device *adev = drm_to_adev(ddev); \ 684 \ 685 return sysfs_emit(buf, "0x%08x\n", adev->field); \ 686 } \ 687 static DEVICE_ATTR(name, mode, show_##name, NULL) 688 689 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 690 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 691 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 692 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 693 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 694 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 695 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 696 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 697 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 698 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 699 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 700 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 701 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version); 702 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version); 703 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version); 704 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version); 705 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version); 706 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 707 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 708 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 709 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 710 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 711 712 static struct attribute *fw_attrs[] = { 713 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 714 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 715 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 716 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 717 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 718 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 719 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 720 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 721 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 722 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 723 &dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr, 724 NULL 725 }; 726 727 static const struct attribute_group fw_attr_group = { 728 .name = "fw_version", 729 .attrs = fw_attrs 730 }; 731 732 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 733 { 734 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 735 } 736 737 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 738 { 739 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 740 } 741 742 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 743 struct amdgpu_firmware_info *ucode, 744 uint64_t mc_addr, void *kptr) 745 { 746 const struct common_firmware_header *header = NULL; 747 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 748 const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL; 749 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 750 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 751 const struct mes_firmware_header_v1_0 *mes_hdr = NULL; 752 const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL; 753 const struct imu_firmware_header_v1_0 *imu_hdr = NULL; 754 u8 *ucode_addr; 755 756 if (NULL == ucode->fw) 757 return 0; 758 759 ucode->mc_addr = mc_addr; 760 ucode->kaddr = kptr; 761 762 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 763 return 0; 764 765 header = (const struct common_firmware_header *)ucode->fw->data; 766 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 767 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; 768 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 769 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 770 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; 771 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data; 772 imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data; 773 774 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 775 switch (ucode->ucode_id) { 776 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 777 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 778 ucode_addr = (u8 *)ucode->fw->data + 779 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes); 780 break; 781 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 782 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 783 ucode_addr = (u8 *)ucode->fw->data + 784 le32_to_cpu(sdma_hdr->ctl_ucode_offset); 785 break; 786 case AMDGPU_UCODE_ID_CP_MEC1: 787 case AMDGPU_UCODE_ID_CP_MEC2: 788 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 789 le32_to_cpu(cp_hdr->jt_size) * 4; 790 ucode_addr = (u8 *)ucode->fw->data + 791 le32_to_cpu(header->ucode_array_offset_bytes); 792 break; 793 case AMDGPU_UCODE_ID_CP_MEC1_JT: 794 case AMDGPU_UCODE_ID_CP_MEC2_JT: 795 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 796 ucode_addr = (u8 *)ucode->fw->data + 797 le32_to_cpu(header->ucode_array_offset_bytes) + 798 le32_to_cpu(cp_hdr->jt_offset) * 4; 799 break; 800 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 801 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 802 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; 803 break; 804 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 805 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 806 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; 807 break; 808 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 809 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 810 ucode_addr = adev->gfx.rlc.save_restore_list_srm; 811 break; 812 case AMDGPU_UCODE_ID_RLC_IRAM: 813 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; 814 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; 815 break; 816 case AMDGPU_UCODE_ID_RLC_DRAM: 817 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; 818 ucode_addr = adev->gfx.rlc.rlc_dram_ucode; 819 break; 820 case AMDGPU_UCODE_ID_RLC_P: 821 ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes; 822 ucode_addr = adev->gfx.rlc.rlcp_ucode; 823 break; 824 case AMDGPU_UCODE_ID_RLC_V: 825 ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes; 826 ucode_addr = adev->gfx.rlc.rlcv_ucode; 827 break; 828 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 829 ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes; 830 ucode_addr = adev->gfx.rlc.global_tap_delays_ucode; 831 break; 832 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 833 ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes; 834 ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode; 835 break; 836 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 837 ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes; 838 ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode; 839 break; 840 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 841 ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes; 842 ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode; 843 break; 844 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 845 ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes; 846 ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode; 847 break; 848 case AMDGPU_UCODE_ID_CP_MES: 849 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 850 ucode_addr = (u8 *)ucode->fw->data + 851 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 852 break; 853 case AMDGPU_UCODE_ID_CP_MES_DATA: 854 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 855 ucode_addr = (u8 *)ucode->fw->data + 856 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 857 break; 858 case AMDGPU_UCODE_ID_CP_MES1: 859 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 860 ucode_addr = (u8 *)ucode->fw->data + 861 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 862 break; 863 case AMDGPU_UCODE_ID_CP_MES1_DATA: 864 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 865 ucode_addr = (u8 *)ucode->fw->data + 866 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 867 break; 868 case AMDGPU_UCODE_ID_DMCU_ERAM: 869 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 870 le32_to_cpu(dmcu_hdr->intv_size_bytes); 871 ucode_addr = (u8 *)ucode->fw->data + 872 le32_to_cpu(header->ucode_array_offset_bytes); 873 break; 874 case AMDGPU_UCODE_ID_DMCU_INTV: 875 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 876 ucode_addr = (u8 *)ucode->fw->data + 877 le32_to_cpu(header->ucode_array_offset_bytes) + 878 le32_to_cpu(dmcu_hdr->intv_offset_bytes); 879 break; 880 case AMDGPU_UCODE_ID_DMCUB: 881 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 882 ucode_addr = (u8 *)ucode->fw->data + 883 le32_to_cpu(header->ucode_array_offset_bytes); 884 break; 885 case AMDGPU_UCODE_ID_PPTABLE: 886 ucode->ucode_size = ucode->fw->size; 887 ucode_addr = (u8 *)ucode->fw->data; 888 break; 889 case AMDGPU_UCODE_ID_IMU_I: 890 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 891 ucode_addr = (u8 *)ucode->fw->data + 892 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes); 893 break; 894 case AMDGPU_UCODE_ID_IMU_D: 895 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes); 896 ucode_addr = (u8 *)ucode->fw->data + 897 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) + 898 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 899 break; 900 case AMDGPU_UCODE_ID_CP_RS64_PFP: 901 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 902 ucode_addr = (u8 *)ucode->fw->data + 903 le32_to_cpu(header->ucode_array_offset_bytes); 904 break; 905 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 906 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 907 ucode_addr = (u8 *)ucode->fw->data + 908 le32_to_cpu(cpv2_hdr->data_offset_bytes); 909 break; 910 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 911 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 912 ucode_addr = (u8 *)ucode->fw->data + 913 le32_to_cpu(cpv2_hdr->data_offset_bytes); 914 break; 915 case AMDGPU_UCODE_ID_CP_RS64_ME: 916 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 917 ucode_addr = (u8 *)ucode->fw->data + 918 le32_to_cpu(header->ucode_array_offset_bytes); 919 break; 920 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 921 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 922 ucode_addr = (u8 *)ucode->fw->data + 923 le32_to_cpu(cpv2_hdr->data_offset_bytes); 924 break; 925 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 926 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 927 ucode_addr = (u8 *)ucode->fw->data + 928 le32_to_cpu(cpv2_hdr->data_offset_bytes); 929 break; 930 case AMDGPU_UCODE_ID_CP_RS64_MEC: 931 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 932 ucode_addr = (u8 *)ucode->fw->data + 933 le32_to_cpu(header->ucode_array_offset_bytes); 934 break; 935 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 936 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 937 ucode_addr = (u8 *)ucode->fw->data + 938 le32_to_cpu(cpv2_hdr->data_offset_bytes); 939 break; 940 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 941 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 942 ucode_addr = (u8 *)ucode->fw->data + 943 le32_to_cpu(cpv2_hdr->data_offset_bytes); 944 break; 945 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 946 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 947 ucode_addr = (u8 *)ucode->fw->data + 948 le32_to_cpu(cpv2_hdr->data_offset_bytes); 949 break; 950 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 951 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 952 ucode_addr = (u8 *)ucode->fw->data + 953 le32_to_cpu(cpv2_hdr->data_offset_bytes); 954 break; 955 default: 956 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 957 ucode_addr = (u8 *)ucode->fw->data + 958 le32_to_cpu(header->ucode_array_offset_bytes); 959 break; 960 } 961 } else { 962 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 963 ucode_addr = (u8 *)ucode->fw->data + 964 le32_to_cpu(header->ucode_array_offset_bytes); 965 } 966 967 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size); 968 969 return 0; 970 } 971 972 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 973 uint64_t mc_addr, void *kptr) 974 { 975 const struct gfx_firmware_header_v1_0 *header = NULL; 976 const struct common_firmware_header *comm_hdr = NULL; 977 uint8_t *src_addr = NULL; 978 uint8_t *dst_addr = NULL; 979 980 if (NULL == ucode->fw) 981 return 0; 982 983 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 984 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 985 dst_addr = ucode->kaddr + 986 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 987 PAGE_SIZE); 988 src_addr = (uint8_t *)ucode->fw->data + 989 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 990 (le32_to_cpu(header->jt_offset) * 4); 991 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 992 993 return 0; 994 } 995 996 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 997 { 998 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) { 999 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 1000 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 1001 &adev->firmware.fw_buf, 1002 &adev->firmware.fw_buf_mc, 1003 &adev->firmware.fw_buf_ptr); 1004 if (!adev->firmware.fw_buf) { 1005 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 1006 return -ENOMEM; 1007 } else if (amdgpu_sriov_vf(adev)) { 1008 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 1009 } 1010 } 1011 return 0; 1012 } 1013 1014 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 1015 { 1016 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 1017 &adev->firmware.fw_buf_mc, 1018 &adev->firmware.fw_buf_ptr); 1019 } 1020 1021 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 1022 { 1023 uint64_t fw_offset = 0; 1024 int i; 1025 struct amdgpu_firmware_info *ucode = NULL; 1026 1027 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 1028 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend)) 1029 return 0; 1030 /* 1031 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 1032 * ucode info here 1033 */ 1034 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1035 if (amdgpu_sriov_vf(adev)) 1036 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 1037 else 1038 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 1039 } else { 1040 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 1041 } 1042 1043 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1044 ucode = &adev->firmware.ucode[i]; 1045 if (ucode->fw) { 1046 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 1047 adev->firmware.fw_buf_ptr + fw_offset); 1048 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 1049 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1050 const struct gfx_firmware_header_v1_0 *cp_hdr; 1051 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 1052 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 1053 adev->firmware.fw_buf_ptr + fw_offset); 1054 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 1055 } 1056 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 1057 } 1058 } 1059 return 0; 1060 } 1061 1062 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len) 1063 { 1064 int maj, min, rev; 1065 char *ip_name; 1066 uint32_t version = adev->ip_versions[block_type][0]; 1067 1068 switch (block_type) { 1069 case GC_HWIP: 1070 ip_name = "gc"; 1071 break; 1072 case SDMA0_HWIP: 1073 ip_name = "sdma"; 1074 break; 1075 case MP0_HWIP: 1076 ip_name = "psp"; 1077 break; 1078 case MP1_HWIP: 1079 ip_name = "smu"; 1080 break; 1081 case UVD_HWIP: 1082 ip_name = "vcn"; 1083 break; 1084 default: 1085 BUG(); 1086 } 1087 1088 maj = IP_VERSION_MAJ(version); 1089 min = IP_VERSION_MIN(version); 1090 rev = IP_VERSION_REV(version); 1091 1092 snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev); 1093 } 1094