1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 32 { 33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 41 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 42 le32_to_cpu(hdr->ucode_array_offset_bytes)); 43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 44 } 45 46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 47 { 48 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 50 51 DRM_DEBUG("MC\n"); 52 amdgpu_ucode_print_common_hdr(hdr); 53 54 if (version_major == 1) { 55 const struct mc_firmware_header_v1_0 *mc_hdr = 56 container_of(hdr, struct mc_firmware_header_v1_0, header); 57 58 DRM_DEBUG("io_debug_size_bytes: %u\n", 59 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 62 } else { 63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 64 } 65 } 66 67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 68 { 69 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 71 const struct smc_firmware_header_v1_0 *v1_0_hdr; 72 const struct smc_firmware_header_v2_0 *v2_0_hdr; 73 const struct smc_firmware_header_v2_1 *v2_1_hdr; 74 75 DRM_DEBUG("SMC\n"); 76 amdgpu_ucode_print_common_hdr(hdr); 77 78 if (version_major == 1) { 79 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); 80 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); 81 } else if (version_major == 2) { 82 switch (version_minor) { 83 case 0: 84 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); 85 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); 86 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); 87 break; 88 case 1: 89 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); 90 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); 91 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); 92 break; 93 default: 94 break; 95 } 96 97 } else { 98 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 99 } 100 } 101 102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 103 { 104 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 105 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 106 107 DRM_DEBUG("GFX\n"); 108 amdgpu_ucode_print_common_hdr(hdr); 109 110 if (version_major == 1) { 111 const struct gfx_firmware_header_v1_0 *gfx_hdr = 112 container_of(hdr, struct gfx_firmware_header_v1_0, header); 113 114 DRM_DEBUG("ucode_feature_version: %u\n", 115 le32_to_cpu(gfx_hdr->ucode_feature_version)); 116 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 117 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 118 } else { 119 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 120 } 121 } 122 123 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 124 { 125 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 126 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 127 128 DRM_DEBUG("RLC\n"); 129 amdgpu_ucode_print_common_hdr(hdr); 130 131 if (version_major == 1) { 132 const struct rlc_firmware_header_v1_0 *rlc_hdr = 133 container_of(hdr, struct rlc_firmware_header_v1_0, header); 134 135 DRM_DEBUG("ucode_feature_version: %u\n", 136 le32_to_cpu(rlc_hdr->ucode_feature_version)); 137 DRM_DEBUG("save_and_restore_offset: %u\n", 138 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 139 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 140 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 141 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 142 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 143 DRM_DEBUG("master_pkt_description_offset: %u\n", 144 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 145 } else if (version_major == 2) { 146 const struct rlc_firmware_header_v2_0 *rlc_hdr = 147 container_of(hdr, struct rlc_firmware_header_v2_0, header); 148 149 DRM_DEBUG("ucode_feature_version: %u\n", 150 le32_to_cpu(rlc_hdr->ucode_feature_version)); 151 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 152 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 153 DRM_DEBUG("save_and_restore_offset: %u\n", 154 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 155 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 156 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 157 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 158 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 159 DRM_DEBUG("reg_restore_list_size: %u\n", 160 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 161 DRM_DEBUG("reg_list_format_start: %u\n", 162 le32_to_cpu(rlc_hdr->reg_list_format_start)); 163 DRM_DEBUG("reg_list_format_separate_start: %u\n", 164 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 165 DRM_DEBUG("starting_offsets_start: %u\n", 166 le32_to_cpu(rlc_hdr->starting_offsets_start)); 167 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 168 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 169 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 170 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 171 DRM_DEBUG("reg_list_size_bytes: %u\n", 172 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 173 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 174 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 175 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 176 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 177 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 178 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 179 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 180 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 181 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 182 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 183 if (version_minor == 1) { 184 const struct rlc_firmware_header_v2_1 *v2_1 = 185 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 186 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 187 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); 188 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 189 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); 190 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 191 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); 192 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 193 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); 194 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 195 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); 196 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 197 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); 198 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 199 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); 200 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 201 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); 202 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 203 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); 204 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 205 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); 206 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 207 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); 208 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 209 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes)); 210 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 211 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes)); 212 } 213 } else { 214 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 215 } 216 } 217 218 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 219 { 220 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 221 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 222 223 DRM_DEBUG("SDMA\n"); 224 amdgpu_ucode_print_common_hdr(hdr); 225 226 if (version_major == 1) { 227 const struct sdma_firmware_header_v1_0 *sdma_hdr = 228 container_of(hdr, struct sdma_firmware_header_v1_0, header); 229 230 DRM_DEBUG("ucode_feature_version: %u\n", 231 le32_to_cpu(sdma_hdr->ucode_feature_version)); 232 DRM_DEBUG("ucode_change_version: %u\n", 233 le32_to_cpu(sdma_hdr->ucode_change_version)); 234 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 235 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 236 if (version_minor >= 1) { 237 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 238 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 239 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 240 } 241 } else { 242 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 243 version_major, version_minor); 244 } 245 } 246 247 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 248 { 249 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 250 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 251 uint32_t fw_index; 252 const struct psp_fw_bin_desc *desc; 253 254 DRM_DEBUG("PSP\n"); 255 amdgpu_ucode_print_common_hdr(hdr); 256 257 if (version_major == 1) { 258 const struct psp_firmware_header_v1_0 *psp_hdr = 259 container_of(hdr, struct psp_firmware_header_v1_0, header); 260 261 DRM_DEBUG("ucode_feature_version: %u\n", 262 le32_to_cpu(psp_hdr->sos.fw_version)); 263 DRM_DEBUG("sos_offset_bytes: %u\n", 264 le32_to_cpu(psp_hdr->sos.offset_bytes)); 265 DRM_DEBUG("sos_size_bytes: %u\n", 266 le32_to_cpu(psp_hdr->sos.size_bytes)); 267 if (version_minor == 1) { 268 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 269 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 270 DRM_DEBUG("toc_header_version: %u\n", 271 le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); 272 DRM_DEBUG("toc_offset_bytes: %u\n", 273 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); 274 DRM_DEBUG("toc_size_bytes: %u\n", 275 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); 276 DRM_DEBUG("kdb_header_version: %u\n", 277 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); 278 DRM_DEBUG("kdb_offset_bytes: %u\n", 279 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); 280 DRM_DEBUG("kdb_size_bytes: %u\n", 281 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); 282 } 283 if (version_minor == 2) { 284 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 285 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 286 DRM_DEBUG("kdb_header_version: %u\n", 287 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); 288 DRM_DEBUG("kdb_offset_bytes: %u\n", 289 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); 290 DRM_DEBUG("kdb_size_bytes: %u\n", 291 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); 292 } 293 if (version_minor == 3) { 294 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 295 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 296 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = 297 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); 298 DRM_DEBUG("toc_header_version: %u\n", 299 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); 300 DRM_DEBUG("toc_offset_bytes: %u\n", 301 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); 302 DRM_DEBUG("toc_size_bytes: %u\n", 303 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); 304 DRM_DEBUG("kdb_header_version: %u\n", 305 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); 306 DRM_DEBUG("kdb_offset_bytes: %u\n", 307 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); 308 DRM_DEBUG("kdb_size_bytes: %u\n", 309 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); 310 DRM_DEBUG("spl_header_version: %u\n", 311 le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); 312 DRM_DEBUG("spl_offset_bytes: %u\n", 313 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); 314 DRM_DEBUG("spl_size_bytes: %u\n", 315 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); 316 } 317 } else if (version_major == 2) { 318 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 = 319 container_of(hdr, struct psp_firmware_header_v2_0, header); 320 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) { 321 desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]); 322 switch (desc->fw_type) { 323 case PSP_FW_TYPE_PSP_SOS: 324 DRM_DEBUG("psp_sos_version: %u\n", 325 le32_to_cpu(desc->fw_version)); 326 DRM_DEBUG("psp_sos_size_bytes: %u\n", 327 le32_to_cpu(desc->size_bytes)); 328 break; 329 case PSP_FW_TYPE_PSP_SYS_DRV: 330 DRM_DEBUG("psp_sys_drv_version: %u\n", 331 le32_to_cpu(desc->fw_version)); 332 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n", 333 le32_to_cpu(desc->size_bytes)); 334 break; 335 case PSP_FW_TYPE_PSP_KDB: 336 DRM_DEBUG("psp_kdb_version: %u\n", 337 le32_to_cpu(desc->fw_version)); 338 DRM_DEBUG("psp_kdb_size_bytes: %u\n", 339 le32_to_cpu(desc->size_bytes)); 340 break; 341 case PSP_FW_TYPE_PSP_TOC: 342 DRM_DEBUG("psp_toc_version: %u\n", 343 le32_to_cpu(desc->fw_version)); 344 DRM_DEBUG("psp_toc_size_bytes: %u\n", 345 le32_to_cpu(desc->size_bytes)); 346 break; 347 case PSP_FW_TYPE_PSP_SPL: 348 DRM_DEBUG("psp_spl_version: %u\n", 349 le32_to_cpu(desc->fw_version)); 350 DRM_DEBUG("psp_spl_size_bytes: %u\n", 351 le32_to_cpu(desc->size_bytes)); 352 break; 353 case PSP_FW_TYPE_PSP_RL: 354 DRM_DEBUG("psp_rl_version: %u\n", 355 le32_to_cpu(desc->fw_version)); 356 DRM_DEBUG("psp_rl_size_bytes: %u\n", 357 le32_to_cpu(desc->size_bytes)); 358 break; 359 case PSP_FW_TYPE_PSP_SOC_DRV: 360 DRM_DEBUG("psp_soc_drv_version: %u\n", 361 le32_to_cpu(desc->fw_version)); 362 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n", 363 le32_to_cpu(desc->size_bytes)); 364 break; 365 case PSP_FW_TYPE_PSP_INTF_DRV: 366 DRM_DEBUG("psp_intf_drv_version: %u\n", 367 le32_to_cpu(desc->fw_version)); 368 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n", 369 le32_to_cpu(desc->size_bytes)); 370 break; 371 case PSP_FW_TYPE_PSP_DBG_DRV: 372 DRM_DEBUG("psp_dbg_drv_version: %u\n", 373 le32_to_cpu(desc->fw_version)); 374 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n", 375 le32_to_cpu(desc->size_bytes)); 376 break; 377 default: 378 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type); 379 break; 380 } 381 } 382 } else { 383 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 384 version_major, version_minor); 385 } 386 } 387 388 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 389 { 390 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 391 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 392 393 DRM_DEBUG("GPU_INFO\n"); 394 amdgpu_ucode_print_common_hdr(hdr); 395 396 if (version_major == 1) { 397 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 398 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 399 400 DRM_DEBUG("version_major: %u\n", 401 le16_to_cpu(gpu_info_hdr->version_major)); 402 DRM_DEBUG("version_minor: %u\n", 403 le16_to_cpu(gpu_info_hdr->version_minor)); 404 } else { 405 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 406 } 407 } 408 409 int amdgpu_ucode_validate(const struct firmware *fw) 410 { 411 const struct common_firmware_header *hdr = 412 (const struct common_firmware_header *)fw->data; 413 414 if (fw->size == le32_to_cpu(hdr->size_bytes)) 415 return 0; 416 417 return -EINVAL; 418 } 419 420 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 421 uint16_t hdr_major, uint16_t hdr_minor) 422 { 423 if ((hdr->common.header_version_major == hdr_major) && 424 (hdr->common.header_version_minor == hdr_minor)) 425 return false; 426 return true; 427 } 428 429 enum amdgpu_firmware_load_type 430 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 431 { 432 switch (adev->asic_type) { 433 #ifdef CONFIG_DRM_AMDGPU_SI 434 case CHIP_TAHITI: 435 case CHIP_PITCAIRN: 436 case CHIP_VERDE: 437 case CHIP_OLAND: 438 case CHIP_HAINAN: 439 return AMDGPU_FW_LOAD_DIRECT; 440 #endif 441 #ifdef CONFIG_DRM_AMDGPU_CIK 442 case CHIP_BONAIRE: 443 case CHIP_KAVERI: 444 case CHIP_KABINI: 445 case CHIP_HAWAII: 446 case CHIP_MULLINS: 447 return AMDGPU_FW_LOAD_DIRECT; 448 #endif 449 case CHIP_TOPAZ: 450 case CHIP_TONGA: 451 case CHIP_FIJI: 452 case CHIP_CARRIZO: 453 case CHIP_STONEY: 454 case CHIP_POLARIS10: 455 case CHIP_POLARIS11: 456 case CHIP_POLARIS12: 457 case CHIP_VEGAM: 458 return AMDGPU_FW_LOAD_SMU; 459 case CHIP_VEGA10: 460 case CHIP_RAVEN: 461 case CHIP_VEGA12: 462 case CHIP_VEGA20: 463 case CHIP_ARCTURUS: 464 case CHIP_RENOIR: 465 case CHIP_NAVI10: 466 case CHIP_NAVI14: 467 case CHIP_NAVI12: 468 case CHIP_SIENNA_CICHLID: 469 case CHIP_NAVY_FLOUNDER: 470 case CHIP_VANGOGH: 471 case CHIP_DIMGREY_CAVEFISH: 472 case CHIP_ALDEBARAN: 473 case CHIP_BEIGE_GOBY: 474 case CHIP_YELLOW_CARP: 475 if (!load_type) 476 return AMDGPU_FW_LOAD_DIRECT; 477 else 478 return AMDGPU_FW_LOAD_PSP; 479 case CHIP_CYAN_SKILLFISH: 480 if (!(load_type && 481 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) 482 return AMDGPU_FW_LOAD_DIRECT; 483 else 484 return AMDGPU_FW_LOAD_PSP; 485 default: 486 if (!load_type) 487 return AMDGPU_FW_LOAD_DIRECT; 488 else 489 return AMDGPU_FW_LOAD_PSP; 490 } 491 } 492 493 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) 494 { 495 switch (ucode_id) { 496 case AMDGPU_UCODE_ID_SDMA0: 497 return "SDMA0"; 498 case AMDGPU_UCODE_ID_SDMA1: 499 return "SDMA1"; 500 case AMDGPU_UCODE_ID_SDMA2: 501 return "SDMA2"; 502 case AMDGPU_UCODE_ID_SDMA3: 503 return "SDMA3"; 504 case AMDGPU_UCODE_ID_SDMA4: 505 return "SDMA4"; 506 case AMDGPU_UCODE_ID_SDMA5: 507 return "SDMA5"; 508 case AMDGPU_UCODE_ID_SDMA6: 509 return "SDMA6"; 510 case AMDGPU_UCODE_ID_SDMA7: 511 return "SDMA7"; 512 case AMDGPU_UCODE_ID_CP_CE: 513 return "CP_CE"; 514 case AMDGPU_UCODE_ID_CP_PFP: 515 return "CP_PFP"; 516 case AMDGPU_UCODE_ID_CP_ME: 517 return "CP_ME"; 518 case AMDGPU_UCODE_ID_CP_MEC1: 519 return "CP_MEC1"; 520 case AMDGPU_UCODE_ID_CP_MEC1_JT: 521 return "CP_MEC1_JT"; 522 case AMDGPU_UCODE_ID_CP_MEC2: 523 return "CP_MEC2"; 524 case AMDGPU_UCODE_ID_CP_MEC2_JT: 525 return "CP_MEC2_JT"; 526 case AMDGPU_UCODE_ID_CP_MES: 527 return "CP_MES"; 528 case AMDGPU_UCODE_ID_CP_MES_DATA: 529 return "CP_MES_DATA"; 530 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 531 return "RLC_RESTORE_LIST_CNTL"; 532 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 533 return "RLC_RESTORE_LIST_GPM_MEM"; 534 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 535 return "RLC_RESTORE_LIST_SRM_MEM"; 536 case AMDGPU_UCODE_ID_RLC_IRAM: 537 return "RLC_IRAM"; 538 case AMDGPU_UCODE_ID_RLC_DRAM: 539 return "RLC_DRAM"; 540 case AMDGPU_UCODE_ID_RLC_G: 541 return "RLC_G"; 542 case AMDGPU_UCODE_ID_STORAGE: 543 return "STORAGE"; 544 case AMDGPU_UCODE_ID_SMC: 545 return "SMC"; 546 case AMDGPU_UCODE_ID_UVD: 547 return "UVD"; 548 case AMDGPU_UCODE_ID_UVD1: 549 return "UVD1"; 550 case AMDGPU_UCODE_ID_VCE: 551 return "VCE"; 552 case AMDGPU_UCODE_ID_VCN: 553 return "VCN"; 554 case AMDGPU_UCODE_ID_VCN1: 555 return "VCN1"; 556 case AMDGPU_UCODE_ID_DMCU_ERAM: 557 return "DMCU_ERAM"; 558 case AMDGPU_UCODE_ID_DMCU_INTV: 559 return "DMCU_INTV"; 560 case AMDGPU_UCODE_ID_VCN0_RAM: 561 return "VCN0_RAM"; 562 case AMDGPU_UCODE_ID_VCN1_RAM: 563 return "VCN1_RAM"; 564 case AMDGPU_UCODE_ID_DMCUB: 565 return "DMCUB"; 566 default: 567 return "UNKNOWN UCODE"; 568 } 569 } 570 571 #define FW_VERSION_ATTR(name, mode, field) \ 572 static ssize_t show_##name(struct device *dev, \ 573 struct device_attribute *attr, \ 574 char *buf) \ 575 { \ 576 struct drm_device *ddev = dev_get_drvdata(dev); \ 577 struct amdgpu_device *adev = drm_to_adev(ddev); \ 578 \ 579 return sysfs_emit(buf, "0x%08x\n", adev->field); \ 580 } \ 581 static DEVICE_ATTR(name, mode, show_##name, NULL) 582 583 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 584 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 585 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 586 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 587 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 588 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 589 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 590 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 591 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 592 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 593 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 594 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 595 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version); 596 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version); 597 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version); 598 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version); 599 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 600 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 601 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 602 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 603 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 604 605 static struct attribute *fw_attrs[] = { 606 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 607 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 608 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 609 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 610 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 611 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 612 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 613 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 614 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 615 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 616 &dev_attr_dmcu_fw_version.attr, NULL 617 }; 618 619 static const struct attribute_group fw_attr_group = { 620 .name = "fw_version", 621 .attrs = fw_attrs 622 }; 623 624 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 625 { 626 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 627 } 628 629 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 630 { 631 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 632 } 633 634 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 635 struct amdgpu_firmware_info *ucode, 636 uint64_t mc_addr, void *kptr) 637 { 638 const struct common_firmware_header *header = NULL; 639 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 640 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 641 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 642 const struct mes_firmware_header_v1_0 *mes_hdr = NULL; 643 u8 *ucode_addr; 644 645 if (NULL == ucode->fw) 646 return 0; 647 648 ucode->mc_addr = mc_addr; 649 ucode->kaddr = kptr; 650 651 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 652 return 0; 653 654 header = (const struct common_firmware_header *)ucode->fw->data; 655 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 656 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 657 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 658 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; 659 660 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 661 switch (ucode->ucode_id) { 662 case AMDGPU_UCODE_ID_CP_MEC1: 663 case AMDGPU_UCODE_ID_CP_MEC2: 664 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 665 le32_to_cpu(cp_hdr->jt_size) * 4; 666 ucode_addr = (u8 *)ucode->fw->data + 667 le32_to_cpu(header->ucode_array_offset_bytes); 668 break; 669 case AMDGPU_UCODE_ID_CP_MEC1_JT: 670 case AMDGPU_UCODE_ID_CP_MEC2_JT: 671 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 672 ucode_addr = (u8 *)ucode->fw->data + 673 le32_to_cpu(header->ucode_array_offset_bytes) + 674 le32_to_cpu(cp_hdr->jt_offset) * 4; 675 break; 676 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 677 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 678 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; 679 break; 680 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 681 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 682 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; 683 break; 684 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 685 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 686 ucode_addr = adev->gfx.rlc.save_restore_list_srm; 687 break; 688 case AMDGPU_UCODE_ID_RLC_IRAM: 689 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; 690 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; 691 break; 692 case AMDGPU_UCODE_ID_RLC_DRAM: 693 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; 694 ucode_addr = adev->gfx.rlc.rlc_dram_ucode; 695 break; 696 case AMDGPU_UCODE_ID_CP_MES: 697 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 698 ucode_addr = (u8 *)ucode->fw->data + 699 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 700 break; 701 case AMDGPU_UCODE_ID_CP_MES_DATA: 702 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 703 ucode_addr = (u8 *)ucode->fw->data + 704 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 705 break; 706 case AMDGPU_UCODE_ID_DMCU_ERAM: 707 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 708 le32_to_cpu(dmcu_hdr->intv_size_bytes); 709 ucode_addr = (u8 *)ucode->fw->data + 710 le32_to_cpu(header->ucode_array_offset_bytes); 711 break; 712 case AMDGPU_UCODE_ID_DMCU_INTV: 713 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 714 ucode_addr = (u8 *)ucode->fw->data + 715 le32_to_cpu(header->ucode_array_offset_bytes) + 716 le32_to_cpu(dmcu_hdr->intv_offset_bytes); 717 break; 718 case AMDGPU_UCODE_ID_DMCUB: 719 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 720 ucode_addr = (u8 *)ucode->fw->data + 721 le32_to_cpu(header->ucode_array_offset_bytes); 722 break; 723 default: 724 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 725 ucode_addr = (u8 *)ucode->fw->data + 726 le32_to_cpu(header->ucode_array_offset_bytes); 727 break; 728 } 729 } else { 730 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 731 ucode_addr = (u8 *)ucode->fw->data + 732 le32_to_cpu(header->ucode_array_offset_bytes); 733 } 734 735 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size); 736 737 return 0; 738 } 739 740 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 741 uint64_t mc_addr, void *kptr) 742 { 743 const struct gfx_firmware_header_v1_0 *header = NULL; 744 const struct common_firmware_header *comm_hdr = NULL; 745 uint8_t *src_addr = NULL; 746 uint8_t *dst_addr = NULL; 747 748 if (NULL == ucode->fw) 749 return 0; 750 751 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 752 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 753 dst_addr = ucode->kaddr + 754 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 755 PAGE_SIZE); 756 src_addr = (uint8_t *)ucode->fw->data + 757 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 758 (le32_to_cpu(header->jt_offset) * 4); 759 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 760 761 return 0; 762 } 763 764 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 765 { 766 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) { 767 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 768 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 769 &adev->firmware.fw_buf, 770 &adev->firmware.fw_buf_mc, 771 &adev->firmware.fw_buf_ptr); 772 if (!adev->firmware.fw_buf) { 773 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 774 return -ENOMEM; 775 } else if (amdgpu_sriov_vf(adev)) { 776 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 777 } 778 } 779 return 0; 780 } 781 782 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 783 { 784 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) 785 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 786 &adev->firmware.fw_buf_mc, 787 &adev->firmware.fw_buf_ptr); 788 } 789 790 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 791 { 792 uint64_t fw_offset = 0; 793 int i; 794 struct amdgpu_firmware_info *ucode = NULL; 795 796 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 797 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend)) 798 return 0; 799 /* 800 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 801 * ucode info here 802 */ 803 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 804 if (amdgpu_sriov_vf(adev)) 805 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 806 else 807 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 808 } else { 809 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 810 } 811 812 for (i = 0; i < adev->firmware.max_ucodes; i++) { 813 ucode = &adev->firmware.ucode[i]; 814 if (ucode->fw) { 815 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 816 adev->firmware.fw_buf_ptr + fw_offset); 817 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 818 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 819 const struct gfx_firmware_header_v1_0 *cp_hdr; 820 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 821 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 822 adev->firmware.fw_buf_ptr + fw_offset); 823 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 824 } 825 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 826 } 827 } 828 return 0; 829 } 830 831 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len) 832 { 833 int maj, min, rev; 834 char *ip_name; 835 uint32_t version = adev->ip_versions[block_type][0]; 836 837 switch (block_type) { 838 case GC_HWIP: 839 ip_name = "gc"; 840 break; 841 case SDMA0_HWIP: 842 ip_name = "sdma"; 843 break; 844 case MP0_HWIP: 845 ip_name = "psp"; 846 break; 847 case MP1_HWIP: 848 ip_name = "smu"; 849 break; 850 case UVD_HWIP: 851 ip_name = "vcn"; 852 break; 853 default: 854 BUG(); 855 } 856 857 maj = IP_VERSION_MAJ(version); 858 min = IP_VERSION_MIN(version); 859 rev = IP_VERSION_REV(version); 860 861 snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev); 862 } 863